JP4783595B2 - 半導体素子のdram製造方法 - Google Patents
半導体素子のdram製造方法 Download PDFInfo
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- JP4783595B2 JP4783595B2 JP2005202899A JP2005202899A JP4783595B2 JP 4783595 B2 JP4783595 B2 JP 4783595B2 JP 2005202899 A JP2005202899 A JP 2005202899A JP 2005202899 A JP2005202899 A JP 2005202899A JP 4783595 B2 JP4783595 B2 JP 4783595B2
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- 239000004065 semiconductor Substances 0.000 title claims description 72
- 238000004519 manufacturing process Methods 0.000 title claims description 37
- 239000000758 substrate Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 20
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 2
- 230000005524 hole trap Effects 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 229910019001 CoSi Inorganic materials 0.000 claims 1
- 229910005883 NiSi Inorganic materials 0.000 claims 1
- 230000007423 decrease Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- PWPJGUXAGUPAHP-UHFFFAOYSA-N lufenuron Chemical compound C1=C(Cl)C(OC(F)(F)C(C(F)(F)F)F)=CC(Cl)=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F PWPJGUXAGUPAHP-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010893 electron trap Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910019044 CoSix Inorganic materials 0.000 description 1
- 229910005889 NiSix Inorganic materials 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
Description
図1に示されているように、従来の技術に係るDRAMセルは半導体基板10の上部に素子分離膜20と深いn−ウェル15及びp−ウェル25を含む。さらに、ゲート酸化膜40及びゲート電極45の積層構造を含み、ゲート電極45の下部の半導体基板10にチャンネル領域35を備えている。ゲート電極45の両側の半導体基板10にはソース/ドレーン領域30が備えられている。
「DRAMのリテンションタイム分配に関する研究("On the Retention Time Distribution of Dynamic Random Access Memory (DRAM)) "、 p. 1300〜1309、 IEEE ED-45、 No. 6、 1999 「規格化されたプログラミング電圧を有し、リテンション信頼性が強化されたSONOS NVSM("Retention reliability enhanced SONOS NVSM with scaled programming voltage) "、 Aerospace Conference Proceedings、 9-16 March、 2002、 p. 5-2383〜5-2390、 vol. 5
110 素子分離膜
120、140 n−ウェル
130、150 p−ウェル
160 セルチャンネル領域
170 pMOSチャンネル領域
180 nMOSチャンネル領域
200 下部ゲート酸化膜
210 中間ゲート絶縁膜
220 バッファ酸化膜
230 上部ゲート酸化膜
240 導電層パターン
250 CVD絶縁膜パターン
1000a 第1の領域
1000b 第2の領域
1000b−1 pMOS領域
1000b−2 nMOS領域
Claims (14)
- (a)セル領域である第1の領域と、pMOS領域及びnMOS領域を備えた第2の領域と、前記第1及び第2の領域に備えられたチャンネル領域とを含む半導体基板を提供する段階と、
(b)前記半導体基板の上部に下部ゲート酸化膜、電子/正孔トラップを含む中間ゲート絶縁膜及びバッファ酸化膜を順次形成する段階と、
(c)前記第2の領域のpMOS領域及びnMOS領域のうち、少なくともnMOS領域のバッファ酸化膜及び中間ゲート絶縁膜を取り除き、前記第2の領域の一部の下部ゲート酸化膜を露出させる段階と、
(d)少なくとも所定厚さの前記バッファ酸化膜、及び前記第2の領域の露出した下部ゲート酸化膜の全てを取り除く段階と、
(e)前記中間ゲート絶縁膜の上部、及び前記第2の領域のpMOS領域及びnMOS領域のうち少なくともnMOS領域の半導体基板の上部に上部ゲート酸化膜を形成する段階と、
(f)前記第1及び第2の領域の前記上部ゲート酸化膜にゲート電極パターンを形成する段階とを含むことを特徴とする半導体素子のDRAM製造方法。 - 前記(a)段階は
前記半導体基板の上部に活性領域を定義する素子分離膜を形成する段階と、
前記第1の領域に深いn−ウェル及びセルp−ウェルを形成する段階と、
前記第2の領域にn−ウェル及びp−ウェルを形成してそれぞれの前記pMOS領域及びnMOS領域を定義する段階と、
前記第1及び第2の領域に前記チャンネル領域をそれぞれ形成する段階とを含むことを特徴とする請求項1に記載の半導体素子のDRAM製造方法。 - 前記下部ゲート絶縁膜の厚さは100Å以下であることを特徴とする請求項1に記載の半導体素子のDRAM製造方法。
- 前記中間ゲート絶縁膜は窒化膜、Al2O3膜、HfO2膜及びその組合せのうち選択されたいずれか一つであることを特徴とする請求項1に記載の半導体素子のDRAM製造方法。
- 前記中間ゲート絶縁膜の厚さは5〜100Åであることを特徴とする請求項1及び4のいずれかに記載の半導体素子のDRAM製造方法。
- 前記第1の領域の上部ゲート酸化膜の厚さは10〜400Åの厚さを有する第2の領域の上部ゲート酸化膜の厚さと同一であるか薄いことを特徴とする請求項1に記載の半導体素子のDRAM製造方法。
- 前記(f)段階は
前記半導体基板の上部にゲート電極用導電層及びCVD絶縁膜の積層構造を形成する段階と、
前記積層構造をパターニングし、前記ゲート電極パターンを形成する段階とを含むことを特徴とする請求項1に記載の半導体素子のDRAM製造方法。 - 前記ゲート電極用導電層は多結晶シリコン層及び多結晶SiGe層のうち選択されたいずれか一つを含む下部導電層及びWSiX層、NiSiX層、CoSiX層、WN/W層及びTiN/W層のうち選択されたいずれか一つを含む上部導電層の積層構造で形成することを特徴とする請求項7に記載の半導体素子のDRAM製造方法。
- 前記積層構造パターニング工程は少なくとも前記第1の領域及び前記第2の領域のpMOS領域の上部ゲート酸化膜及び中間ゲート絶縁膜をパターニングする段階をさらに含むことを特徴とする請求項7に記載の半導体素子のDRAM製造方法。
- 前記ゲート電極パターンの両側の半導体基板にソース/ドレーン領域を形成する段階をさらに含むことを特徴とする請求項1に記載の半導体素子のDRAM製造方法。
- 前記第2の領域は、コア/周辺回路領域を含むことを特徴とする請求項1に記載の半導体素子のDRAM製造方法。
- 前記(c)段階は、前記第2の領域のpMOS領域及びnMOS領域のバッファ酸化膜及び中間ゲート絶縁膜を全て取り除く段階を含むことを特徴とする請求項1に記載の半導体素子のDRAM製造方法。
- 前記(c)段階は、前記第2の領域のnMOS領域のバッファ酸化膜及び中間ゲート絶縁膜だけを取り除く段階を含むことを特徴とする請求項1に記載の半導体素子のDRAM製造方法。
- 前記(d)段階は、前記バッファ酸化膜は所定厚さのみを取り除いて一定厚さが残るようにし、前記下部ゲート酸化膜は全て取り除くことを特徴とする請求項1に記載の半導体素子のDRAM製造方法。
Applications Claiming Priority (2)
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KR1020040059750A KR100702307B1 (ko) | 2004-07-29 | 2004-07-29 | 반도체 소자의 디램 및 그 제조 방법 |
KR2004-059750 | 2004-07-29 |
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JP2006041510A JP2006041510A (ja) | 2006-02-09 |
JP4783595B2 true JP4783595B2 (ja) | 2011-09-28 |
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JP2005202899A Expired - Fee Related JP4783595B2 (ja) | 2004-07-29 | 2005-07-12 | 半導体素子のdram製造方法 |
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US (2) | US7229881B2 (ja) |
JP (1) | JP4783595B2 (ja) |
KR (1) | KR100702307B1 (ja) |
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US7552584B2 (en) * | 2006-03-31 | 2009-06-30 | Caterpillar Inc. | Common engine and exhaust treatment fuel system |
KR100870321B1 (ko) | 2006-09-29 | 2008-11-25 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
US8071440B2 (en) * | 2008-12-01 | 2011-12-06 | United Microelectronics Corporation | Method of fabricating a dynamic random access memory |
EP4350345A2 (en) | 2011-06-23 | 2024-04-10 | Ablynx N.V. | Techniques for predicting, detecting and reducing aspecific protein interference in assays involving immunoglobin single variable domains |
CN106129011A (zh) * | 2016-09-27 | 2016-11-16 | 上海华力微电子有限公司 | 一种改善sonos结构嵌入式闪存性能的方法 |
CN106298680A (zh) * | 2016-10-24 | 2017-01-04 | 上海华力微电子有限公司 | Sonos结构嵌入式闪存的制造方法 |
CN113629009B (zh) * | 2021-08-09 | 2023-10-24 | 长鑫存储技术有限公司 | 半导体硅化钴膜层的制造方法、半导体器件及存储器 |
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2004
- 2004-07-29 KR KR1020040059750A patent/KR100702307B1/ko not_active IP Right Cessation
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2005
- 2005-06-24 US US11/165,180 patent/US7229881B2/en not_active Expired - Fee Related
- 2005-07-12 JP JP2005202899A patent/JP4783595B2/ja not_active Expired - Fee Related
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2006
- 2006-11-22 US US11/603,054 patent/US20070066016A1/en not_active Abandoned
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Publication number | Publication date |
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KR100702307B1 (ko) | 2007-03-30 |
KR20060011078A (ko) | 2006-02-03 |
JP2006041510A (ja) | 2006-02-09 |
US20070066016A1 (en) | 2007-03-22 |
US20060024888A1 (en) | 2006-02-02 |
US7229881B2 (en) | 2007-06-12 |
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