JP4759381B2 - Device-embedded circuit board and manufacturing method thereof - Google Patents

Device-embedded circuit board and manufacturing method thereof Download PDF

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JP4759381B2
JP4759381B2 JP2005358577A JP2005358577A JP4759381B2 JP 4759381 B2 JP4759381 B2 JP 4759381B2 JP 2005358577 A JP2005358577 A JP 2005358577A JP 2005358577 A JP2005358577 A JP 2005358577A JP 4759381 B2 JP4759381 B2 JP 4759381B2
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wiring
recess
insulator layer
circuit board
metal foil
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JP2007165502A (en
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敏 中尾
浩二 加本
一樹 新保
徹 斉藤
昇次 有泉
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Yamaichi Electronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Abstract

<P>PROBLEM TO BE SOLVED: To provide an element-incorporated circuit board which is reliable and can be made highly functional and compact, and to provide its manufacturing method. <P>SOLUTION: The element-incorporated circuit board comprises an interlayer insulation layer 1 formed of thermoplastic resin, a first interconnection circuit 2 formed on one principal plane of the interlayer insulation layer 1, and a second interconnection circuit 3 formed on the other principal plane of the interlayer insulation layer 1. The interconnection 3a of the second interconnection circuit 3 includes a convex portion 4 which penetrates through the interlayer insulation layer 1 and is exposed on the one principal plane. The interconnection 3b of the second interconnection circuit 3 includes a concave portion 5 encompassed by the interconnection insulation layer 1. On the bottom of the concave portion 5, a semiconductor chip 8 is mounted via a plating layer 6. A bonding wire 9 connects an electrode pad of the semiconductor chip 8 and the convex portion 4. A sealing resin 10 is formed on the entire surface by sealing the semiconductor chip 8 in the concave portion 5 and covering the first interconnection circuit 2. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

本発明は、素子内蔵回路基板およびその製造方法に係り、詳しくは機能素子から成る電子部品を収容した両面銅張積層板から成る素子内蔵回路基板とその製造方法に関する。   The present invention relates to a circuit board with a built-in element and a manufacturing method thereof, and more particularly to a circuit board with a built-in element composed of a double-sided copper-clad laminate containing electronic components composed of functional elements and a manufacturing method thereof.

携帯機器類のような電子機器の短小軽薄化に伴い、電子部品の実装される回路基板では、その高密度配線化および短小軽薄化が強く要求され、それに対応した多層配線板が種々に開発されている。例えば両面銅張積層板を内層基板とし、その両側に外層として層間絶縁体層と配線パターン層(配線回路)を積層する多層配線板が実用に供されている。ここで、上記両面銅張積層板は、熱硬化性樹脂から成る層間絶縁体層の両面に銅箔を配置し加熱加圧により一体化したものである。また、上記層間絶縁体層としては、通常、配線回路間の電気的な絶縁及び機械的な支持等の機能を呈するガラスエポキシ系、ポリエステル樹脂系、ポリイミド樹脂系等の熱硬化性樹脂が用いられる。なお、この多層配線板の各層の配線回路間は、それぞれ介挿する層間絶縁体層を貫通する導電体で電気的に接続される。   As electronic devices such as portable devices become shorter, lighter and thinner, circuit boards on which electronic components are mounted are strongly required to have higher density wiring and shorter, lighter and thinner, and various multilayer wiring boards have been developed. ing. For example, a multilayer wiring board in which a double-sided copper-clad laminate is used as an inner layer substrate and an interlayer insulator layer and a wiring pattern layer (wiring circuit) are laminated as outer layers on both sides thereof is put into practical use. Here, the double-sided copper-clad laminate is obtained by arranging copper foils on both sides of an interlayer insulator layer made of a thermosetting resin and integrating them by heating and pressing. Further, as the interlayer insulator layer, a thermosetting resin such as a glass epoxy type, a polyester resin type, a polyimide resin type or the like that normally exhibits functions such as electrical insulation between wiring circuits and mechanical support is used. . In addition, the wiring circuits of each layer of the multilayer wiring board are electrically connected by a conductor penetrating an interlayer insulating layer interposed therebetween.

そして、この種の多層配線板では、トランジスタ、ダイオード、IC等の能動素子から成る例えば半導体パッケージ部品、あるいは抵抗体、コンデンサ等の受動素子から成る電子部品は、通常では多層配線板の最上層の配線回路面に表面実装される。以下、このような能動素子の電子部品(能動素子部品ともいう)および受動素子の電子部品(受動素子部品ともいう)をあわせて機能素子部品と呼称する。   In this type of multilayer wiring board, for example, semiconductor package parts made of active elements such as transistors, diodes, and ICs, or electronic parts made of passive elements such as resistors and capacitors are usually placed on the uppermost layer of the multilayer wiring board. Surface mounted on the wiring circuit surface. Hereinafter, such an electronic component of an active element (also referred to as an active element component) and an electronic component of a passive element (also referred to as a passive element component) are collectively referred to as a functional element component.

更に回路基板への機能素子部品の実装密度を上げるために、多層配線板の層間絶縁体層の一部に貫通孔を穿設し、この貫通孔内に抵抗チップ、コンデンサ、インダクタンス等の受動素子部品を収納した構成をとる多層配線板が開発されている(例えば、特許文献1参照)。あるいは、上記多層配線板の層間絶縁体層の一部に凹所あるいはキャビティを設け、その中に例えば半導体ベアチップあるいはICチップ封止のCSP(チップサイズパッケージ)のような能動素子部品を収納する多層配線板も種々に提案されている(例えば、特許文献2参照)。ここで、上記凹所あるいはキャビティの占める表面積は上記貫通孔の占める表面積に比べてかなり広いものになる。   Furthermore, in order to increase the mounting density of functional element parts on the circuit board, a through hole is formed in a part of the interlayer insulating layer of the multilayer wiring board, and a passive element such as a resistor chip, a capacitor, and an inductance is formed in the through hole. A multilayer wiring board having a configuration in which components are accommodated has been developed (see, for example, Patent Document 1). Alternatively, a recess or a cavity is provided in a part of the interlayer insulator layer of the multilayer wiring board, and a multilayer in which an active element component such as a semiconductor bare chip or an IC chip encapsulated CSP (chip size package) is accommodated. Various wiring boards have also been proposed (see, for example, Patent Document 2). Here, the surface area occupied by the recess or cavity is considerably larger than the surface area occupied by the through hole.

このようにして、素子内蔵回路基板は、機能素子部品を配線板の層間絶縁体層中に収納することにより、表面実装領域面あるいは配線領域面が広く設定できるようになる。このため、高密度配線化及び高密度実装化が更に促進され、回路基板の高機能化やコンパクト化が容易に図れるようになる。
特開2000−340955号公報 特開2003−188314号公報
In this way, the circuit board with a built-in element can set the surface mounting area surface or the wiring area surface widely by housing the functional element parts in the interlayer insulator layer of the wiring board. For this reason, high-density wiring and high-density mounting are further promoted, and the circuit board can be easily enhanced in function and size.
JP 2000-340955 A JP 2003-188314 A

上記素子内蔵回路基板への機能素子部品の収納において、機能素子と配線回路をワイヤーボンディングにより電気接続する場合には、層間絶縁体層はワイヤーボンディングの熱押圧に耐える所要の硬度を具備する必要がある。そこで、層間絶縁体層としては、アルミナ等のセラミックスやガラスが主体の無機系材料、ガラスエポキシ樹脂系あるいはポリイミド樹脂系等の熱硬化性樹脂材料、そしてこれらのコンポジット系材料が好適になる。   In storing functional element parts on the above-described element built-in circuit board, when the functional element and the wiring circuit are electrically connected by wire bonding, the interlayer insulator layer needs to have a required hardness to withstand the heat pressing of wire bonding. is there. Therefore, as the interlayer insulator, inorganic materials mainly composed of ceramics such as alumina or glass, thermosetting resin materials such as glass epoxy resin or polyimide resin, and composite materials thereof are suitable.

しかしながら、層間絶縁体層に上記所要の硬度を確保できる無機系材料、熱硬化性樹脂材料あるいはコンポジット系材料を使用する構成の場合は、多層配線板の外層の接合とその一体化のため接着剤を介在させることが必須になり回路基板の製造工程が煩雑化する。また、接着剤の介挿による接合と一体化は、接着剤の流動等の招来を伴い、信頼性の低下や不良品の発生を起し易い。更に、無機系材料、ガラスエポキシ樹脂系材料あるいはコンポジット系材料の場合は、可撓性(フレキシブリディ)が悪いために取り扱い難く、ときには配線層が剥離する。このために、回路基板の信頼性の低下や不良品の発生が助長され、歩留まりや生産性の点で実用上問題があった。   However, in the case of a structure using an inorganic material, a thermosetting resin material or a composite material capable of ensuring the required hardness for the interlayer insulator layer, an adhesive for joining and integrating the outer layers of the multilayer wiring board It becomes essential to intervene, and the manufacturing process of the circuit board becomes complicated. Moreover, joining and integration by the insertion of an adhesive are accompanied by the flow of the adhesive and the like, and are liable to cause a decrease in reliability and generation of defective products. Furthermore, in the case of an inorganic material, a glass epoxy resin material, or a composite material, it is difficult to handle due to poor flexibility, and sometimes the wiring layer peels off. For this reason, a decrease in the reliability of the circuit board and the generation of defective products are promoted, and there are practical problems in terms of yield and productivity.

また、上記無機系材料、熱硬化性樹脂材料あるいはコンポジット系材料から成る層間絶縁体層では、上記素子部品を収納する凹所あるいはキャビティを穿設するために、層間絶縁体層の広い領域をレーザ加工する必要が生じる。ここで、レーザとしてはUV(遠紫外)−YAG(Yttrium Aluminum Garnet)レーザあるいは炭酸ガスレーザのような高出力レーザが必要になる。このために、上記素子内蔵回路基板の製造工程が煩雑化することから製造コストが増加し、安価な素子内蔵回路基板の生産が難しいという問題が生じていた。   Further, in the interlayer insulator layer made of the inorganic material, thermosetting resin material, or composite material, a wide area of the interlayer insulator layer is formed by laser in order to make a recess or cavity for housing the element component. Need to be processed. Here, a high-power laser such as a UV (far ultraviolet) -YAG (Yttrium Aluminum Garnet) laser or a carbon dioxide laser is required as the laser. For this reason, the manufacturing process of the circuit board with a built-in element becomes complicated, resulting in an increase in manufacturing cost and a difficulty in producing an inexpensive circuit board with a built-in element.

本発明は、上述の事情に鑑みてなされたもので、信頼性が高く、高機能化およびコンパクト化が可能で低コストの素子内蔵回路基板およびその製造方法を提供することを目的とする。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a low-cost element-embedded circuit board that is highly reliable, highly functional and compact, and a manufacturing method thereof.

上記目的を達成するために、本発明に係る素子内蔵回路基板は、金属箔で形成された第1の配線回路と、金属箔で形成された第2の配線回路と、一主面に前記第1の配線回路を積層し、他主面に前記第2の配線回路を積層し前記第2の配線回路の一部が前記一主面側に露出するように形成した熱可塑性樹脂から成る絶縁体層であって、前記第2の配線回路の前記一主面側に露出する一部を底部として機能素子を収納可能な第1の凹所を形成している絶縁体層とを具備し、前記第1の凹所の底部に露出する前記第2の配線回路の一配線に前記機能素子が装着され、且つ、前記絶縁体層の前記一主面側に露出し前記一配線と同一金属箔でできた前記第2の配線回路の他配線と前記機能素子がボンディングワイヤーで接続されている構成になっている。 In order to achieve the above object, an element-embedded circuit board according to the present invention includes a first wiring circuit formed of a metal foil, a second wiring circuit formed of a metal foil, and the first wiring circuit formed on a main surface. An insulating body made of a thermoplastic resin formed by laminating one wiring circuit and laminating the second wiring circuit on the other main surface so that a part of the second wiring circuit is exposed on the one main surface side An insulating layer forming a first recess capable of accommodating a functional element with a part exposed on the one main surface side of the second wiring circuit as a bottom portion, The functional element is attached to one wiring of the second wiring circuit exposed at the bottom of the first recess, and is exposed on the one main surface side of the insulator layer and is the same metal foil as the one wiring. other wiring and the functional element of the second wiring circuits that could have been a configuration that is connected with a bonding wire .

上記発明により、素子内蔵回路基板は、熱可塑性樹脂により形成されることから、可撓性に優れ、信頼性が高く、しかも高歩留まりに生産できるようになり実用性に優れたものになる。また、上記素子内蔵回路基板は、第1の配線回路および第2の配線回路の所要の領域において、種々の電子部品を自在に実装することができるようになる。このために、機能素子等の電子部品の高密度実装が極めて容易になり、回路基板の更なる高機能化およびコンパクト化が可能となる。   According to the above invention, since the circuit board with a built-in element is formed of a thermoplastic resin, it is excellent in flexibility, high reliability, and can be produced at a high yield, so that it has excellent practicality. The element-embedded circuit board can freely mount various electronic components in required regions of the first wiring circuit and the second wiring circuit. For this reason, high-density mounting of electronic components such as functional elements becomes extremely easy, and the circuit board can be further enhanced in function and size.

そして、本発明にかかる素子内蔵回路基板の製造方法は、機能素子を内部に収納した素子内蔵回路基板の製造方法であって、第1の金属箔の表面を選択的にエッチングし複数の凹部および凸部を形成する工程と、前記凹部と凸部を形成した前記第1の金属箔の表面側に、熱可塑性樹脂から成る絶縁体層と第2の金属箔とをこの順に積層配置する工程と、前記積層配置した積層体の加熱加圧により一体化し、前記凹部に前記絶縁体層を充填し前記凸部を前記絶縁体層の一主面まで貫挿させる工程と、前記第1の金属箔および前記第2の金属箔を選択的にエッチングし、前記第2の金属箔から成る第1の配線回路を前記絶縁体層の一主面に形成すると共に前記凸部を露出させ、更に前記第1の金属箔から成る第2の配線回路を前記絶縁体層の他主面に形成する工程と、前記第2の配線回路の一配線の前記凸部を前記絶縁体層の一主面側から所定の深さにエッチングし第1の凹所を形成する工程と、前記第1の凹所の前記一配線に機能素子を装着する工程と、前記機能素子と前記第2の配線回路の他配線の前記凸部の上面にワイヤーボンディングする工程と、を有する構成になっている。   And the manufacturing method of the circuit board with a built-in element concerning this invention is a manufacturing method of the circuit board with a built-in element which accommodated the functional element inside, Comprising: The surface of the 1st metal foil was selectively etched, and several recessed parts and A step of forming a convex portion, and a step of laminating and arranging an insulating layer made of a thermoplastic resin and a second metal foil in this order on the surface side of the first metal foil on which the concave portion and the convex portion are formed. A step of integrating the laminated body arranged by heating and pressurizing, filling the concave portion with the insulator layer, and penetrating the convex portion to one main surface of the insulator layer; and the first metal foil And selectively etching the second metal foil to form a first wiring circuit made of the second metal foil on one main surface of the insulator layer, exposing the convex portion, and further A second wiring circuit made of one metal foil is connected to the other insulator layer. Forming a first recess by etching the protrusion of one wiring of the second wiring circuit to a predetermined depth from one main surface side of the insulator layer, A step of attaching a functional element to the one wiring in one recess, and a step of wire bonding to the upper surface of the convex portion of the other wiring of the functional element and the second wiring circuit. .

上記発明により、機能素子が収納される第1の凹所は、配線回路を形成する銅箔のような金属の薄板のエッチング工程で形成できることから、素子内蔵回路基板の製造工程は極めて簡素化し、その製造コストが低減して安価な回路基板の生産が可能になる。   According to the above invention, the first recess in which the functional element is accommodated can be formed by the etching process of a thin metal plate such as a copper foil that forms the wiring circuit. The manufacturing cost is reduced, and an inexpensive circuit board can be produced.

また、第1の凹所に収納された機能素子と配線回路との電気接続において、ボンディングワイヤーは、その下部に熱可塑性樹脂から成る絶縁体層を有しない第2の配線回路の一配線にボンディングされる。このために、ワイヤーボンディング工程において素子内蔵回路基板を加熱しても、上記絶縁体層の熱変形の影響を受けることなく安定的なワイヤーボンディングが可能になる。   In addition, in the electrical connection between the functional element housed in the first recess and the wiring circuit, the bonding wire is bonded to one wiring of the second wiring circuit that does not have an insulator layer made of a thermoplastic resin underneath. Is done. For this reason, even if the circuit board with a built-in element is heated in the wire bonding step, stable wire bonding is possible without being affected by thermal deformation of the insulator layer.

あるいは、本発明にかかる素子内蔵回路基板の製造方法は、機能素子を内部に収納した素子内蔵回路基板の製造方法であって、第1の金属箔の表面を選択的にエッチングし複数の凹部および凸部を形成する工程と、前記凹部と凸部を形成した前記第1の金属箔の表面側に、熱可塑性樹脂から成る絶縁体層と第2の金属箔とをこの順に積層配置する工程と、前記積層配置した積層体の加熱加圧により一体化し、前記凹部に前記絶縁体層を充填し前記凸部を前記絶縁体層の一主面まで貫挿させる工程と、前記第1の金属箔および前記第2の金属箔を選択的にエッチングし、前記第2の金属箔から成る第1の配線回路を前記絶縁体層の一主面に形成すると共に前記凸部を露出させ、更に前記第1の金属箔から成る第2の配線回路を前記絶縁体層の他主面に形成する工程と、前記第2の配線回路の一配線の前記凸部を前記絶縁体層の一主面側から所定の深さにエッチングし第1の凹所を形成する工程と、前記第2の配線回路の他配線の前記凸部を前記絶縁体層の一主面側から所定の深さにエッチングし第2の凹所を形成する工程と、前記第1の凹所の前記一配線に機能素子を装着する工程と、前記機能素子と前記第2の凹所の前記他配線にワイヤーボンディングする工程と、を有する構成になっている。   Alternatively, the method for manufacturing a circuit board with a built-in element according to the present invention is a method for manufacturing a circuit board with a built-in element in which a functional element is housed, and the surface of the first metal foil is selectively etched to form a plurality of recesses and A step of forming a convex portion, and a step of laminating and arranging an insulating layer made of a thermoplastic resin and a second metal foil in this order on the surface side of the first metal foil on which the concave portion and the convex portion are formed. A step of integrating the laminated body arranged by heating and pressurizing, filling the concave portion with the insulator layer, and penetrating the convex portion to one main surface of the insulator layer; and the first metal foil And selectively etching the second metal foil to form a first wiring circuit made of the second metal foil on one main surface of the insulator layer, exposing the convex portion, and further A second wiring circuit made of one metal foil is connected to the insulating layer. Forming a first recess by etching the protrusion of one wiring of the second wiring circuit to a predetermined depth from one main surface side of the insulator layer; Etching the protrusions of the other wiring of the second wiring circuit to a predetermined depth from one main surface side of the insulator layer to form a second recess; and the one of the first recesses The method includes a step of attaching a functional element to the wiring, and a step of wire bonding to the functional element and the other wiring of the second recess.

上記発明により、ボンディングワイヤーは、絶縁体層に設けた第1の凹所の第2の配線回路上に装着した機能素子と、絶縁体層に設けた第2の凹所を介し第1の配線回路より低位置の第2の配線回路の配線との間でボンディングされるようになる。このために、ボンディングワイヤーの高さが低ループになり、上記機能素子を封止するための封止材料の厚さを薄くすることが可能になる。そして、ICカードのような携帯機器を更に軽薄化しコンパクトなものにする。   According to the invention, the bonding wire includes the functional element mounted on the second wiring circuit of the first recess provided in the insulator layer, and the first wiring through the second recess provided in the insulator layer. Bonding is performed with the wiring of the second wiring circuit located lower than the circuit. For this reason, the height of the bonding wire becomes a low loop, and the thickness of the sealing material for sealing the functional element can be reduced. In addition, portable devices such as IC cards are made thinner and more compact.

あるいは、本発明にかかる素子内蔵回路基板の製造方法は、機能素子を内部に収納した素子内蔵回路基板の製造方法であって、第1の金属箔の表面を選択的にエッチングしその断面形状が順テーパーである複数の凹部と凸部を形成する工程と、前記凹部と凸部を形成した前記第1の金属箔の表面側に、熱可塑性樹脂から成る絶縁体層と第2の金属箔とをこの順に積層配置する工程と、前記積層配置した積層体の加熱加圧により一体化し、前記凹部に前記絶縁体層を充填し前記凸部を前記絶縁体層の一主面まで貫挿させる工程と、前記第1の金属箔および前記第2の金属箔を選択的にエッチングして、前記第1の金属箔から成る第1の配線回路を前記絶縁体層の他主面に形成し、前記第2の金属箔から成る第2の配線回路を前記絶縁体層の一主面に形成し、更に前記第1の金属箔の前記凸部を除去することにより前記第2の配線回路の一配線および他配線上にそれぞれ第1の凹所と第1の凹所を形成する工程と、前記第1の凹所の前記一配線に機能素子を装着する工程と、前記機能素子と前記第2の凹所の前記他配線にワイヤーボンディングする工程と、を有する構成になっている。   Alternatively, the method for manufacturing a circuit board with a built-in element according to the present invention is a method for manufacturing a circuit board with a built-in element in which a functional element is housed, and the surface of the first metal foil is selectively etched to have a cross-sectional shape. A step of forming a plurality of concave portions and convex portions which are forward tapered, and an insulating layer made of a thermoplastic resin and a second metal foil on the surface side of the first metal foil on which the concave portions and the convex portions are formed. Are stacked in this order and integrated by heating and pressurization of the stacked stack, and the recess is filled with the insulator layer and the protrusion is inserted through one main surface of the insulator layer. And selectively etching the first metal foil and the second metal foil to form a first wiring circuit made of the first metal foil on the other main surface of the insulator layer, The second wiring circuit made of the second metal foil is mainly used as the insulator layer. Forming the first recess and the first recess on one wiring and the other wiring of the second wiring circuit by removing the convex portion of the first metal foil. And a step of attaching a functional element to the one wiring of the first recess, and a step of wire bonding to the functional element and the other wiring of the second recess.

上記発明により、発光素子のような機能素子の収納される第1の凹所の断面形状が順テーパーになるよう容易に制御される。しかも、第1の凹所の断面は、光反射率が極めて高くなる白色の液晶ポリマーから成る絶縁体層により構成される。このために、発光素子を収納した素子内蔵回路基板は上記断面において発光を高反射させ出射光率を増大させる。そして、例えば波長変換型LEDの白色光から成るコンパクトな液晶表示機器用バックライトに極めて好適になる。その他に、短小軽薄な携帯機器の表示装置あるいは照明装置としても極めて有効になる。   According to the above invention, the cross-sectional shape of the first recess in which the functional element such as the light emitting element is accommodated is easily controlled so as to have a forward taper. Moreover, the cross section of the first recess is constituted by an insulator layer made of a white liquid crystal polymer that has extremely high light reflectance. For this reason, the element-embedded circuit board containing the light-emitting elements highly reflects light emission in the cross section and increases the outgoing light rate. For example, it is extremely suitable for a backlight for a compact liquid crystal display device made of white light of a wavelength conversion type LED. In addition, it is extremely effective as a display device or lighting device for short, small and light portable devices.

本発明の構成により、信頼性が高く、高機能化およびコンパクト化が可能で低コストの素子内蔵回路基板およびその製造方法を提供することができる。   According to the configuration of the present invention, it is possible to provide a low-cost circuit board with a built-in element and a manufacturing method thereof that are highly reliable, capable of high functionality and compactness.

以下に本発明の好適な実施形態のいくつかについて図面を参照して説明する。ここで、互いに同一または類似の部分には共通の符号を付している。
(第1の実施形態)
本発明の第1の実施形態に係る素子内蔵回路基板およびその製造方法について図1ないし4を参照して説明する。図1は素子内蔵回路基板の一態様を示す要部断面図である。そして、図2ないし4は上記素子内蔵回路基板の製造方法を示す工程別回路基板断面図である。
Several preferred embodiments of the present invention will be described below with reference to the drawings. Here, the same or similar parts are denoted by common reference numerals.
(First embodiment)
An element-embedded circuit board and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view of a main part showing one embodiment of a circuit board with a built-in element. 2 to 4 are cross-sectional views of the circuit board according to the process showing the method of manufacturing the element-embedded circuit board.

図1において、素子内蔵回路基板は、熱可塑性樹脂から成る層間絶縁体層1、該層間絶縁体層1の一主面に形成された第1の配線回路2、層間絶縁体層1の他主面に形成された第2の配線回路3を有する。そして、第2の配線回路3の一の配線3aはその一部に凸部4を有し、該凸部4が層間絶縁体層1を貫挿し上記一主面に露出している。更に、第2の配線回路3の他の配線3bにはその一部に層間絶縁体層1により囲繞された凹所5が設けられている。   In FIG. 1, the circuit board with a built-in element includes an interlayer insulator layer 1 made of a thermoplastic resin, a first wiring circuit 2 formed on one main surface of the interlayer insulator layer 1, and other main layers of the interlayer insulator layer 1. It has the 2nd wiring circuit 3 formed in the surface. One wiring 3a of the second wiring circuit 3 has a convex portion 4 in a part thereof, and the convex portion 4 penetrates the interlayer insulating layer 1 and is exposed on the one main surface. Further, the other wiring 3 b of the second wiring circuit 3 is provided with a recess 5 surrounded by the interlayer insulating layer 1 in a part thereof.

ここで、上記配線3aの凸部4の表面、凹所5底部の配線3bの表面に、例えばニッケル(Ni)/金(Au)あるいはNi/銀(Ag)の複合層から成るメッキ層6がそれぞれに施されている。同様に、上記第1の配線回路2および第2の配線回路3を被覆するメッキレジスト7の開口部にも上記複合層から成るメッキ層6が施されている。   Here, a plating layer 6 made of a composite layer of nickel (Ni) / gold (Au) or Ni / silver (Ag), for example, is formed on the surface of the protrusion 4 of the wiring 3a and the surface of the wiring 3b at the bottom of the recess 5. It is given to each. Similarly, the plating layer 6 made of the composite layer is also applied to the opening of the plating resist 7 covering the first wiring circuit 2 and the second wiring circuit 3.

そして、上記凹所5底部の配線3bから成るランド部に半導体チップ8が装着(マウント)され、ボンディングワイヤー9が半導体チップ8の電極パッド(不図示)と上記凸部4に接続されている。更に、封止樹脂10が、上記半導体チップ8を上記凹所5に封止し上記第1の配線回路2を被覆するように全面に形成されている。このようにして、本実施形態の素子内蔵回路基板は、能動素子あるいは受動素子を有する半導体チップ8を収納し内蔵する。   A semiconductor chip 8 is mounted (mounted) on a land portion composed of the wiring 3 b at the bottom of the recess 5, and a bonding wire 9 is connected to an electrode pad (not shown) of the semiconductor chip 8 and the convex portion 4. Further, a sealing resin 10 is formed on the entire surface so as to seal the semiconductor chip 8 in the recess 5 and cover the first wiring circuit 2. In this manner, the element built-in circuit board of the present embodiment accommodates and incorporates the semiconductor chip 8 having active elements or passive elements.

上記実施形態において、層間絶縁体層1に使用する熱可塑性樹脂としては、例えば液晶ポリマー(LCP)、フェノキシ樹脂、ポリエーテルスルフォン樹脂、ポリスルフォン樹脂、ポリフェニレンスルフォン樹脂、ポリフェニレンサルファイド樹脂、ポリフェニールエーテル樹脂、ポリエーテルイミド樹脂、熱可塑性ポリイミド樹脂、ポリテトラフロロエチレン樹脂等が挙げられる。特に、上記LCPは、耐熱性、誘電率の高い安定性を有しており極めて好適である。   In the said embodiment, as a thermoplastic resin used for the interlayer insulator layer 1, liquid crystal polymer (LCP), a phenoxy resin, a polyether sulfone resin, a polysulfone resin, a polyphenylene sulfone resin, a polyphenylene sulfide resin, a polyphenyl ether resin, for example. , Polyetherimide resin, thermoplastic polyimide resin, polytetrafluoroethylene resin, and the like. In particular, the LCP is extremely suitable because it has high heat resistance and high dielectric constant stability.

また、上記第1の配線回路2および第2の配線回路3は、素子内蔵回路基板の製造方法において後述するように銅箔のような金属箔(金属薄板も含む)により形成されると好適である。   Further, the first wiring circuit 2 and the second wiring circuit 3 are preferably formed of a metal foil (including a metal thin plate) such as a copper foil as will be described later in the method of manufacturing an element-embedded circuit board. is there.

次に、上記素子内蔵回路基板の製造方法を説明する。図2(a)に示すように、先ず厚さが50〜100μmの第1の銅箔11を用意する。そして、第1の銅箔11の表面に所定パターンを有するエッチングレジスト12を形成し、更に第1の銅箔11の裏側の全面を被覆するエッチングレジスト13を形成する。ここで、上記エッチングレジストは、公知の感光性樹脂膜のスピン塗布法あるいはスクリーン印刷法による成膜と、その露光・現像とによる所要のパターニングにより形成される。   Next, a method for manufacturing the element-embedded circuit board will be described. As shown in FIG. 2A, first, a first copper foil 11 having a thickness of 50 to 100 μm is prepared. Then, an etching resist 12 having a predetermined pattern is formed on the surface of the first copper foil 11, and an etching resist 13 that covers the entire back side of the first copper foil 11 is formed. Here, the etching resist is formed by a required patterning by a known photosensitive resin film formed by spin coating or screen printing, and exposure / development.

次に、例えば塩化第二銅水溶液あるいは塩化鉄水溶液からなる化学薬液のエッチング液に浸漬し、上記エッチングレジスト12,13をエッチングマスクにして、上記第1の銅箔11をエッチング加工する。このようにして、図2(b)に示すように、上記半導体チップ8の厚さと同程度になるように、例えば深さが30〜80μm程度の凹部14を第1の銅箔11aの表面に形成する。ここで、上記エッチング液としては、特に塩化第二鉄水溶液が好適である。このエッチング液を用いることにより、深い凹部14の側壁の形状を垂直に制御することが容易になる。更には、上記エッチング加工の後で硫酸−過酸化水素水溶液による処理、黒化処理等の化学研磨やバフやブラシ等の機械研磨を施すとよい。このような処理は、後述する両面銅張積層板の作製における層間絶縁体層と銅箔との密着力を向上させる。   Next, the first copper foil 11 is etched using the etching resists 12 and 13 as an etching mask by immersing in an etching solution of a chemical solution made of, for example, an aqueous cupric chloride solution or an aqueous iron chloride solution. In this manner, as shown in FIG. 2B, a recess 14 having a depth of, for example, about 30 to 80 μm is formed on the surface of the first copper foil 11a so as to be approximately the same as the thickness of the semiconductor chip 8. Form. Here, as the etching solution, a ferric chloride aqueous solution is particularly preferable. By using this etching solution, it becomes easy to control the shape of the side wall of the deep recess 14 vertically. Further, after the etching process, chemical polishing such as treatment with a sulfuric acid-hydrogen peroxide solution, blackening treatment, or mechanical polishing such as buffing or brushing may be performed. Such a treatment improves the adhesion between the interlayer insulator layer and the copper foil in the production of a double-sided copper-clad laminate described below.

次に、図2(c)に示すように、第1の銅箔11aの凹部14を形設した面側に凹部14とほぼ同等な厚み、例えば30〜80μm程度の熱可塑性樹脂であるLCPフィルム15を配置し、更に厚さ20〜35μmの第2の銅箔16を積層配置して積層体にする。ここで、LCPフィルム15としては、例えば住友化学社製のLCPキャスト(商品名)、クラレ社製のベクスター(商品名)等が好適に使用できる。   Next, as shown in FIG. 2 (c), an LCP film which is a thermoplastic resin having a thickness substantially equal to the concave portion 14, for example, about 30 to 80 μm, on the surface side where the concave portion 14 of the first copper foil 11a is formed. 15 is further arranged, and a second copper foil 16 having a thickness of 20 to 35 μm is further laminated to form a laminate. Here, as the LCP film 15, for example, LCP cast (trade name) manufactured by Sumitomo Chemical Co., Ltd., Bexter (trade name) manufactured by Kuraray Co., Ltd. and the like can be suitably used.

続いて、図2(d)に示すように、上記積層体の両銅箔11a、16面に当て板を配置して、樹脂圧として例えば30〜100kg/cm程度で加熱加圧して一体化し両面銅張積層板17を作製する。ここで、第1の銅箔11aの凸部はLCPフィルム15を貫挿し第2の銅箔16に達するようになる。 Then, as shown in FIG.2 (d), a contact plate is arrange | positioned on both the copper foils 11a and 16 surfaces of the said laminated body, and it heat-presses and integrates as resin pressure, for example at about 30-100 kg / cm < 2 >. A double-sided copper-clad laminate 17 is produced. Here, the convex portion of the first copper foil 11 a penetrates the LCP film 15 and reaches the second copper foil 16.

次に、図3(a)に示すように、両面銅張積層板17の表面に第1の配線回路2を有するエッチングレジスト18を形成し、更に両面銅張積層板17の裏側に第2の配線回路3を有するエッチングレジスト18を形成する。   Next, as shown in FIG. 3A, an etching resist 18 having the first wiring circuit 2 is formed on the surface of the double-sided copper-clad laminate 17, and further, a second side is formed on the back side of the double-sided copper-clad laminate 17. An etching resist 18 having the wiring circuit 3 is formed.

そして、例えば塩化第二銅水溶液、塩化鉄水溶液、硫酸−過酸化水素水溶液等のエッチング液に浸漬し、上記エッチングレジスト18,19をエッチングマスクにして、両面銅張積層板17の両銅箔11a,16をエッチング加工する。銅箔11aと16との境界面に絶縁樹脂が若干介在する場合、バフやブラシ等の機械研磨やポリイミドエッチング液のような溶液による化学研磨を施すとよい。このようにして、図3(b)に示すように、第1の配線回路2、凸部4を有する配線3aそして凸部20を有する配線3bを形成する。   Then, the copper foils 11a of the double-sided copper clad laminate 17 are immersed in an etching solution such as a cupric chloride aqueous solution, an iron chloride aqueous solution, or a sulfuric acid-hydrogen peroxide aqueous solution, and the etching resists 18 and 19 are used as an etching mask. 16 are etched. When the insulating resin is slightly present at the interface between the copper foils 11a and 16, it is preferable to perform mechanical polishing such as buffing or brushing or chemical polishing using a solution such as a polyimide etching solution. In this way, as shown in FIG. 3B, the first wiring circuit 2, the wiring 3a having the convex portion 4, and the wiring 3b having the convex portion 20 are formed.

このようにした後、図3(c)に示すように、の配線回路2,3の形成された両面銅張積層板17の表面に凸部20を露出する所定パターンのエッチングレジスト21を形成し、更に両面銅張積層板17の裏側の全面を被覆するエッチングレジスト22を形成する。   Thereafter, as shown in FIG. 3C, an etching resist 21 having a predetermined pattern is formed on the surface of the double-sided copper-clad laminate 17 on which the wiring circuits 2 and 3 are formed so as to expose the protrusions 20. Further, an etching resist 22 that covers the entire back side of the double-sided copper-clad laminate 17 is formed.

そして、例えば塩化第二鉄水溶液から成る化学薬液を使用し、上記エッチングレジスト21,22をエッチングマスクにして両面銅張積層板17を上記化学薬液に浸漬し、配線3bの凸部20を所要の深さになるようにエッチングする。このようにして、図3(d)に示すように、配線3b上の一部に層間絶縁体層1により囲繞された凹所5が設けられる。図3(d)では、凹所5の深さは凹部14と同じになるように示しているが、上記所要の深さになるようにすればよい。凹所5の平面寸法は、収納される半導体チップ8のサイズに応じ、例えば10mm×10mmにも達する広いものとなる。   Then, for example, a chemical solution made of an aqueous ferric chloride solution is used, and the double-sided copper-clad laminate 17 is immersed in the chemical solution using the etching resists 21 and 22 as an etching mask. Etch to a depth. In this way, as shown in FIG. 3D, a recess 5 surrounded by the interlayer insulator layer 1 is provided in a part on the wiring 3b. In FIG. 3D, the depth of the recess 5 is shown to be the same as that of the recess 14, but it may be set to the required depth. The planar dimension of the recess 5 is as wide as, for example, 10 mm × 10 mm depending on the size of the semiconductor chip 8 to be accommodated.

次に、図4(a)に示すように、所定の領域を被覆するパターンを有するメッキレジスト7を形成する。ここで、メッキレジスト7は、公知の感光性樹脂膜のスピン塗布法あるいはスクリーン印刷法による成膜と、その露光・現像とによる所要のパターニングにより形成される。そして、上述した凸部4の表面、凹所5底部の配線3bの表面、および第1の配線回路2と第2の配線回路3の所定領域に、例えばNi/Auの複合層から成るメッキ層6を形成する。ここで、例えば3μm程度の厚さのNi層をメッキ形成し、その上に1μm程度の厚さのAu層をメッキ形成する。   Next, as shown in FIG. 4A, a plating resist 7 having a pattern covering a predetermined region is formed. Here, the plating resist 7 is formed by a required patterning by a known photosensitive resin film formed by spin coating or screen printing, and exposure / development. Then, a plating layer made of, for example, a composite layer of Ni / Au is formed on the surface of the convex portion 4, the surface of the wiring 3 b at the bottom of the recess 5, and a predetermined region of the first wiring circuit 2 and the second wiring circuit 3. 6 is formed. Here, for example, a Ni layer having a thickness of about 3 μm is formed by plating, and an Au layer having a thickness of about 1 μm is formed thereon by plating.

続いて、図4(b)に示すように、凹所5底部の配線3bから成るランド部のメッキ層6表面に、例えばAgペーストにより半導体チップ8を接着させて装着する。そして、図4(c)に示すように、半導体チップ8の電極パッド(不図示)と配線3aの凸部4のメッキ層6にボンディングワイヤー9を例えば超音波ボンディングにより接続させる。上記凸部4の表面寸法は、上記ボンディングワイヤー9をボンディングできる広さであればよく、例えば矩形の一辺が50μm〜100μm程度になっている。   Subsequently, as shown in FIG. 4B, the semiconductor chip 8 is attached to the surface of the plating layer 6 in the land portion composed of the wiring 3b at the bottom of the recess 5 by, for example, Ag paste. Then, as shown in FIG. 4C, a bonding wire 9 is connected to the electrode pad (not shown) of the semiconductor chip 8 and the plating layer 6 of the projection 4 of the wiring 3a by, for example, ultrasonic bonding. The surface dimension of the convex part 4 only needs to be large enough to bond the bonding wire 9. For example, one side of the rectangle is about 50 μm to 100 μm.

最後に、図1で示した封止樹脂10を全面に形成する。以上のようにして、第1の実施形態の素子内蔵回路基板が形成される。ここで、封止樹脂10は、エポキシ樹脂、アクリル樹脂等の熱硬化性樹脂であってもよいし、上記熱可塑性樹脂であってもよい。   Finally, the sealing resin 10 shown in FIG. 1 is formed on the entire surface. As described above, the circuit board with a built-in element according to the first embodiment is formed. Here, the sealing resin 10 may be a thermosetting resin such as an epoxy resin or an acrylic resin, or may be the above thermoplastic resin.

本実施形態では、層間絶縁体層1は熱可塑性樹脂により形成される。このために、素子内蔵回路基板は、可撓性に優れて取り扱い易く、回路基板としての信頼性が高く、しかも高歩留まりに生産できることから、極めて実用性に優れたものとなる。   In the present embodiment, the interlayer insulator layer 1 is formed of a thermoplastic resin. For this reason, the circuit board with a built-in element has excellent flexibility, is easy to handle, has high reliability as a circuit board, and can be produced at a high yield.

また、素子内蔵回路基板における半導体チップ8を収納する凹所5は、上記両面銅張積層板17を化学薬液に浸漬し、第1の銅箔11aの凸部20を所要の深さにエッチングして形成される。この場合、通常の配線回路のパターンを形成するための銅箔のエッチング装置をそのまま使用することができ、従来の技術で説明した層間絶縁体層の広い領域のレーザ加工は全く不要になる。このために、上記素子内蔵回路基板の製造工程は極めて簡素化し、その製造コストが低減して安価な回路基板の生産が可能になる。   The recess 5 for housing the semiconductor chip 8 in the circuit board with the built-in element immerses the double-sided copper-clad laminate 17 in a chemical solution, and etches the convex portion 20 of the first copper foil 11a to a required depth. Formed. In this case, the copper foil etching apparatus for forming a normal wiring circuit pattern can be used as it is, and the laser processing of the wide region of the interlayer insulating layer described in the prior art is completely unnecessary. For this reason, the manufacturing process of the circuit board with a built-in element is greatly simplified, the manufacturing cost is reduced, and an inexpensive circuit board can be produced.

また、上記凹所5に収納された半導体チップ8と配線回路との電気接続において、ボンディングワイヤー9は上記第2の配線回路3の一配線にワイヤーボンディングされる。このために、ワイヤーボンディング工程において素子内蔵回路基板を加熱しても、安定的なワイヤーボンディングが可能になる。これは、第1の配線回路の一配線にワイヤーボンディングするのと違って、その下部に熱可塑性樹脂がないからである。この熱可塑性樹脂から成る層間絶縁体層1上の第1の配線回路2にワイヤーボンディングする場合には、上記加熱において層間絶縁体層1が変形しやすくなるために、その上の第1の配線回路2とのボンディング不良が生じ易くなる。   Further, in the electrical connection between the semiconductor chip 8 accommodated in the recess 5 and the wiring circuit, the bonding wire 9 is wire-bonded to one wiring of the second wiring circuit 3. For this reason, even if the element built-in circuit board is heated in the wire bonding step, stable wire bonding is possible. This is because there is no thermoplastic resin underneath, unlike wire bonding to one wiring of the first wiring circuit. When wire bonding is performed to the first wiring circuit 2 on the interlayer insulating layer 1 made of the thermoplastic resin, the interlayer insulating layer 1 is easily deformed by the heating, and therefore the first wiring thereon Bonding failure with the circuit 2 is likely to occur.

そして、上記素子内蔵回路基板では、更に、上記第1の配線回路2および第2の配線回路3の所要の領域において種々の電子部品が実装される。このようにして、本実施形態で説明した素子内蔵回路基板は、機能素子部品の高密度実装を容易にし、回路基板の更なる高機能化およびコンパクト化を可能にする。   In the element-embedded circuit board, various electronic components are further mounted in required regions of the first wiring circuit 2 and the second wiring circuit 3. In this manner, the element-embedded circuit board described in the present embodiment facilitates high-density mounting of functional element parts, and enables further enhancement of function and compactness of the circuit board.

(第2の実施形態)
次に、本発明の第2の実施形態に係る素子内蔵回路基板およびその製造方法について図5ないし8を参照して説明する。図5は素子内蔵回路基板の別の一態様を示す要部断面図である。そして、図6ないし8はこの素子内蔵回路基板の製造方法を示す工程別回路基板断面図である。
(Second Embodiment)
Next, an element built-in circuit board and a method for manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a cross-sectional view of an essential part showing another aspect of the circuit board with a built-in element. 6 to 8 are sectional views of the circuit boards according to the process showing the method of manufacturing the element built-in circuit board.

図5において、素子内蔵回路基板は、熱可塑性樹脂から成る層間絶縁体層1、該層間絶縁体層1の一主面に形成された第1の配線回路2、層間絶縁体層1の他主面に形成された第2の配線回路3を有する。そして、第2の配線回路3の一の配線3aおよび他の配線3bには、それぞれ層間絶縁体層1により囲繞された凹所23および凹所5が設けられている。   In FIG. 5, the circuit board with a built-in element includes an interlayer insulator layer 1 made of a thermoplastic resin, a first wiring circuit 2 formed on one main surface of the interlayer insulator layer 1, and another main layer of the interlayer insulator layer 1. It has the 2nd wiring circuit 3 formed in the surface. The one wiring 3a and the other wiring 3b of the second wiring circuit 3 are each provided with a recess 23 and a recess 5 surrounded by the interlayer insulating layer 1.

ここで、上記凹所23底部および凹所5底部の配線3aと配線3bの表面、そして第2の配線回路3を被覆するメッキレジスト7の一部の開口部に、例えばNi/AuあるいはNi/Agの複合層から成るメッキ層6が施されている。   Here, the surface of the wiring 3a and the wiring 3b at the bottom of the recess 23 and the bottom of the recess 5 and the opening of a part of the plating resist 7 covering the second wiring circuit 3, for example, Ni / Au or Ni / A plating layer 6 made of a composite layer of Ag is applied.

そして、上記凹所5底部の配線3bのランド部に半導体チップ8がマウントされ、ボンディングワイヤー9が半導体チップ8の電極パッド(不図示)と上記凹所23で露出する一の配線3aに接続されている。更に、封止樹脂10が、上記半導体チップ8を上記凹所5に封止し第1の配線回路2を被覆するようにして、全面に形成されている。このようにして、本実施形態の素子内蔵回路基板は、能動素子あるいは受動素子を有する半導体チップ8を内蔵する。   The semiconductor chip 8 is mounted on the land portion of the wiring 3b at the bottom of the recess 5, and the bonding wire 9 is connected to the electrode pad (not shown) of the semiconductor chip 8 and the one wiring 3a exposed at the recess 23. ing. Further, a sealing resin 10 is formed on the entire surface so as to seal the semiconductor chip 8 in the recess 5 and cover the first wiring circuit 2. In this manner, the element built-in circuit board of the present embodiment incorporates the semiconductor chip 8 having an active element or a passive element.

上記実施形態において、層間絶縁体層1には、第1の実施形態で説明したLCPのような熱可塑性樹脂が使用される。また、上記第1の配線回路2および第2の配線回路3は銅箔のような金属箔により形成されると好適である。   In the above embodiment, the interlayer insulator layer 1 is made of a thermoplastic resin such as the LCP described in the first embodiment. The first wiring circuit 2 and the second wiring circuit 3 are preferably formed of a metal foil such as a copper foil.

次に、第2の実施形態の素子内蔵回路基板の製造方法を説明する。図6(a)に示すように、第1の実施形態の場合と同様に、例えば50〜100μmの第1の銅箔11を用意する。そして、第1の銅箔11の表面に所定パターンを有するエッチングレジスト24を形成し、更に第1の銅箔11の裏側の全面を被覆するエッチングレジスト25を形成する。   Next, a method for manufacturing the element built-in circuit board according to the second embodiment will be described. As shown in FIG. 6A, as in the case of the first embodiment, for example, a first copper foil 11 of 50 to 100 μm is prepared. Then, an etching resist 24 having a predetermined pattern is formed on the surface of the first copper foil 11, and further an etching resist 25 that covers the entire back side of the first copper foil 11 is formed.

次に、例えば化学薬液である塩化第二鉄水溶液のエッチング液に浸漬し、上記エッチングレジスト24,25をエッチングマスクにして、上記第1の銅箔11をエッチング加工する。このようにして、図6(b)に示すように、上記半導体チップ8の厚さと同程度となる深さが30〜80μm程度の凹部14を第1の銅箔11bの表面に形成する。   Next, the first copper foil 11 is etched by immersing it in an etching solution of ferric chloride aqueous solution, which is a chemical solution, for example, using the etching resists 24 and 25 as an etching mask. In this way, as shown in FIG. 6B, a recess 14 having a depth of about 30 to 80 μm, which is about the same as the thickness of the semiconductor chip 8, is formed on the surface of the first copper foil 11b.

次に、図6(c)に示すように、第1の銅箔11bの凹部14を形設した面側に凹部14とほぼ同等な厚さの熱可塑性樹脂であるLCPフィルム15を配置し、更に厚さ20〜35μmの第2の銅箔16を積層配置して積層体にする。そして、図6(d)に示すように、上記積層体の両銅箔11b、16を加熱加圧し一体化して両面銅張積層板17を作製する。ここで、第1の銅箔11bの凸部はLCPフィルム15を貫挿し第2の銅箔16に達するようになる。   Next, as shown in FIG. 6 (c), an LCP film 15 which is a thermoplastic resin having a thickness substantially equal to the concave portion 14 is disposed on the surface side where the concave portion 14 of the first copper foil 11b is formed, and Further, a second copper foil 16 having a thickness of 20 to 35 μm is laminated to form a laminate. And as shown in FIG.6 (d), both the copper foils 11b and 16 of the said laminated body are heat-pressed and integrated, and the double-sided copper clad laminated board 17 is produced. Here, the convex portion of the first copper foil 11 b reaches the second copper foil 16 through the LCP film 15.

次に、図7(a)に示すように、両面銅張積層板17の表面に第1の配線回路2を有するエッチングレジスト26を形成し、更に両面銅張積層板17の裏側に第2の配線回路3を有するエッチングレジスト27を形成する。   Next, as shown in FIG. 7A, an etching resist 26 having the first wiring circuit 2 is formed on the surface of the double-sided copper-clad laminate 17, and further a second side is formed on the back side of the double-sided copper-clad laminate 17. An etching resist 27 having the wiring circuit 3 is formed.

そして、例えば化学薬液である塩化第二鉄水溶液のエッチング液に浸漬し、上記エッチングレジスト26,27をエッチングマスクにして、両面銅張積層板17の両銅箔11b,16をエッチング加工する。このようにして、図7(b)に示すように、第1の配線回路2、第2の配線回路を構成する配線3aと配線3bを形成する。また、配線3aおよび配線3bの層間絶縁体層1を貫挿し第2の銅箔16に達していた凸部は所要の深さにエッチングされる。このようにして、配線3b上に層間絶縁体層1により囲繞された凹所5、配線3a上に層間絶縁体層1により囲繞された凹所23が設けられる。   Then, for example, the copper foils 11b and 16 of the double-sided copper clad laminate 17 are etched by immersing in an etching solution of a ferric chloride aqueous solution that is a chemical solution and using the etching resists 26 and 27 as an etching mask. In this way, as shown in FIG. 7B, the first wiring circuit 2 and the wiring 3a and the wiring 3b constituting the second wiring circuit are formed. Further, the convex portion that has penetrated the interlayer insulator layer 1 of the wiring 3a and the wiring 3b and reached the second copper foil 16 is etched to a required depth. In this way, the recess 5 surrounded by the interlayer insulator layer 1 is provided on the wiring 3b, and the recess 23 surrounded by the interlayer insulator layer 1 is provided on the wiring 3a.

図7(b)では、凹所5および凹所23の深さは凹部14と同じになるように示しているが、これ等の深さは所要の深さになるように自在に設定すればよい。ここで、凹所5の平面寸法は、収納される半導体チップ8のサイズに応じ、例えば10mm×10mmにも達する広いものとなる。これに対して、凹所23の平面寸法は、ボンディングワイヤー9をボンディングできる広さであればよく、例えば矩形の一辺が50μm〜100μm程度であればよい。   In FIG. 7B, the depths of the recess 5 and the recess 23 are shown to be the same as those of the recess 14, but these depths can be freely set so as to be the required depth. Good. Here, the planar dimension of the recess 5 is as wide as 10 mm × 10 mm, for example, depending on the size of the semiconductor chip 8 to be accommodated. On the other hand, the planar dimension of the recess 23 only needs to be large enough to bond the bonding wire 9, and for example, one side of the rectangle may be about 50 μm to 100 μm.

続いて、公知の方法により有機溶剤を用いてエッチングレジスト26,27を剥離し図7(c)に示すような回路基板にする。   Subsequently, the etching resists 26 and 27 are peeled off using an organic solvent by a known method to obtain a circuit board as shown in FIG.

次に、図8(a)に示すように、第1の実施形態で説明したのと同様にして所定の領域を被覆するパターンを有するメッキレジスト7を形成する。そして、上記凹所23底部および凹所5底部の配線3aおよび配線3bの表面、および第2の配線回路3の所定領域に、例えばNi/Auの複合層から成るメッキ層6を形成する。   Next, as shown in FIG. 8A, a plating resist 7 having a pattern covering a predetermined region is formed in the same manner as described in the first embodiment. Then, a plated layer 6 made of, for example, a Ni / Au composite layer is formed on the surfaces of the wiring 3 a and the wiring 3 b at the bottom of the recess 23 and the bottom of the recess 5 and a predetermined region of the second wiring circuit 3.

続いて、図8(b)に示すように、凹所5底部の配線3bから成るランド部のメッキ層6表面に、例えばAgペーストにより半導体チップ8を接着させ装着する。そして、図8(c)に示すように、半導体チップ8の電極パッド(不図示)と例えば2つの配線3aの凹所23底部のメッキ層6とを例えば超音波ボンディング法を用いてボンディングワイヤー9で接続する。   Subsequently, as shown in FIG. 8B, the semiconductor chip 8 is attached and attached to the surface of the plating layer 6 in the land portion composed of the wiring 3b at the bottom of the recess 5 by, for example, Ag paste. Then, as shown in FIG. 8C, an electrode pad (not shown) of the semiconductor chip 8 and, for example, the plating layer 6 at the bottom of the recess 23 of the two wirings 3a are bonded to the bonding wire 9 using, for example, an ultrasonic bonding method. Connect with.

最後に、第1の実施形態で説明したのと同じようにして、図5で示した封止樹脂10を全面に形成する。以上のようにして、第2の実施形態の素子内蔵回路基板が形成される。   Finally, the sealing resin 10 shown in FIG. 5 is formed on the entire surface in the same manner as described in the first embodiment. As described above, the circuit board with a built-in element according to the second embodiment is formed.

本実施形態では、第1の実施形態で説明したのと同様な効果が生じる。更に、この実施形態では、ボンディングワイヤー9が低ループになり、第1の実施形態の場合よりも封止樹脂10の膜厚を薄くすることが可能になる。この効果は、ボンディングワイヤー9が、第1の実施形態では第1の配線回路3の凸部4にボンディングされるのに対し、この場合には上記凸部4より低位置になる凹所23底部にボンディングされることから生じる。ここで、ボンディングワイヤー9の径を例えば20μmφにすると、ボンディングワイヤー9の高さは30〜60μm低くなり、それに伴い封止樹脂10の厚さを30〜60μm薄くすることが可能になる。このようにして、例えば全体の厚さが350〜400μm程度の素子内蔵回路基板が容易に実現できる。   In this embodiment, the same effect as described in the first embodiment is produced. Furthermore, in this embodiment, the bonding wire 9 becomes a low loop, and the film thickness of the sealing resin 10 can be made thinner than in the case of the first embodiment. The effect is that the bonding wire 9 is bonded to the convex portion 4 of the first wiring circuit 3 in the first embodiment, whereas in this case, the bottom of the recess 23 that is positioned lower than the convex portion 4. Results from being bonded to. Here, when the diameter of the bonding wire 9 is, for example, 20 μmφ, the height of the bonding wire 9 is reduced by 30 to 60 μm, and accordingly, the thickness of the sealing resin 10 can be reduced by 30 to 60 μm. In this way, for example, an element-embedded circuit board having an overall thickness of about 350 to 400 μm can be easily realized.

そして、上記素子内蔵回路基板は、例えばICカード厚さを更に薄くし、あるいは携帯機器の更なるコンパクト化を容易にする。   The element-embedded circuit board further reduces the thickness of the IC card, for example, or facilitates further downsizing of the portable device.

(第3の実施形態)
次に、本発明の第3の実施形態に係る素子内蔵回路基板およびその製造方法について図9ないし12を参照して説明する。図9は素子内蔵回路基板の更に別の一態様を示す要部断面図である。そして、図10ないし12はこの素子内蔵回路基板の製造方法を示す工程別回路基板断面図である。
(Third embodiment)
Next, an element built-in circuit board and a method for manufacturing the same according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a cross-sectional view of an essential part showing still another aspect of the circuit board with a built-in element. 10 to 12 are sectional views of the circuit boards according to the process showing the method of manufacturing the element built-in circuit board.

図9において、素子内蔵回路基板は、熱可塑性樹脂から成る層間絶縁体層1、該層間絶縁体層1の一主面に形成された第1の配線回路2(不図示)、層間絶縁体層1の他主面に形成された第2の配線回路3を有する。上記第2の配線回路3の一の配線3aおよび他の配線3bには、それぞれ層間絶縁体層1により囲繞された凹所23aおよび凹所5aが設けられている。そして、本実施形態で特徴的事項として、少なくとも凹所5aが順テーパー状に形成されている。なお、凹所23aも順テーパー状に形成されていてもよい。   In FIG. 9, the circuit board with a built-in element includes an interlayer insulator layer 1 made of thermoplastic resin, a first wiring circuit 2 (not shown) formed on one main surface of the interlayer insulator layer 1, an interlayer insulator layer. 1 has a second wiring circuit 3 formed on the other main surface. The one wiring 3a and the other wiring 3b of the second wiring circuit 3 are provided with a recess 23a and a recess 5a surrounded by the interlayer insulator layer 1, respectively. And as a characteristic matter in the present embodiment, at least the recess 5a is formed in a forward tapered shape. The recess 23a may also be formed in a forward tapered shape.

ここで、上記凹所23a底部および凹所5a底部の配線3aと配線3bの表面、そして第2の配線回路3を被覆するメッキレジスト7の一部の開口部に、例えばNi/Agの複合層から成るメッキ層6が施されている。   Here, for example, a Ni / Ag composite layer is formed at the bottom of the recess 23 a and the surfaces of the wiring 3 a and the wiring 3 b at the bottom of the recess 5 a and a part of the opening of the plating resist 7 covering the second wiring circuit 3. A plating layer 6 made of is applied.

そして、上記順テーパー状の凹所5a底部の配線3bのランド部に半導体チップ8がマウントされ、ボンディングワイヤー9が半導体チップ8の電極パッド(不図示)と上記凹所23a底部の配線3aに接続されている。ここで、半導体チップ8は半導体LED(Light Emitting Diode)が好適である。その具体的なものとしては、例えば紫外光、青色光等を出射し蛍光体を励起するいわゆる波長変換型LEDの励起光源を構成する半導体LED、あるいは色光の三原色の可視光を出射し照明または表示等の直接光源となる半導体LEDがある。   The semiconductor chip 8 is mounted on the land portion of the wiring 3b at the bottom of the forward tapered recess 5a, and the bonding wire 9 is connected to the electrode pad (not shown) of the semiconductor chip 8 and the wiring 3a at the bottom of the recess 23a. Has been. Here, the semiconductor chip 8 is preferably a semiconductor LED (Light Emitting Diode). Specific examples thereof include a semiconductor LED that constitutes an excitation light source of a so-called wavelength conversion LED that emits ultraviolet light, blue light, etc. to excite a phosphor, or emits or displays visible light of the three primary colors of colored light. There are semiconductor LEDs that serve as direct light sources.

そして、封止樹脂28が、上記半導体チップ8を上記凹所5aに封止し第1の配線回路2を被覆するようにして、全面に形成されている。ここで、封止樹脂28は上記半導体LEDの出射光を透過する透明樹脂、あるいは蛍光体等の混在する透明樹脂である。   A sealing resin 28 is formed on the entire surface so as to seal the semiconductor chip 8 in the recess 5 a and cover the first wiring circuit 2. Here, the sealing resin 28 is a transparent resin that transmits the light emitted from the semiconductor LED or a transparent resin in which a phosphor or the like is mixed.

この実施形態においては、層間絶縁体層1としては特に光の反射性の高いLCPが好適である。また、上記第1の配線回路2および第2の配線回路3は銅箔により形成されるとよい。   In this embodiment, the interlayer insulator layer 1 is particularly preferably an LCP with high light reflectivity. The first wiring circuit 2 and the second wiring circuit 3 may be formed of copper foil.

次に、第3の実施形態の素子内蔵回路基板の製造方法を説明する。図10(a)に示すように、第1の実施形態の場合と同様に、例えば50〜100μmの第1の銅箔11を用意する。そして、第1の銅箔11の表面に所定パターンを有するエッチングレジスト29を形成し、更に第1の銅箔11の裏側の全面を被覆するエッチングレジスト30を形成する。   Next, a method for manufacturing the element built-in circuit board according to the third embodiment will be described. As shown in FIG. 10A, as in the case of the first embodiment, for example, a first copper foil 11 of 50 to 100 μm is prepared. Then, an etching resist 29 having a predetermined pattern is formed on the surface of the first copper foil 11, and an etching resist 30 that covers the entire back side of the first copper foil 11 is formed.

次に、例えば化学薬液である塩化第二銅水溶液のエッチング液に浸漬し、上記エッチングレジスト29,30をエッチングマスクにして、上記第1の銅箔11をエッチング加工する。このようにして、図10(b)に示すように、上記半導体チップ8と同程度になる深さが30〜80μm程度の凹部14aを第1の銅箔11cの表面に形成する。ここで、上記塩化第二銅水溶液のエッチング液は、凹部14aの断面形状を順テーパー状にする好適な化学薬液である。   Next, the first copper foil 11 is etched using the etching resists 29 and 30 as an etching mask by immersing in an etching solution of a cupric chloride aqueous solution that is a chemical solution, for example. In this way, as shown in FIG. 10B, a recess 14a having a depth of about 30 to 80 μm, which is about the same as the semiconductor chip 8, is formed on the surface of the first copper foil 11c. Here, the etching solution of the above-mentioned cupric chloride aqueous solution is a suitable chemical solution that makes the cross-sectional shape of the recess 14a a forward tapered shape.

次に、図10(c)に示すように、第1の銅箔11cの凹部14aを形設した面側に凹部14aとほぼ同等な厚さの熱可塑性樹脂であるLCPフィルム15を配置し、更に厚さ20〜35μmの第2の銅箔16を積層配置して積層体にする。そして、図10(d)に示すように、上記積層体の両銅箔11c、16を加熱加圧し一体化して両面銅張積層板17を作製する。ここで、第1の銅箔11cの凸部はLCPフィルム15を貫挿し第2の銅箔16に達するようになる。   Next, as shown in FIG. 10 (c), the LCP film 15 which is a thermoplastic resin having a thickness substantially equal to the concave portion 14a is disposed on the surface side where the concave portion 14a of the first copper foil 11c is formed, Further, a second copper foil 16 having a thickness of 20 to 35 μm is laminated to form a laminate. And as shown in FIG.10 (d), both the copper foils 11c and 16 of the said laminated body are heat-pressed and integrated, and the double-sided copper clad laminated board 17 is produced. Here, the convex portion of the first copper foil 11 c reaches the second copper foil 16 through the LCP film 15.

次に、図11(a)に示すように、両面銅張積層板17の上下を反転させ、第1の銅箔11cを表側に第2の銅箔16を裏側にする。そして、両面銅張積層板17の裏側に第2の配線回路3を有するエッチングレジスト31を形成する。ここで、両面銅張積層板17の表側の所定の領域にも第1の配線回路2を有するエッチングレジストが形成されるが図示していない。   Next, as shown in FIG. 11A, the double-sided copper clad laminate 17 is turned upside down so that the first copper foil 11c is the front side and the second copper foil 16 is the back side. Then, an etching resist 31 having the second wiring circuit 3 is formed on the back side of the double-sided copper-clad laminate 17. Here, an etching resist having the first wiring circuit 2 is also formed in a predetermined region on the front side of the double-sided copper-clad laminate 17 but is not shown.

そして、例えば化学薬液である塩化第二鉄水溶液のエッチング液に浸漬し、上記エッチングレジスト31をエッチングマスクにして、両面銅張積層板17の両銅箔16,11cをエッチング加工する。このエッチング加工により、図11(b)に示すように、第2の配線回路3の一配線である配線3aと他配線である配線3bが形成される。また、第1の銅箔11cは上記所定の領域を残してエッチングされる。ここで、第1の銅箔11cが層間絶縁体層1を貫挿し第2の銅箔16に達していた順テーパー形状の凸部は全てエッチング除去される。このようにして、上記第2の銅箔16のエッチング加工により形成された配線3b上に層間絶縁体層1により囲繞された順テーパー形状の凹所5a、配線3a上に層間絶縁体層1により囲繞された順テーパー形状凹所23aが設けられる。   Then, for example, the copper foils 16 and 11c of the double-sided copper clad laminate 17 are etched by immersing in an etching solution of a ferric chloride aqueous solution that is a chemical solution and using the etching resist 31 as an etching mask. By this etching process, as shown in FIG. 11B, a wiring 3a that is one wiring of the second wiring circuit 3 and a wiring 3b that is another wiring are formed. Further, the first copper foil 11c is etched leaving the predetermined region. Here, all the forward taper-shaped convex parts which the 1st copper foil 11c penetrated the interlayer insulator layer 1 and reached the 2nd copper foil 16 are removed by etching. Thus, the forward tapered recess 5a surrounded by the interlayer insulator layer 1 on the wiring 3b formed by etching the second copper foil 16 and the interlayer insulator layer 1 on the wiring 3a. An enclosed forward tapered recess 23a is provided.

図11(b)では、凹所5aおよび凹所23aの深さは凹部14aと同じになっている。ここで、上記LCPフィルム15を貫挿した第1の銅箔11cの凸部が第2の銅箔16と電気的に接続すれば、上記両銅箔16,11cのエッチング加工において、上記凸部を所要の深さにエッチングするようにしてもよい。この場合には、凹所5aおよび凹所23aの深さは凹部14aの深さより浅くなる。なお、凹所5aの平面寸法は、収納される例えば半導体LEDのサイズに応じ、矩形の一辺が例えば1mm〜2mm程度となる。これに対して、凹所23aの平面寸法は矩形の一辺が50μm〜100μm程度になる。   In FIG. 11B, the depth of the recess 5a and the recess 23a is the same as that of the recess 14a. Here, if the convex part of the 1st copper foil 11c which penetrated the said LCP film 15 electrically connects with the 2nd copper foil 16, in the etching process of both the said copper foils 16 and 11c, the said convex part May be etched to a required depth. In this case, the depths of the recess 5a and the recess 23a are shallower than the depth of the recess 14a. The planar dimension of the recess 5a is, for example, about 1 mm to 2 mm on one side of the rectangle depending on the size of the semiconductor LED to be stored. On the other hand, the planar dimension of the recess 23a is about 50 μm to 100 μm on one side of the rectangle.

続いて、公知の方法により有機溶剤を用いてエッチングレジスト31等のエッチングレジストを剥離し、図11(c)に示すような回路基板にする。   Subsequently, the etching resist such as the etching resist 31 is peeled off using an organic solvent by a known method to obtain a circuit board as shown in FIG.

次に、図12(a)に示すように、所定の領域を被覆するパターンを有するメッキレジスト7を形成する。そして、上記凹所23a底部および凹所5a底部の配線3aおよび配線3bの表面、および第2の配線回路3の所定領域に、例えばNi/Agの複合層から成るメッキ層6を形成する。   Next, as shown in FIG. 12A, a plating resist 7 having a pattern covering a predetermined region is formed. Then, a plating layer 6 made of, for example, a composite layer of Ni / Ag is formed on the surfaces of the wiring 3a and wiring 3b at the bottom of the recess 23a and the bottom of the recess 5a and a predetermined region of the second wiring circuit 3.

続いて、図12(b)に示すように、凹所5a底部の配線3bから成るランド部のメッキ層6表面に、例えばAgペーストにより半導体LEDの半導体チップ8を接着させて装着する。そして、図12(c)に示すように、半導体チップ8の電極パッド(不図示)と配線3aの凹所23a底部のメッキ層6とにそれぞれのボンディングワイヤー9を超音波ボンディングする。   Subsequently, as shown in FIG. 12B, the semiconductor LED semiconductor chip 8 is attached to the surface of the plating layer 6 in the land portion composed of the wiring 3b at the bottom of the recess 5a by, for example, Ag paste. Then, as shown in FIG. 12C, the respective bonding wires 9 are ultrasonically bonded to the electrode pads (not shown) of the semiconductor chip 8 and the plating layer 6 at the bottom of the recess 23a of the wiring 3a.

ここで、上記励起光源の半導体LEDとしては、例えばMgZn1−xO、InAlGa(1−x−y)N、GaN系半導体層、InGaN系半導体層、AlGaN系半導体層を含む化合物半導体から成る半導体LEDがある。あるいは、緑色光〜赤色光を発光する直接光源の半導体LEDとしては、例えばInAlGaP系半導体層、GaAsP半導体層、GaP半導体層、AlGaAs半導体層等の化合物半導体層を含んで成る。その他に、SiC、Al(サファイア)、ZnSe、ZnS等の材料が用いられてもよい。 Here, the semiconductor LED of said excitation light source, for example, Mg x Zn 1-x O, In x Al y Ga (1-x-y) N, GaN -based semiconductor layer, InGaN-based semiconductor layer, an AlGaN-based semiconductor layer There are semiconductor LEDs consisting of compound semiconductors. Alternatively, the direct-source semiconductor LED that emits green light to red light includes, for example, a compound semiconductor layer such as an InAlGaP-based semiconductor layer, a GaAsP semiconductor layer, a GaP semiconductor layer, and an AlGaAs semiconductor layer. In addition, materials such as SiC, Al 2 O 3 (sapphire), ZnSe, and ZnS may be used.

最後に、図9で示した封止樹脂28を全面に形成する。以上のようにして、第3の実施形態の素子内蔵回路基板が形成される。ここで、封止樹脂28を構成する透明樹脂としては、無色透明なエポキシ樹脂、アクリル樹脂あるいはシリコーン樹脂が極めて好適である。更に、封止樹脂28に光の分散材として発光の損失がなく、無色透明で高反射率の材料が添加されるとよい。そのような材料として、例えば、酸化ケイ素、酸化アルミニウム、炭酸カルシウム、酸化バリウム、酸化チタン、硫酸バリウム、エポキシ系樹脂などが挙げられる。   Finally, the sealing resin 28 shown in FIG. 9 is formed on the entire surface. As described above, the circuit board with a built-in element according to the third embodiment is formed. Here, as the transparent resin constituting the sealing resin 28, a colorless and transparent epoxy resin, acrylic resin, or silicone resin is extremely suitable. Furthermore, it is preferable to add a colorless, transparent, and highly reflective material as a light dispersion material to the sealing resin 28 without loss of light emission. Examples of such materials include silicon oxide, aluminum oxide, calcium carbonate, barium oxide, titanium oxide, barium sulfate, and epoxy resin.

また、上述した波長変換型LEDの場合は、封止樹脂28に所要の蛍光体が添加される。そのような蛍光体は、半導体LEDからの光により励起され長波長側にシフトした波長で発光するものである。例えば、A12:M(A:Y、Gd、Lu、Tb等 B:Al、Ga M:Ce3+、Tb3+、Eu3+、Cr3+、Nd3+、Er3+等)、ABO:M(A:Y、Gd、Lu、Tb B:Al、Ga M:Ce3+、Tb3+、Eu3+、Cr3+、Nd3+、Er3+)などのアルミン酸塩、又は、(Ba,Ca,Eu)Si:Eu2+などのオルトケイ酸塩が例として挙げられる。 Further, in the case of the wavelength conversion type LED described above, a required phosphor is added to the sealing resin 28. Such a phosphor emits light at a wavelength that is excited by light from the semiconductor LED and shifted to the longer wavelength side. For example, A 3 B 5 O 12 : M (A: Y, Gd, Lu, Tb, etc. B: Al, Ga M: Ce 3+ , Tb 3+ , Eu 3+ , Cr 3+ , Nd 3+ , Er 3+ etc.), ABO 3 : Aluminate such as M (A: Y, Gd, Lu, Tb B: Al, Ga M: Ce 3+ , Tb 3+ , Eu 3+ , Cr 3+ , Nd 3+ , Er 3+ ), or (Ba, Ca, Eu) x Si y O z: orthosilicates such as Eu 2+ and the like as examples.

そして、例えば、GaN系の半導体LEDからの青色光によりYAG(Yttrium Aluminum Garnet)系の蛍光体を励起し、黄色系の蛍光を出射させそれらの混合色である白色光を生成する。あるいは、半導体LEDからの紫外光により上記封止樹脂28中に混在する複数の蛍光体を励起し、例えば色光の三原色の赤、緑、青の蛍光を出射させて白色光を生成する。   Then, for example, a YAG (Yttrium Aluminum Garnet) phosphor is excited by blue light from a GaN-based semiconductor LED, and yellow fluorescent light is emitted to generate white light that is a mixed color thereof. Alternatively, a plurality of phosphors mixed in the sealing resin 28 are excited by ultraviolet light from the semiconductor LED, and white light is generated by emitting, for example, three primary colors of red, green, and blue fluorescence.

本実施形態では、第1および第2の実施形態で説明したのと同様な効果も生じる。そして、素子内蔵回路基板は、上記波長変換型LEDの白色光から成るコンパクトな液晶表示機器用バックライトとして極めて有用になる。その他に、短小軽薄な携帯機器の表示装置あるいは照明装置としても好適になる。   In the present embodiment, the same effect as described in the first and second embodiments is also produced. The circuit board with a built-in element is extremely useful as a compact backlight for liquid crystal display devices made of white light of the wavelength conversion LED. In addition, it is also suitable as a display device or illumination device for short, small and light portable devices.

また、この実施形態では、半導体チップ8が収納される凹所5aが順テーパー状に形成されることから、半導体チップ8から出射する光が層間絶縁体層1の順テーパー状側壁で反射し、その封止樹脂28への出射光率が向上するようになる。また、層間絶縁体層1を例えば白色のLCPフィルム15により形成することにより、上記反射する量が増大するようになる。そして、上記表示装置あるいは照明装置の照度が向上する。   Further, in this embodiment, since the recess 5a in which the semiconductor chip 8 is accommodated is formed in a forward tapered shape, the light emitted from the semiconductor chip 8 is reflected by the forward tapered side wall of the interlayer insulator layer 1, The light emission rate to the sealing resin 28 is improved. Further, by forming the interlayer insulator layer 1 with, for example, a white LCP film 15, the amount of reflection increases. And the illumination intensity of the said display apparatus or an illuminating device improves.

第3の実施形態において、半導体チップ8としてその他の発光素子を収納するようにしてもよい。例えば、有機薄膜のエレクトロルミネセンス(EL)現象を利用した有機EL素子であってもよい。   In the third embodiment, other light emitting elements may be accommodated as the semiconductor chip 8. For example, an organic EL element utilizing the electroluminescence (EL) phenomenon of an organic thin film may be used.

本発明は、上記実施形態に限定されるものでなく、発明の趣旨を逸脱しない範囲でいろいろの変形を採ることができる。当業者にあっては、具体的な実施態様において本発明の技術思想および技術範囲から逸脱せずに種々の変形・変更を加えることが可能である。   The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. Those skilled in the art can make various modifications and changes in specific embodiments without departing from the technical idea and technical scope of the present invention.

例えば、上記実施形態において、上記両面銅張積層板から成る素子内蔵回路基板を内層板とし、その両側に外層としていわゆるプリプレグおよび配線パターン層を所要の層だけ積層して多層配線構造になるようにしてもよい。   For example, in the above-described embodiment, an element-embedded circuit board made of the double-sided copper-clad laminate is used as an inner layer board, and so-called prepregs and wiring pattern layers are laminated as required on both sides to form a multilayer wiring structure. May be.

また、上記実施形態において、回路基板の配線回路は銅箔あるいは薄板から形成しているが、その他の金属材料から成る銅箔あるいは薄板のエッチングにより形成してもよい。   Moreover, in the said embodiment, although the wiring circuit of a circuit board is formed from copper foil or a thin plate, you may form by etching the copper foil or thin plate which consists of another metal material.

また、上記第3の実施形態において、封止樹脂28による半導体チップ8の封止は、無色透明なガラス封止にしてもよい。あるいは、上記封止樹脂10、28の代わりに、多層配線板の形成に用いられるプリプレグのような層間絶縁体層が封止材料として使用されるようにしてもよい。   In the third embodiment, the sealing of the semiconductor chip 8 with the sealing resin 28 may be colorless and transparent glass sealing. Alternatively, instead of the sealing resins 10 and 28, an interlayer insulator layer such as a prepreg used for forming a multilayer wiring board may be used as a sealing material.

更に、本発明の素子内蔵回路基板では、ハンダバンプあるいはボールバンプを用いた接合手段により配線回路と電気接続する機能素子部品を上記第1の凹所に収納するようにしてもよい。   Further, in the circuit board with a built-in element of the present invention, the functional element component that is electrically connected to the wiring circuit by the joining means using solder bumps or ball bumps may be housed in the first recess.

本発明の第1の実施形態にかかる素子内蔵回路基板の一態様を示す要部断面図。1 is a cross-sectional view of a main part showing one aspect of an element built-in circuit board according to a first embodiment of the present invention. (a)ないし(d)は、本発明の第1の実施形態にかかる素子内蔵回路基板の一製造工程を示す工程別回路基板断面図。(A) thru | or (d) is a circuit board sectional drawing according to process which shows one manufacturing process of the circuit board with a built-in element concerning the 1st Embodiment of this invention. (a)および(d)は、図2に続く素子内蔵回路基板の製造工程を示す工程別回路基板断面図。(A) And (d) is the circuit board sectional drawing according to process which shows the manufacturing process of the circuit board with a built-in element following FIG. (a)および(c)は、図3に続く素子内蔵回路基板の製造工程を示す工程別回路基板断面図。(A) And (c) is a circuit board sectional view according to process which shows a manufacturing process of an element built-in circuit board following Drawing 3. 本発明の第2の実施形態にかかる素子内蔵回路基板の一態様を示す要部断面図。The principal part sectional view showing one mode of the circuit board with a built-in element concerning a 2nd embodiment of the present invention. (a)ないし(d)は、本発明の第2の実施形態にかかる素子内蔵回路基板の一製造工程を示す工程別回路基板断面図。(A) thru | or (d) is a circuit board sectional drawing according to process which shows one manufacturing process of the circuit board with a built-in element concerning the 2nd Embodiment of this invention. (a)および(c)は、図6に続く素子内蔵回路基板の製造工程を示す工程別回路基板断面図。(A) And (c) is a circuit board sectional view according to process which shows a manufacturing process of an element built-in circuit board following Drawing 6. (a)および(c)は、図7に続く素子内蔵回路基板の製造工程を示す工程別回路基板断面図。(A) And (c) is a circuit board sectional view according to process which shows the manufacturing process of the circuit board with a built-in element following Drawing 7. 本発明の第3の実施形態にかかる素子内蔵回路基板の一態様を示す要部断面図。Sectional drawing which shows the principal part which shows the one aspect | mode of the circuit board with a built-in element concerning the 3rd Embodiment of this invention. (a)ないし(d)は、本発明の第3の実施形態にかかる素子内蔵回路基板の一製造工程を示す工程別回路基板断面図。(A) thru | or (d) are circuit board sectional drawings according to process which show one manufacturing process of the circuit board with a built-in element concerning the 3rd Embodiment of this invention. (a)および(c)は、図10に続く素子内蔵回路基板の製造工程を示す工程別回路基板断面図。(A) And (c) is the circuit board sectional drawing according to process which shows the manufacturing process of the circuit board with a built-in element following FIG. (a)および(c)は、図11に続く素子内蔵回路基板の製造工程を示す工程別回路基板断面図。(A) And (c) is a circuit board sectional view according to process which shows a manufacturing process of a circuit board with a built-in element following Drawing 11.

符号の説明Explanation of symbols

1…層間絶縁体層,2…第1の配線回路,3…第2の配線回路,3a,3b…配線,4,20…凸部,5,5a,23,23a…凹所,6…メッキ層,7…メッキレジスト,8…半導体チップ,9…ボンディングワイヤー,10,28…封止樹脂,11,11a,11b,11c…第1の銅箔,12,13,18,19,21,22,24,25,26,27,29,30,31…エッチングレジスト,14,14a…凹部,15…LCPフィルム,16…第2の銅箔,17…両面銅張積層板   DESCRIPTION OF SYMBOLS 1 ... Interlayer insulator layer, 2 ... 1st wiring circuit, 3 ... 2nd wiring circuit, 3a, 3b ... wiring, 4, 20 ... Convex part, 5, 5a, 23, 23a ... Recessed part, 6 ... Plating Layer, 7 ... plating resist, 8 ... semiconductor chip, 9 ... bonding wire, 10, 28 ... sealing resin, 11, 11a, 11b, 11c ... first copper foil, 12, 13, 18, 19, 21, 22 24, 25, 26, 27, 29, 30, 31 ... Etching resist, 14, 14a ... Recess, 15 ... LCP film, 16 ... Second copper foil, 17 ... Double-sided copper-clad laminate

Claims (7)

金属箔で形成された第1の配線回路と、
金属箔で形成された第2の配線回路と、
一主面に前記第1の配線回路を積層し、他主面に前記第2の配線回路を積層し前記第2の配線回路の一部が前記一主面側に露出するように形成した熱可塑性樹脂から成る絶縁体層であって、前記第2の配線回路の前記一主面側に露出する一部を底部として機能素子を収納可能な第1の凹所を形成している絶縁体層とを具備し、
前記第1の凹所の底部に露出する前記第2の配線回路の一配線に前記機能素子が装着され、且つ、前記絶縁体層の前記一主面側に露出し前記一配線と同一金属箔でできた前記第2の配線回路の他配線と前記機能素子がボンディングワイヤーで接続されていることを特徴とする素子内蔵回路基板。
A first wiring circuit formed of metal foil;
A second wiring circuit formed of metal foil;
Heat formed by laminating the first wiring circuit on one main surface and laminating the second wiring circuit on the other main surface so that a part of the second wiring circuit is exposed on the one main surface side An insulator layer made of a plastic resin, the insulator layer forming a first recess capable of accommodating a functional element with a part exposed on the one main surface side of the second wiring circuit as a bottom portion And
The functional element is mounted on one wiring of the second wiring circuit exposed at the bottom of the first recess, and is exposed on the one main surface side of the insulator layer and is the same metal foil as the one wiring A circuit board with a built-in element, characterized in that the other wiring of the second wiring circuit made of and the functional element are connected by a bonding wire.
前記他配線の一部が前記絶縁体層を貫挿し前記一主面側に露出する凸部を有し、
前記ボンディングワイヤーは前記凸部の上面にボンディングされていることを特徴とする請求項1に記載の素子内蔵回路基板。
A portion of the other wiring has a protrusion that penetrates the insulator layer and is exposed to the one main surface side;
The element built-in circuit board according to claim 1, wherein the bonding wire is bonded to an upper surface of the convex portion.
前記他配線の一部に前記絶縁体層に形成された第2の凹所を有し、
前記ボンディングワイヤーは、前記第2の凹所の底部で前記一主面側に露出する前記他配線にボンディングされていることを特徴とする請求項1に記載の素子内蔵回路基板。
A second recess formed in the insulator layer in a part of the other wiring;
2. The element built-in circuit board according to claim 1, wherein the bonding wire is bonded to the other wiring exposed to the one main surface side at the bottom of the second recess.
前記第1の凹所の断面形状が順テーパーになっていることを特徴とする請求項1ないし3のいずれかに記載の素子内蔵回路基板。 4. The element built-in circuit board according to claim 1, wherein a cross-sectional shape of the first recess is a forward taper. 機能素子を内部に収納した素子内蔵回路基板の製造方法であって、
第1の金属箔の表面を選択的にエッチングし複数の凹部および凸部を形成する工程と、
前記凹部と凸部を形成した前記第1の金属箔の表面側に、熱可塑性樹脂から成る絶縁体層と第2の金属箔とをこの順に積層配置する工程と、
前記積層配置した積層体の加熱加圧により一体化し、前記凹部に前記絶縁体層を充填し前記凸部を前記絶縁体層の一主面まで貫挿させる工程と、
前記第1の金属箔および前記第2の金属箔を選択的にエッチングし、前記第2の金属箔から成る第1の配線回路を前記絶縁体層の一主面に形成すると共に前記凸部を露出させ、更に前記第1の金属箔から成る第2の配線回路を前記絶縁体層の他主面に形成する工程と、
前記第2の配線回路の一配線の前記凸部を前記絶縁体層の一主面側から所定の深さにエッチングし第1の凹所を形成する工程と、
前記第1の凹所の前記一配線に機能素子を装着する工程と、
前記機能素子と前記第2の配線回路の他配線の前記凸部の上面にワイヤーボンディングする工程と、
を有することを特徴とする素子内蔵回路基板の製造方法。
A method of manufacturing an element-embedded circuit board that houses functional elements therein,
Selectively etching the surface of the first metal foil to form a plurality of recesses and protrusions;
A step of laminating and arranging an insulating layer made of a thermoplastic resin and a second metal foil in this order on the surface side of the first metal foil in which the concave and convex portions are formed;
The step of integrating the laminated body arranged by heating and pressurizing, filling the concave portion with the insulator layer, and penetrating the convex portion to one main surface of the insulator layer;
The first metal foil and the second metal foil are selectively etched to form a first wiring circuit made of the second metal foil on one main surface of the insulator layer, and the convex portion Exposing the second wiring circuit made of the first metal foil on the other main surface of the insulator layer; and
Etching the convex portion of one wiring of the second wiring circuit from the main surface side of the insulator layer to a predetermined depth to form a first recess;
Attaching a functional element to the one wiring of the first recess;
Wire bonding to the upper surface of the convex portion of the other wiring of the functional element and the second wiring circuit;
A method of manufacturing a circuit board with a built-in element, comprising:
機能素子を内部に収納した素子内蔵回路基板の製造方法であって、
第1の金属箔の表面を選択的にエッチングし複数の凹部および凸部を形成する工程と、
前記凹部と凸部を形成した前記第1の金属箔の表面側に、熱可塑性樹脂から成る絶縁体層と第2の金属箔とをこの順に積層配置する工程と、
前記積層配置した積層体の加熱加圧により一体化し、前記凹部に前記絶縁体層を充填し前記凸部を前記絶縁体層の一主面まで貫挿させる工程と、
前記第1の金属箔および前記第2の金属箔を選択的にエッチングし、前記第2の金属箔から成る第1の配線回路を前記絶縁体層の一主面に形成すると共に前記凸部を露出させ、更に前記第1の金属箔から成る第2の配線回路を前記絶縁体層の他主面に形成する工程と、
前記第2の配線回路の一配線の前記凸部を前記絶縁体層の一主面側から所定の深さにエッチングし第1の凹所を形成する工程と、
前記第2の配線回路の他配線の前記凸部を前記絶縁体層の一主面側から所定の深さにエッチングし第2の凹所を形成する工程と、
前記第1の凹所の前記一配線に機能素子を装着する工程と、
前記機能素子と前記第2の凹所の前記他配線にワイヤーボンディングする工程と、
を有することを特徴とする素子内蔵回路基板の製造方法。
A method of manufacturing an element-embedded circuit board that houses functional elements therein,
Selectively etching the surface of the first metal foil to form a plurality of recesses and protrusions;
A step of laminating and arranging an insulating layer made of a thermoplastic resin and a second metal foil in this order on the surface side of the first metal foil in which the concave and convex portions are formed;
The step of integrating the laminated body arranged by heating and pressurizing, filling the concave portion with the insulator layer, and penetrating the convex portion to one main surface of the insulator layer;
The first metal foil and the second metal foil are selectively etched to form a first wiring circuit made of the second metal foil on one main surface of the insulator layer, and the convex portion Exposing the second wiring circuit made of the first metal foil on the other main surface of the insulator layer; and
Etching the convex portion of one wiring of the second wiring circuit from the main surface side of the insulator layer to a predetermined depth to form a first recess;
Etching the convex portion of the other wiring of the second wiring circuit to a predetermined depth from one main surface side of the insulator layer to form a second recess;
Attaching a functional element to the one wiring of the first recess;
Wire bonding the functional element and the second wiring in the second recess;
A method of manufacturing a circuit board with a built-in element, comprising:
前記第1の凹所は断面形状が順テーパーである請求項5または6に記載の素子内蔵回路基板の製造方法。 7. The method of manufacturing a circuit board with a built- in element according to claim 5, wherein the first recess has a forward taper in cross-sectional shape .
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