JP2006013465A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2006013465A
JP2006013465A JP2005148357A JP2005148357A JP2006013465A JP 2006013465 A JP2006013465 A JP 2006013465A JP 2005148357 A JP2005148357 A JP 2005148357A JP 2005148357 A JP2005148357 A JP 2005148357A JP 2006013465 A JP2006013465 A JP 2006013465A
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Prior art keywords
wiring
semiconductor device
film
semiconductor
wiring layer
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JP2005148357A
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Japanese (ja)
Inventor
Koichi Hirano
浩一 平野
Yoshiyuki Yamamoto
義之 山本
Seiichi Nakatani
誠一 中谷
Toshiyuki Kojima
俊之 小島
Shingo Komatsu
慎五 小松
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2005148357A priority Critical patent/JP2006013465A/en
Publication of JP2006013465A publication Critical patent/JP2006013465A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where inconvenience, that a semiconductor device applying a WB method, FC method, or TAB method has, is alleviated. <P>SOLUTION: The semiconductor device includes a first semiconductor element 101A which has a first element body 10 and a first element electrode 12a provided on a first surface 10a of the first element body; a wiring substrate 301 which has an insulating substrate 30 and a first wiring layer 32 formed on one main surface of the insulating substrate and where the one main surface is positioned so as to face the second surface of the first element body; a first film 20 which covers at least a part of a surface containing the surface of the first element electrode of the first semiconductor element and at least a part of a surface of the first semiconductor element side of the wiring substrate; and a second wiring layer 25 which is formed on a surface of the wiring substrate side of the first film and contains first wiring 22 having a first end and second end. The first end of the first wiring and the first element electrode are joined, and the second end of the first wiring and a part of the first wiring layer are joined. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置およびその製造方法に関する。特に、配線基板と配線基板に実装された半導体素子とを含む半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device including a wiring board and a semiconductor element mounted on the wiring board, and a manufacturing method thereof.

半導体素子と配線基板の配線とを接続する技術には、大別すると（１）ワイヤーボンディング（ＷＢ）法（例えば、特許文献１参照）、（２）フィリップチップボンディング（ＦＣ）法（例えば、特許文献２参照）、（３）ＴＡＢ（tape automated bonding）法（例えば、特許文献３参照）等がある。以下、これらの方法を簡単に説明する。   The technology for connecting the semiconductor element and the wiring on the wiring board can be broadly divided into (1) wire bonding (WB) method (for example, see Patent Document 1) and (2) Philip chip bonding (FC) method (for example, patent). Reference 3), (3) TAB (tape automated bonding) method (for example, see Patent Document 3), and the like. Hereinafter, these methods will be briefly described.

まず、ＷＢ法を、図１７Ａ、図１７Ｂ、および図１８を参照しながら説明する。図１７Ａは、半導体チップとリードフレームとがボンディングワイヤにより接続された状態を説明する平面図であり、図１７Ｂは図１７ＡのＡ−Ａ断面図である。図１８はＷＢ法を採用した半導体装置の断面図である。   First, the WB method will be described with reference to FIG. 17A, FIG. 17B, and FIG. FIG. 17A is a plan view for explaining a state in which the semiconductor chip and the lead frame are connected by bonding wires, and FIG. 17B is a cross-sectional view taken along line AA of FIG. 17A. FIG. 18 is a cross-sectional view of a semiconductor device employing the WB method.

図１７Ａおよび図１７Ｂに示すように、ＷＢ法では、まず、半導体チップ５０１をリードフレームのダイパッド５０４にダイボンディングする。その後、半導体チップ５０１のワイヤーボンディングパッド５０２と、リードフレームの外部端子５０５のインナーリード部とをボンディングワイヤ５０３を介して接続する。次いで、図１８に示すように、半導体チップ５０１および外部端子５０５のインナーリード部を含む領域を封止樹脂５０６によって樹脂封止し、樹脂封止体（半導体装置）５００を得る。   As shown in FIGS. 17A and 17B, in the WB method, first, a semiconductor chip 501 is die-bonded to a die pad 504 of a lead frame. Thereafter, the wire bonding pad 502 of the semiconductor chip 501 and the inner lead portion of the external terminal 505 of the lead frame are connected via the bonding wire 503. Next, as shown in FIG. 18, the region including the semiconductor chip 501 and the inner lead portion of the external terminal 505 is sealed with a sealing resin 506 to obtain a resin sealing body (semiconductor device) 500.

次に、ＦＣ法について、図１９を参照しながら説明する。図１９は、ＦＣ法を採用した半導体装置６００の断面構成を示している。ＦＣ法では、基板６０１（配線基板）の配線層６０２と半導体チップ６０５の電極６０４とが、パンプ６０３を介して接続されている。基板６０１と半導体チップ６０５との隙間は封止樹脂６０７により封止されており、封止樹脂６０７内に、配線層６０２、バンプ６０３および電極６０４が埋め込まれている。尚、図１９において、６０６は、トランジスタ等が形成されたセンシティブエリアである。   Next, the FC method will be described with reference to FIG. FIG. 19 shows a cross-sectional configuration of a semiconductor device 600 employing the FC method. In the FC method, the wiring layer 602 of the substrate 601 (wiring substrate) and the electrode 604 of the semiconductor chip 605 are connected via a pump 603. A gap between the substrate 601 and the semiconductor chip 605 is sealed with a sealing resin 607, and the wiring layer 602, the bump 603, and the electrode 604 are embedded in the sealing resin 607. In FIG. 19, reference numeral 606 denotes a sensitive area in which transistors and the like are formed.

次に、ＴＡＢ法を採用した半導体装置について、図２０〜図２３を参照しながら説明する。図２０および図２２は、ＴＡＢ法を採用した半導体装置７００の断面構成を示しており、図２１および図２３は、その半導体装置７００を実装基板７０９に実装した状態を示している。   Next, a semiconductor device employing the TAB method will be described with reference to FIGS. 20 and 22 show a cross-sectional configuration of a semiconductor device 700 employing the TAB method, and FIGS. 21 and 23 show a state in which the semiconductor device 700 is mounted on a mounting substrate 709.

図２０および図２２に示した半導体装置７００は、ベースフィルム７０２と、半導体ＩＣチップ７０１とを含んでいる。半導体ＩＣチップ７０１は、ベースフィルム７０２に形成されたデバイスホール内に配置されている。ベースフィルム７０２の一方の面上には銅箔配線７０３が形成されている。半導体ＩＣチップ７０１の電極７０１ａは、銅箔配線７０３の内側先端部（インナーリード７０３ａ）に接続されている。銅箔配線７０３のうちインナーリード７０３ａよりも外側の部分には、外部接続用のランド７０３ｂが設けられている。ランド７０３ｂには半田バンプ７０６が接続されている。ベースフィルム７０２にはスルーホール７０２ａが形成されており、ランド７０３ｂの中央部には孔７０３ｃが形成されている。ベースフィルム７０２上にはカバーレジスト７０４が形成されている。デバイスホール内には、半導体ＩＣチップ７０１を保護する封止樹脂７０５が充填されている。   A semiconductor device 700 shown in FIGS. 20 and 22 includes a base film 702 and a semiconductor IC chip 701. The semiconductor IC chip 701 is disposed in a device hole formed in the base film 702. Copper foil wiring 703 is formed on one surface of the base film 702. The electrode 701a of the semiconductor IC chip 701 is connected to the inner tip (inner lead 703a) of the copper foil wiring 703. An external connection land 703b is provided in a portion of the copper foil wiring 703 outside the inner lead 703a. Solder bumps 706 are connected to the lands 703b. A through hole 702a is formed in the base film 702, and a hole 703c is formed in the center of the land 703b. A cover resist 704 is formed on the base film 702. The device hole is filled with a sealing resin 705 that protects the semiconductor IC chip 701.

この半導体装置７００では、半田バンプ７０６がアウターリードの役割を果たしている。図２１および図２３に示すように、実装基板７０９上のパッド７０９ａ上に半田バンプ７０６が配置され、一括リフロー方式によって、半導体装置７００が実装基板７０９に実装されている。
特開平４−２８６１３４号公報 特開２０００−３６５０４号公報 特開平８−８８２４５号公報 In this semiconductor device 700, the solder bumps 706 serve as outer leads. As shown in FIGS. 21 and 23, solder bumps 706 are arranged on pads 709a on the mounting substrate 709, and the semiconductor device 700 is mounted on the mounting substrate 709 by a batch reflow method.
JP-A-4-286134 JP 2000-36504 A JP-A-8-88245

しかし、ＷＢ法を採用した半導体装置５００では、ワイヤーボンディングパッド５０２と、外部端子５０５とを一つずつボンディングワイヤ５０３で接続する。そのため、ワイヤーボンディングパッド５０２や外部端子５０５の数が多くなればなるほど作業の手間がかかり生産性が悪くなるという問題がある（図１７Ａおよび図１７Ｂ参照）。図１８に示すように、ＷＢ法を採用した半導体装置５００は、この図においてボンディングワイヤ５０３の一部が半導体チップ５０１の下面よりも下方に配置され、半導体チップ５０１とボンディングワイヤ５０３とが封止樹脂５０６によって封止された構造をしている。そのため、半導体装置５００の薄型化について制約が大きい。また、隣り合う外部端子５０５間のピッチによって、隣り合うワイヤーボンディングパッド５０２間のピッチが規定されてしまう。外部端子５０５は基板へ半田付けされる。そのため、外部端子間のショート等の問題が生じないように、外部端子間のピッチは、現状では、０．４ｍｍ程度である。半導体チップのワイヤーボンディングパッド５０２間のピッチを狭くすることができても、外部端子５０５間のピッチは、０．４ｍｍより小さくすることは困難である。このことが、半導体装置の小型化の妨げとなっていた。   However, in the semiconductor device 500 employing the WB method, the wire bonding pads 502 and the external terminals 505 are connected one by one with the bonding wires 503. Therefore, there is a problem that the more the number of wire bonding pads 502 and external terminals 505, the more labor is required and the productivity becomes worse (see FIGS. 17A and 17B). As shown in FIG. 18, in the semiconductor device 500 employing the WB method, a part of the bonding wire 503 is disposed below the lower surface of the semiconductor chip 501 in this figure, and the semiconductor chip 501 and the bonding wire 503 are sealed. A structure sealed with a resin 506 is employed. For this reason, there are significant restrictions on the thickness reduction of the semiconductor device 500. Further, the pitch between adjacent wire bonding pads 502 is defined by the pitch between adjacent external terminals 505. The external terminal 505 is soldered to the board. Therefore, the pitch between the external terminals is currently about 0.4 mm so as not to cause a problem such as a short circuit between the external terminals. Even if the pitch between the wire bonding pads 502 of the semiconductor chip can be reduced, it is difficult to make the pitch between the external terminals 505 smaller than 0.4 mm. This has hindered miniaturization of the semiconductor device.

ＦＣ法を採用した半導体装置６００（図１９参照）には、次のような問題がある。ＦＣ法を採用する半導体装置では、隣り合う電極６０４間のピッチが、外部端子５０５間（図１７参照）のピッチよりも狭い。それゆえ、半導体チップ６０５と基板６０１との位置合わせについて、非常に高い精度が要求される。   The semiconductor device 600 (see FIG. 19) employing the FC method has the following problems. In a semiconductor device employing the FC method, the pitch between adjacent electrodes 604 is narrower than the pitch between external terminals 505 (see FIG. 17). Therefore, very high accuracy is required for alignment between the semiconductor chip 605 and the substrate 601.

また、基板６０１が高価になる傾向があるという問題もある。なぜなら、ＦＣ法を採用した半導体装置では、半導体チップ６０５の電極６０４に対応した、微細な配線を含む配線層６０２を有する基板６０１が必要となるからである。また、電極６０４の数が多い場合には、多層構造の基板６０１（配線基板）が必要となりコスト高となるからである。   There is also a problem that the substrate 601 tends to be expensive. This is because a semiconductor device employing the FC method requires a substrate 601 having a wiring layer 602 including fine wiring corresponding to the electrode 604 of the semiconductor chip 605. Further, when the number of electrodes 604 is large, a multilayer substrate 601 (wiring substrate) is required, resulting in high costs.

また、ＦＣ法を採用した半導体装置６００では、半導体チップ６０５と配線基板６０１とがバンプ６０３を介して接続された構造となっているので、半導体チップ６０５の線膨張係数と基板６０１の線膨張係数とをできるだけ一致させる必要がある。半導体チップ６０５の線膨張係数と基板６０１の線膨張係数とが大きく異なると、バンプ６０３等に応力が加わり、半導体チップ６０５と配線基板６０１との電気接続が損なわれる場合があるからである。したがって、両者の線膨張係数のマッチングは厳密に行われる必要があり、材料選択の制限が大きい。   Further, the semiconductor device 600 adopting the FC method has a structure in which the semiconductor chip 605 and the wiring substrate 601 are connected via the bumps 603. Therefore, the linear expansion coefficient of the semiconductor chip 605 and the linear expansion coefficient of the substrate 601 are obtained. Must be matched as much as possible. This is because if the linear expansion coefficient of the semiconductor chip 605 and the linear expansion coefficient of the substrate 601 are greatly different, stress is applied to the bumps 603 and the like, and the electrical connection between the semiconductor chip 605 and the wiring substrate 601 may be impaired. Therefore, matching of the linear expansion coefficients of the two needs to be performed strictly, and there is a great limitation on material selection.

さらに、ＦＣ法を採用した半導体装置６００では、半導体チップ６０５と基板６０１とをバンプ６０３を介して接続した後、両者の隙間に樹脂（アンダーフィル剤）６０７を充填するため、その分コストがかかり、工程数も多く、生産性が良くない。また、ＦＣ法を採用した半導体装置６００は、ＷＢ法を採用した半導体装置よりも、半導体チップの放熱性が悪いという問題もある。ＷＢ法を採用した半導体装置では、半導体チップの本体部の一方の面が樹脂や半田等からなる薄い接合材層を介して熱伝導性の高いダイパットに固定されているので、半導体チップの放熱性は比較的良い。一方、ＦＣ法を採用した半導体装置では、半導体チップ６０５がバンプ６０３を介して基板６０１に接続されているので、半導体チップ６０５の本体部の基板６０１に対向する面と、基板６０１の半導体素子６０５側の面とが、ＷＢ法を採用した半導体装置よりも離れており、半導体チップの放熱性が悪い。また、ＦＣ法を採用した半導体装置６００では、その製造過程において、バンプ６０３を形成しなければならず、手間がかかる。   Further, in the semiconductor device 600 adopting the FC method, since the semiconductor chip 605 and the substrate 601 are connected via the bumps 603 and the gap between them is filled with the resin (underfill agent) 607, the cost increases accordingly. There are many processes and productivity is not good. Further, the semiconductor device 600 adopting the FC method also has a problem that the heat dissipation of the semiconductor chip is worse than that of the semiconductor device adopting the WB method. In a semiconductor device adopting the WB method, one surface of the main body of the semiconductor chip is fixed to a die pad having high thermal conductivity through a thin bonding material layer made of resin, solder, or the like. Is relatively good. On the other hand, in the semiconductor device adopting the FC method, since the semiconductor chip 605 is connected to the substrate 601 through the bump 603, the surface of the main body of the semiconductor chip 605 facing the substrate 601 and the semiconductor element 605 of the substrate 601. The side surface is separated from the semiconductor device adopting the WB method, and the heat dissipation of the semiconductor chip is poor. Further, in the semiconductor device 600 adopting the FC method, bumps 603 must be formed in the manufacturing process, which is troublesome.

ＴＡＢ法を採用した半導体装置７００には次のような問題がある。ＴＡＢ法を採用した半導体装置７００では、製造過程において、半導体ＩＣチップ７０１の電極７０１ａとインナーリード７０３ａとを接続するインナーリードボンディング（ＩＬＢ）工程と、ランド７０３ｂに半田バンプ７０６を形成するアウターリードボンディング（ＯＬＢ）工程とが、全く異なる手法により行われるので手間がかかる。また、デバイスホールに配置された半導体ＩＣチップ７０１を封止樹脂７０５で封止する必要がある。この工程も手間がかり、ＴＡＢ法を採用した半導体装置７００は、生産性が良くない。   The semiconductor device 700 employing the TAB method has the following problems. In the semiconductor device 700 employing the TAB method, in the manufacturing process, an inner lead bonding (ILB) process for connecting the electrode 701a of the semiconductor IC chip 701 and the inner lead 703a, and an outer lead bonding for forming a solder bump 706 on the land 703b. Since the (OLB) process is performed by a completely different method, it takes time. In addition, the semiconductor IC chip 701 disposed in the device hole needs to be sealed with a sealing resin 705. This process also takes time, and the semiconductor device 700 adopting the TAB method has poor productivity.

本発明は、ＷＢ法、ＦＣ法またはＴＡＢ法を採用した半導体装置が抱えていた不都合が軽減された半導体装置を提供する。本発明は、例えば、生産性が良い半導体装置を提供する。   The present invention provides a semiconductor device in which the disadvantages of a semiconductor device employing the WB method, FC method, or TAB method are reduced. The present invention provides, for example, a semiconductor device with high productivity.

本発明の半導体装置は、第１面と前記第１面に対向する第２面とを有する第１の素子本体部と、前記第１面に設けられた第１の素子電極とを含む第１の半導体素子と、絶縁性基板と前記絶縁性基板の一方の主面に形成された第１の配線層とを含み、前記一方の主面が前記第１の素子本体部の前記第２面と向かい合うように配置された配線基板と、前記第１の半導体素子の前記第１の素子電極の表面を含む面の少なくとも一部と、前記配線基板の第１の半導体素子側の面の少なくとも一部とを覆う第１のフィルムと、前記第１のフィルムの前記配線基板側の面に形成され、第１端と第２端とを有する第１の配線を含む第２の配線層と、を備え、前記第１の配線の前記第１端と前記第１の素子電極とが接合され、前記第１の配線の前記第２端と前記第１の配線層の一部とが接合されていることを特徴とする。   The semiconductor device according to the present invention includes a first element body having a first surface and a second surface facing the first surface, and a first element electrode provided on the first surface. The semiconductor element, an insulating substrate, and a first wiring layer formed on one main surface of the insulating substrate, wherein the one main surface is the second surface of the first element body. A wiring substrate disposed so as to face each other, at least a part of a surface including the surface of the first element electrode of the first semiconductor element, and at least a part of a surface of the wiring substrate on the first semiconductor element side And a second wiring layer including a first wiring having a first end and a second end formed on the surface of the first film on the wiring board side. The first end of the first wiring and the first element electrode are joined, and the second end of the first wiring and the front A portion of the first wiring layer is characterized in that it is joined.

本発明の半導体装置の製造方法は、第１の素子本体部と前記第１の素子本体部に設けられた第１の素子電極とを有する第１の半導体素子と、絶縁性基板と前記絶縁性基板の一方の主面に形成された第１の配線層とを含む配線基板とを、前記第１の素子本体部の前記第１の素子電極が設けられた面の反対面と、前記絶縁性基板の前記一方の主面とが向かい合うように重ね、フィルムと前記フィルムの一方の主面に形成され、第１端と第２端とを有する第１の配線を含む第２の配線層とを含むシート状物の、前記第１の配線の前記第１端と前記第１の素子電極とを接合し、前記第１の配線の前記第２端と前記第１の配線層の一部とを接合して、前記フィルムで、前記第１の半導体素子の前記第１の素子電極の表面を含む面の少なくとも一部と、前記配線基板の前記第１の半導体素子側の面の少なくとも一部とを覆う実装工程を含む。   The method of manufacturing a semiconductor device according to the present invention includes a first semiconductor element having a first element body and a first element electrode provided on the first element body, an insulating substrate, and the insulating material. A wiring substrate including a first wiring layer formed on one main surface of the substrate, a surface opposite to the surface of the first element body portion on which the first element electrode is provided, and the insulating property A second wiring layer including a first wiring having a first end and a second end formed on the one main surface of the film, and overlapping the first main surface of the substrate so as to face each other. The sheet-like material including the first end of the first wiring and the first element electrode are joined, and the second end of the first wiring and a part of the first wiring layer are joined together. Bonding, at least a part of a surface including the surface of the first element electrode of the first semiconductor element with the film; Comprising the mounting step of covering at least a portion of the surface of the first semiconductor element side of the wiring board.

本発明によれば、ＷＢ法、ＦＣ法またはＴＡＢ法を採用した半導体装置が抱えていた不都合が軽減された半導体装置を提供できる。例えば、生産性が良い半導体装置を提供できる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device with which the trouble which the semiconductor device which employ | adopted WB method, FC method, or TAB method had was reduced can be provided. For example, a semiconductor device with high productivity can be provided.

本発明の半導体装置の一例において、好ましくは、第１のフィルムが実質的に透明である。ここで、「実質的に透明」であるとは、第１のフィルムの一方の主面側から、第１のフィルムのもう一方の主面側にある第１の半導体素子の第１の素子電極、および／または絶縁性基板に形成された第１の配線層を可視できる程度に透明であることを意味する。   In one example of the semiconductor device of the present invention, preferably, the first film is substantially transparent. Here, “substantially transparent” means that the first element electrode of the first semiconductor element located on the other main surface side of the first film from the one main surface side of the first film. And / or transparent to such an extent that the first wiring layer formed on the insulating substrate is visible.

本発明の半導体装置の一例において、好ましくは、第１の半導体素子と絶縁性基板とが、接合材を介して接合されている。   In an example of the semiconductor device of the present invention, preferably, the first semiconductor element and the insulating substrate are bonded via a bonding material.

本発明の半導体装置の一例において、好ましくは、第１のフィルムの配線基板側の面の反対面に形成された電磁波遮蔽層をさらに含んでいる。   In one example of the semiconductor device of the present invention, it preferably further includes an electromagnetic wave shielding layer formed on the surface opposite to the surface on the wiring substrate side of the first film.

本発明の半導体装置の一例において、好ましくは、第１のフィルムと第２の配線層とからなる積層体の第２の配線層側の面の一部が、第１の半導体素子の第１の素子電極の表面を含む面に、直接または間接的に密着している。また、本発明の半導体装置の一例において、さらに好ましくは、上記積層体の第２の配線層側の面の上記一部とは異なる他の一部と、第１の素子本体部の側面も、直接または間接的に密着している。   In an example of the semiconductor device of the present invention, preferably, a part of the surface on the second wiring layer side of the laminate composed of the first film and the second wiring layer is the first semiconductor element first surface. It is in direct or indirect contact with the surface including the surface of the device electrode. In one example of the semiconductor device of the present invention, more preferably, another part different from the part of the surface on the second wiring layer side of the stacked body, and the side surface of the first element main body part, Direct or indirect contact.

本発明の半導体装置の一例において、好ましくは、第１のフィルムと第２の配線層とからなる積層体の配線基板側の面が、第１の半導体素子および配線基板に直接または間接的に接合されて、第１の半導体素子が、積層体と配線基板によって囲われる密閉空間内に配置されている。   In an example of the semiconductor device of the present invention, preferably, the surface on the wiring substrate side of the laminate composed of the first film and the second wiring layer is directly or indirectly bonded to the first semiconductor element and the wiring substrate. Thus, the first semiconductor element is disposed in a sealed space surrounded by the stacked body and the wiring board.

本発明の半導体装置の一例において、好ましくは、第１の配線の第１端と第１の素子電極とが接し、第１の配線の第２端と第１の配線層の一部とが接している。   In an example of the semiconductor device of the present invention, preferably, the first end of the first wiring is in contact with the first element electrode, and the second end of the first wiring is in contact with a part of the first wiring layer. ing.

本発明の半導体装置の一例において、好ましくは、第１のフィルムの配線基板側の面の反対面に形成された第３の配線層をさらに含んでいる。   One example of the semiconductor device of the present invention preferably further includes a third wiring layer formed on the surface of the first film opposite to the surface on the wiring substrate side.

本発明の半導体装置の一例において、好ましくは、第２の素子電極を有する第２の半導体素子をさらに含み、第２の素子電極と第３の配線層とが接合されている。   In one example of the semiconductor device of the present invention, preferably, the semiconductor device further includes a second semiconductor element having a second element electrode, and the second element electrode and the third wiring layer are joined.

本発明の半導体装置の一例において、好ましくは、第１のフィルムの配線基板側の面の反対面は、第１の素子本体部の第１面と同面積の平面を含んでいる。また、本発明の半導体装置の一例は、第２の素子本体部と第２の素子本体部に設けられた第２の素子電極とを有する第２の半導体素子をさらに含み、第２の素子本体部の第２の素子電極の表面を含む面の反対面と、第１のフィルムの上記平面とが向かい合うように、第１のフィルム上に第２の半導体素子が配置されている。   In an example of the semiconductor device of the present invention, preferably, the surface opposite to the surface on the wiring board side of the first film includes a plane having the same area as the first surface of the first element body. In addition, an example of the semiconductor device of the present invention further includes a second semiconductor element having a second element body and a second element electrode provided in the second element body, and the second element body The second semiconductor element is disposed on the first film so that the opposite surface of the part including the surface of the second element electrode faces the plane of the first film.

本発明の半導体装置の一例において、好ましくは、第２の半導体素子の第２の素子電極の表面を含む面の少なくとも一部と、配線基板の第２の半導体素子側の面の少なくとも一部とを覆う第２のフィルムと、第２フィルムの配線基板側の面に形成され、第１端と第２端とを有する第２の配線を含む第４の配線層とをさらに備え、第２の配線の第１端と第２の素子電極とが接合され、第１の配線の第２端が接合された第１の配線層の上記一部とは異なる第１の配線層の他の一部と、第２の配線の第２端とが接合されている。   In an example of the semiconductor device of the present invention, preferably, at least a part of a surface including the surface of the second element electrode of the second semiconductor element, and at least a part of a surface of the wiring substrate on the second semiconductor element side, And a second wiring layer formed on a surface of the second film on the side of the wiring board and including a second wiring having a first end and a second end, and a second wiring layer. The other part of the first wiring layer different from the part of the first wiring layer in which the first end of the wiring and the second element electrode are joined and the second end of the first wiring is joined. And the second end of the second wiring are joined.

本発明の半導体装置の一例において、好ましくは、絶縁性基板の第１の配線層が形成された面側に凹部が形成されており、凹部内に、第１の半導体素子が配置されている。   In an example of the semiconductor device of the present invention, preferably, a concave portion is formed on a surface side of the insulating substrate on which the first wiring layer is formed, and the first semiconductor element is disposed in the concave portion.

本発明の半導体装置の一例において、好ましくは、絶縁性基板の第１の配線層が形成された面と、第１の素子本体部の第１面とが、実質的に同一面内にある。   In an example of the semiconductor device of the present invention, preferably, the surface of the insulating substrate on which the first wiring layer is formed and the first surface of the first element main body are substantially in the same plane.

本発明の半導体装置の一例において、好ましくは、第１のフィルムの配線基板側の面の反対面は、実質的に平面である。   In an example of the semiconductor device of the present invention, preferably, the surface opposite to the surface on the wiring board side of the first film is substantially flat.

本発明の半導体装置の一例において、好ましくは、第２の素子本体部と第２の素子本体部に設けられた第２の素子電極とを有する第２の半導体素子をさらに含み、第２の半導体素子の第２の素子電極の表面を含む面の反対面と、第１のフィルムの上記平面とが向かい合うように、第２の半導体素子が第１のフィルム上に配置されている。   In one example of the semiconductor device of the present invention, preferably, the semiconductor device further includes a second semiconductor element having a second element body and a second element electrode provided in the second element body, and the second semiconductor The second semiconductor element is disposed on the first film so that the surface opposite to the surface including the surface of the second element electrode of the element faces the plane of the first film.

本発明の半導体装置の一例において、好ましくは、第２の半導体素子の第２の素子電極の表面を含む面の少なくとも一部と、配線基板の第２の半導体素子側の面の少なくとも一部とを覆う第２のフィルムと、第２フィルムの前記配線基板側の面に形成され、第１端と第２端とを有する第２の配線を含む第４の配線層と、をさらに備え、第２の配線の第１端と第２の素子電極とが接合され、第１の配線の第２端が接合された第１の配線層の一部とは異なる第１の配線層の他の一部と、第２の配線の第２端とが接合されている。   In an example of the semiconductor device of the present invention, preferably, at least a part of a surface including the surface of the second element electrode of the second semiconductor element, and at least a part of a surface of the wiring substrate on the second semiconductor element side, And a fourth wiring layer formed on a surface of the second film on the wiring board side and including a second wiring having a first end and a second end, and The other end of the first wiring layer is different from the part of the first wiring layer in which the first end of the second wiring and the second element electrode are joined, and the second end of the first wiring is joined. And the second end of the second wiring are joined.

本発明の半導体装置の一例において、好ましくは、配線基板は、プリント基板またはガラス基板である。   In one example of the semiconductor device of the present invention, preferably, the wiring board is a printed board or a glass substrate.

本発明の半導体装置の製造方法の一例において、好ましくは、実装工程において、第１の半導体素子と配線基板とを接合する。   In an example of the method for manufacturing a semiconductor device of the present invention, preferably, in the mounting process, the first semiconductor element and the wiring substrate are bonded.

本発明の半導体装置の製造方法の一例において、好ましくは、実装工程において、第１の半導体素子と配線基板とを接合した後、第１の配線の第１端と第１の素子電極とを接合し、第１の配線の第２端と第１の配線層の一部とを接合する。   In an example of the method for manufacturing a semiconductor device of the present invention, preferably, in the mounting step, the first semiconductor element and the wiring substrate are joined, and then the first end of the first wiring and the first element electrode are joined. Then, the second end of the first wiring and a part of the first wiring layer are joined.

本発明の半導体装置の製造方法の一例において、好ましくは、実装工程において、第１の配線の第１端と第１の素子電極とを接合した後、第１の半導体素子と配線基板とを接合する。   In an example of the method for manufacturing a semiconductor device of the present invention, preferably, in the mounting step, the first end of the first wiring and the first element electrode are bonded, and then the first semiconductor element and the wiring substrate are bonded. To do.

本発明の半導体装置の製造方法の一例において、好ましくは、実装工程において、超音波振動を用いて、第１の配線の第１端と第１の素子電極とを接合し、第１の配線の第２端と第１の配線層の一部とを接合する。   In an example of the method for manufacturing a semiconductor device of the present invention, preferably, in the mounting process, the first end of the first wiring and the first element electrode are bonded using ultrasonic vibration, and the first wiring is formed. The second end and a part of the first wiring layer are joined.

本発明の半導体装置の製造方法の一例において、好ましくは、実装工程において、シート状物の第２の配線層側の面の一部を、第１の半導体素子の第１の素子電極の表面を含む面に、直接または間接的に密着させる。例えば、フィルムは樹脂を含み、実装工程において、フィルムを加熱して熱収縮させることにより、シート状物を、第１の半導体素子の第１の素子電極の表面を含む面に密着させる。   In one example of the method for manufacturing a semiconductor device of the present invention, preferably, in the mounting step, a part of the surface of the sheet-like material on the second wiring layer side is formed on the surface of the first element electrode of the first semiconductor element. Adhere directly or indirectly to the containing surface. For example, the film contains a resin, and in the mounting process, the film is heated and thermally contracted, thereby bringing the sheet-like material into close contact with the surface including the surface of the first element electrode of the first semiconductor element.

本発明の半導体装置の製造方法の一例において、好ましくは、実装工程において、フィルムを加熱し、加圧して、フィルムの第２の配線層側の面の反対面を平面とする。   In an example of the method for manufacturing a semiconductor device of the present invention, preferably, in the mounting step, the film is heated and pressed to make the surface opposite to the surface on the second wiring layer side of the film a flat surface.

本発明の半導体装置の製造方法の一例において、好ましくは、フィルムは未硬化状態の熱硬化性樹脂を含み、実装工程において、シート状物を所定の形状に加工した後、加熱により上記熱硬化性樹脂を硬化して、シート状物を第１の半導体素子の第１の素子電極の表面を含む面の少なくとも一部と、配線基板の第１の半導体素子側の面の少なくとも一部とを覆うことができる形状に加工した後、第１の配線の第１端と第１の素子電極とを接合し、第１の配線の第２端と第１の配線層の一部とを接合する。   In an example of the method for producing a semiconductor device of the present invention, preferably, the film contains an uncured thermosetting resin, and in the mounting step, the sheet-like material is processed into a predetermined shape, and then the thermosetting property is heated by heating. The resin is cured to cover the sheet-like material with at least part of the surface including the surface of the first element electrode of the first semiconductor element and at least part of the surface of the wiring substrate on the first semiconductor element side. After processing into a shape that can be performed, the first end of the first wiring and the first element electrode are joined, and the second end of the first wiring and a part of the first wiring layer are joined.

本発明の半導体装置の製造方法の一例において、好ましくは、絶縁性基板の第１の配線層が形成された面側に凹部が形成されており、実装工程において、第１の半導体素子を、凹部内に配置する。   In one example of the method for manufacturing a semiconductor device of the present invention, preferably, a recess is formed on the surface side of the insulating substrate on which the first wiring layer is formed. In the mounting step, the first semiconductor element is inserted into the recess. Place in.

本発明の半導体装置の製造方法の一例において、好ましくは、実装工程の後に、フィルムの第２の配線層が形成された面の反対面上に、第２の素子電極を有する第２の半導体素子を配置する工程をさらに含み、この工程において、第２の半導体素子の第２の素子電極の表面を含む面の反対面とフィルムの平面とが向かい合うように、第２の半導体素子をフィルム上に配置する。   In an example of the method for manufacturing a semiconductor device of the present invention, preferably, after the mounting step, the second semiconductor element having the second element electrode on the surface opposite to the surface on which the second wiring layer of the film is formed. And in this step, the second semiconductor element is placed on the film so that the opposite surface of the second semiconductor element including the surface of the second element electrode faces the plane of the film. Deploy.

以下、図面を参照しながら、本発明の半導体装置およびその製造方法の一例を説明する。以下の図面においては、説明の簡潔化のため、実質的に同一の機能を有する構成要素には同一の参照符号を付す。尚、本発明は下記の実施形態に限定されない。   Hereinafter, an example of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings. In the following drawings, components having substantially the same functions are denoted by the same reference numerals for the sake of brevity. In addition, this invention is not limited to the following embodiment.

（実施形態１）
図１〜図３を参照しながら、本実施形態の半導体装置について説明する。図１Ａは、本実施形態の半導体装置を模式的に示す断面図であり、図１Ｂは、図１Ａの半導体装置を模式的に示す上面図である。図２は、図１Ａの半導体装置を模式的に示す斜視図であり、図３は、他の半導体装置を模式的に示す断面図である。 (Embodiment 1)
The semiconductor device of this embodiment will be described with reference to FIGS. FIG. 1A is a cross-sectional view schematically showing the semiconductor device of this embodiment, and FIG. 1B is a top view schematically showing the semiconductor device of FIG. 1A. 2 is a perspective view schematically showing the semiconductor device of FIG. 1A, and FIG. 3 is a cross-sectional view schematically showing another semiconductor device.

図１Ａ、図１Ｂおよび図２に示した半導体装置１００は、第１の半導体素子１０１Ａと、配線基板（インターポーザー基板）３０１と、第１のフィルム２０と、第２の配線層２５とから構成されている。第１の半導体素子１０１Ａは、第１の素子本体部１０と、第１の素子本体部１０の第１面１０ａに設けられた第１の素子電極１２ａとを有しており、例えばベアチップである。配線基板３０１は、絶縁性基板３０と、絶縁性基板３０の一方の主面に形成された第１の配線層３２とを含んでいる。配線基板３０１は、例えば、リジッド基板（一例を挙げると、典型的なプリント基板）である。   A semiconductor device 100 shown in FIGS. 1A, 1B, and 2 includes a first semiconductor element 101A, a wiring board (interposer board) 301, a first film 20, and a second wiring layer 25. Has been. The first semiconductor element 101A includes a first element body 10 and a first element electrode 12a provided on the first surface 10a of the first element body 10 and is, for example, a bare chip. . The wiring substrate 301 includes an insulating substrate 30 and a first wiring layer 32 formed on one main surface of the insulating substrate 30. The wiring board 301 is, for example, a rigid board (a typical printed board, for example).

図１Ａに示すように、第１の半導体素子１０１Ａは、第１の素子本体部１０の第１面１０ａに対向する第２面１０ｂが、絶縁性基板３０の第１の配線層３２が形成された面と向かい合うように、配線基板３０１上に配置されている。   As shown in FIG. 1A, in the first semiconductor element 101A, the second surface 10b opposite to the first surface 10a of the first element body 10 is formed with the first wiring layer 32 of the insulating substrate 30. It is disposed on the wiring board 301 so as to face the surface.

図１Ａ、図１Ｂおよび図２に示すように、第１のフィルム２０は、第１の半導体素子１０１Ａの第１の素子電極１２ａの表面を含む面（第２面１０ｂに対向する面、または第１面１０ａと第１の素子電極１２ａの表面とを含む面）の少なくとも一部と、配線基板３０１の第１の半導体素子１０１Ａ側の面の少なくとも一部とを覆っている。   As shown in FIG. 1A, FIG. 1B, and FIG. 2, the first film 20 is a surface including the surface of the first element electrode 12a of the first semiconductor element 101A (the surface facing the second surface 10b, or the first 1 surface 10a and the surface of the first element electrode 12a) and at least a part of the surface of the wiring substrate 301 on the first semiconductor element 101A side.

第１のフィルム２０の配線基板３０１側の面には、第２の配線層２５が形成されている。第２の配線層は２５は、第１端と第２端とを有する第１の配線２２を複数含んでいる。各第１の配線２２の第１端は、第１の半導体素子１０１Ａの第１の素子電極１２ａに接しており、第２端は、第１の配線層３２の一部に接している。したがって、第２の配線層２５によって、第１の半導体素子１０１Ａと、配線基板３０１とが電気接続されている。   A second wiring layer 25 is formed on the surface of the first film 20 on the wiring substrate 301 side. The second wiring layer 25 includes a plurality of first wirings 22 having a first end and a second end. The first end of each first wiring 22 is in contact with the first element electrode 12a of the first semiconductor element 101A, and the second end is in contact with a part of the first wiring layer 32. Therefore, the first semiconductor element 101 </ b> A and the wiring substrate 301 are electrically connected by the second wiring layer 25.

第１の配線２２の第１端と第１の素子電極１２ａとの接合、および、第１の配線２２の第２端と第１の配線層３２の一部との接合は、例えば、超音波振動を利用してなされている。超音波振動を用いた接合では、例えば、半田を用いて接合する場合よりも、短時間および低温で接合できる点で好ましい。   The bonding between the first end of the first wiring 22 and the first element electrode 12a and the bonding between the second end of the first wiring 22 and a part of the first wiring layer 32 are performed by, for example, ultrasonic waves. It is made using vibration. Joining using ultrasonic vibration is preferable in that joining can be performed in a short time and at a low temperature, compared to, for example, joining using solder.

上記のような構造をした本実施形態の半導体装置１００では、ＷＢ法、ＦＣ法、ＴＡＢ法を採用した半導体装置と比較して、後述する種々の特徴および利点を有している。   The semiconductor device 100 of the present embodiment having the above-described structure has various features and advantages to be described later as compared with the semiconductor device adopting the WB method, the FC method, and the TAB method.

本実施形態の半導体装置１００では、電気絶縁性基板３０の第１の配線層３２が形成された面と、第１の素子本体部１０の第２面１０ｂとが向かい合うように、第１の半導体素子１０１Ａと配線基板３０１とが配置されているので、第１の半導体素子１０１Ａはダイボンディングにより電気絶縁性基板３０に接合できる。そのため、半導体装置１００は、ＦＣ法を採用した半導体装置よりも放熱性が優れている。   In the semiconductor device 100 of the present embodiment, the first semiconductor is arranged such that the surface of the electrically insulating substrate 30 on which the first wiring layer 32 is formed faces the second surface 10b of the first element body 10. Since the element 101A and the wiring substrate 301 are arranged, the first semiconductor element 101A can be bonded to the electrically insulating substrate 30 by die bonding. Therefore, the semiconductor device 100 has better heat dissipation than a semiconductor device employing the FC method.

ダイボンディングに用いられる接合材１３（図１Ａ参照）について特に制限はなく、従来からダイボンディングに用いられている接合材を用いればよい。例えば、接合材には、ダイボンディングフィルム、ポリマー型導電性ペースト、はんだ等を用いればよい。   There is no particular limitation on the bonding material 13 (see FIG. 1A) used for die bonding, and a bonding material conventionally used for die bonding may be used. For example, a die bonding film, a polymer type conductive paste, solder, or the like may be used as the bonding material.

また、本実施形態の半導体装置１００では、第２の配線層２５の第１の配線２２によって、第１の半導体素子１０１Ａと配線基板３０１とが電気的に接続されている。そのため、製造過程において、ワイヤーボンディングパット５０２と外部端子５０５とをボンディングワイヤによって接続する作業を、何度も繰り返す必要はない（図１７参照）。半導体装置１００では、第２の配線層２５によって、複数の第１の素子電極１２ａと第１の配線層３２とを電気接続しており、ＷＢ法を採用した半導体装置よりも、製造過程における作業の手間が軽減されており生産性もよい。   In the semiconductor device 100 of this embodiment, the first semiconductor element 101A and the wiring board 301 are electrically connected by the first wiring 22 of the second wiring layer 25. Therefore, it is not necessary to repeat the operation of connecting the wire bonding pad 502 and the external terminal 505 with the bonding wire many times during the manufacturing process (see FIG. 17). In the semiconductor device 100, the plurality of first element electrodes 12a and the first wiring layer 32 are electrically connected by the second wiring layer 25, and the work in the manufacturing process is more than that of the semiconductor device employing the WB method. The productivity of this product is also reduced.

また、本実施形態の半導体装置１００では、ＷＢ法を採用した半導体装置よりも、隣り合う配線間の間隔を狭くすることが可能である。ボンディングワイヤは、その両端部のみが固定され、それ以外の部分は固定されていない。それゆえ、封止樹脂により封止される際の封止樹脂の流れにより、隣り合うボンディングワイヤが接しない程度に、隣り合うボンディングワイヤ間の間隔を設定しておくことが必要とされる。一方、半導体装置１００では、第１のフィルム２０に形成された第２の配線層２５によって、第１の半導体素子１０１Ａと配線基板３０１とが電気接続されているので、ボンディングワイヤを用いた場合のように、隣り合う配線（ボンディングワイヤ）間隔を広めに設定する必要はない。したがって、ＷＢ法を採用した半導体装置よりも、配線間の間隔を狭くすることができる。   Further, in the semiconductor device 100 of the present embodiment, the interval between adjacent wirings can be narrower than that of a semiconductor device employing the WB method. Only both ends of the bonding wire are fixed, and other portions are not fixed. Therefore, it is necessary to set an interval between the adjacent bonding wires so that the adjacent bonding wires do not come into contact with each other due to the flow of the sealing resin when sealing with the sealing resin. On the other hand, in the semiconductor device 100, since the first semiconductor element 101A and the wiring board 301 are electrically connected by the second wiring layer 25 formed on the first film 20, the bonding wire is used. Thus, it is not necessary to set the interval between adjacent wires (bonding wires) wider. Therefore, the interval between wirings can be narrower than that of a semiconductor device employing the WB method.

また、本実施形態の半導体装置１００では、第１のフィルム２０に形成された第１の配線２２によって第１の半導体素子１０１Ａと配線基板３０１とが電気接続されているので、ＷＢ法を採用した半導体装置よりも、半導体装置を薄型化できる。   Further, in the semiconductor device 100 of the present embodiment, since the first semiconductor element 101A and the wiring substrate 301 are electrically connected by the first wiring 22 formed on the first film 20, the WB method is adopted. The semiconductor device can be made thinner than the semiconductor device.

また、本実施形態の半導体装置１００では、ＦＣ法を採用した半導体装置よりも、隣り合う配線間の狭ピッチ化に伴うコストアップを抑制できる。ＦＣ法を採用する半導体装置では、配線基板の所定の領域、すなわち、半導体素子と面する領域に、数多くの端子（配線層のうちのバンプとの接続部）が集中的に配置される。それに伴って、配線基板の多層化が必要となる場合が多い。しかし、多層構造の配線基板を用いるとコストアップしてしまう。本実施形態の半導体装置１０１では、第１のフィルム２０に形成された、所望のパターンの第２の配線層２５を構成する第１の配線２２によって第１の半導体素子１０１Ａと配線基板３０１とが電気接続されているので、ＦＣ法を採用した半導体装置と比較して、配線基板３０１の多層化を抑制でき、コストアップを抑制できる。   Moreover, in the semiconductor device 100 of this embodiment, the cost increase accompanying the narrow pitch between adjacent wirings can be suppressed as compared with the semiconductor device adopting the FC method. In a semiconductor device adopting the FC method, a large number of terminals (connection portions with bumps in the wiring layer) are intensively arranged in a predetermined region of the wiring substrate, that is, a region facing the semiconductor element. Along with this, it is often necessary to increase the number of wiring boards. However, the use of a multilayered wiring board increases the cost. In the semiconductor device 101 of the present embodiment, the first semiconductor element 101A and the wiring substrate 301 are formed by the first wiring 22 that forms the second wiring layer 25 having a desired pattern formed on the first film 20. Since they are electrically connected, the wiring board 301 can be prevented from being multi-layered and the cost can be increased as compared with a semiconductor device employing the FC method.

また、本実施形態の半導体装置１００では、第１の半導体素子１０１Ａの線熱膨張係数と第１のフィルム２０の線熱膨張係数とのマッチングは、ＦＣ法を採用した半導体装置の場合よりも、厳格でなくてもよい。その理由は、第１のフィルム２０は配線基板よりも薄いからである。また、第１のフィルム２０は、その可撓性によって、第１のフィルム２０の線熱膨張係数と第１の半導体素子１０１Ａの線熱膨張係数との差異に起因して生じる応力を吸収することができるからである。   Further, in the semiconductor device 100 of the present embodiment, the matching between the linear thermal expansion coefficient of the first semiconductor element 101A and the linear thermal expansion coefficient of the first film 20 is more than in the case of the semiconductor device adopting the FC method. It doesn't have to be strict. The reason is that the first film 20 is thinner than the wiring board. Further, the first film 20 absorbs stress caused by the difference between the linear thermal expansion coefficient of the first film 20 and the linear thermal expansion coefficient of the first semiconductor element 101A due to its flexibility. Because you can.

また、本実施形態の半導体装置１００では、ＦＣ法を採用した半導体装置に使用されるアンダーフィル剤（封止樹脂）が不要である。したがって、封止樹脂を注入する工程が不要であり、生産性もよい。また、第１の素子電極１２ａと第１の配線２２との接続部、および第１の配線層３２と第１の配線２２との接続部が、第１のフィルム２０によって保護されているので、電気接続の信頼性も優れている。   Further, in the semiconductor device 100 of this embodiment, an underfill agent (sealing resin) used for a semiconductor device adopting the FC method is unnecessary. Therefore, the step of injecting the sealing resin is unnecessary and the productivity is good. Moreover, since the connection part of the 1st element electrode 12a and the 1st wiring 22, and the connection part of the 1st wiring layer 32 and the 1st wiring 22 are protected by the 1st film 20, Excellent electrical connection reliability.

また、本実施形態の半導体装置１００では、第１の配線２２によって第１の半導体素子１０１Ａと配線基板３０１とが電気接続されているので、インナーリードボンディング（ＩＬＢ）工程と、アウターリードボンディング（ＯＬＢ）工程とを別々に行う必要がある、ＴＡＢ法を採用した半導体装置よりも簡単に製造できる。また、本実施形態の半導体装置１００では、ＴＡＢ法を採用した半導体装置のように封止樹脂で半導体素子を封止する工程が不要であり、生産性がよい。   Further, in the semiconductor device 100 of the present embodiment, the first semiconductor element 101A and the wiring substrate 301 are electrically connected by the first wiring 22, so that an inner lead bonding (ILB) process and an outer lead bonding (OLB) are performed. ) Can be manufactured more easily than a semiconductor device employing the TAB method, which needs to be performed separately. Further, the semiconductor device 100 of this embodiment does not require a step of sealing a semiconductor element with a sealing resin unlike a semiconductor device employing the TAB method, and has high productivity.

本実施形態の半導体装置１００において、第１のフィルム２０は、実質的に透明であると好ましい。第１のフィルム２０が実質的に透明であると、第２の配線層２５を第１のフィルム２０越しに見ることができる。また、第１のフィルム２０越しに第１の素子電極１２ａの位置を確認することもできる。そのため、ＦＣ法を採用した半導体装置におけるバンプと配線基板の配線との位置合わせよりも、第１の配線２２の第１端と第１の素子電極１２ａとの位置合わせ、および、第１の配線２２の第２端と第１の配線層３２との位置合わせの方が容易である。また、ＦＣ法を採用した半導体装置の場合、接続状況の目視による確認は困難である。一方、本実施形態の半導体装置１００では、第１のフィルム２０が実質的に透明である場合は、接続確認が目視により容易に行える。   In the semiconductor device 100 of this embodiment, it is preferable that the first film 20 is substantially transparent. If the first film 20 is substantially transparent, the second wiring layer 25 can be seen through the first film 20. In addition, the position of the first element electrode 12 a can be confirmed through the first film 20. Therefore, the alignment between the first end of the first wiring 22 and the first element electrode 12a, and the first wiring, rather than the alignment between the bump and the wiring on the wiring board in the semiconductor device adopting the FC method. It is easier to align the second end of 22 and the first wiring layer 32. In the case of a semiconductor device adopting the FC method, it is difficult to visually confirm the connection status. On the other hand, in the semiconductor device 100 of this embodiment, when the first film 20 is substantially transparent, connection confirmation can be easily performed by visual observation.

第１のフィルム２０は、例えば、透光性を有する絶縁性の樹脂にて形成されている。上記樹脂には、例えば、熱可塑性樹脂（ポリイミド、ＰＰＳ（ポリフェニレンサルファイド）、ポリプロピレン、ポリメタクリル酸メチル等が挙げられる。第１のフィルム２０の厚さは、例えば、１０μｍ〜１００μｍであり、特には、５０μｍ以下であると好ましい。第１のフィルム２０上に形成された第１の配線２２（第２の配線層２５）は、例えば、銅にて形成されている。第１の配線２２の厚さは、例えば、５μｍ〜３５μｍであると好ましい。尚、第１の半導体素子（ベアチップ）１０１Ａの厚さは、例えば、５０μｍ〜４００μｍであると好ましい。   The first film 20 is made of, for example, an insulating resin having translucency. Examples of the resin include thermoplastic resins (polyimide, PPS (polyphenylene sulfide), polypropylene, polymethyl methacrylate, etc.) The thickness of the first film 20 is, for example, 10 μm to 100 μm, particularly The first wiring 22 (second wiring layer 25) formed on the first film 20 is made of, for example, copper, and the thickness of the first wiring 22 is 50 μm or less. For example, the thickness of the first semiconductor element (bare chip) 101A is preferably 50 μm to 400 μm, for example.

図１Ａ、図１Ｂおよび図２に示すように、第１のフィルム２０は、第１の半導体素子１０１Ａと、配線基板３０１の第１の配線層３２の一部（第１の配線２２が接触している部位）とを覆っている。また、図１Ａに示すように、第１のフィルム２０と第２の配線層２５とからなる積層体５０の第２の配線層２５側の面の一部は、第１の半導体素子１０１Ａの第１の素子電極１２ａの表面を含む面に、直接または間接的に密着している。これにより、第１の配線２２の第１端と第１の素子電極１２ａの接合部が第１のフィルム２０によって保護され、接続安定性が向上するので好ましい。積層体５０の第２の配線層側の面の上記一部とは異なる他の一部と、第１の素子本体部１０の４つの側面のうちの少なくとも１つの側面とが、直接または間接的に密着していると、さらに接続安定性が向上するので好ましい。   As shown in FIGS. 1A, 1B, and 2, the first film 20 includes a first semiconductor element 101A and a part of the first wiring layer 32 of the wiring board 301 (the first wiring 22 is in contact with the first film 20). Covering the part). Further, as shown in FIG. 1A, a part of the surface on the second wiring layer 25 side of the laminated body 50 formed of the first film 20 and the second wiring layer 25 is a part of the first semiconductor element 101A. It is in direct or indirect contact with the surface including the surface of one element electrode 12a. This is preferable because the joint between the first end of the first wiring 22 and the first element electrode 12a is protected by the first film 20 and the connection stability is improved. Another part different from the part of the surface on the second wiring layer side of the stacked body 50 and at least one side surface of the four side surfaces of the first element body 10 are directly or indirectly. It is preferable to be in close contact with the surface because the connection stability is further improved.

尚、図１Ａに示した例では、第１のフィルム２０と第２の配線層２５とからなる積層体５０の第２の配線層２５側の面の一部が、配線基板３０１にも密着している。すなわち、積層体５０の配線基板側の面が、第１の半導体素子１０１Ａおよび配線基板３０１に直接または間接的に接合されて、積層体５０と配線基板３０１によって囲われる密閉空間内に第１の半導体素子１０１Ａが配置されている。したがって、図１Ａに示した半導体装置１００は、第１の配線２２の第２端と第１の配線層３２の接合部の接続安定性もよい。また、第１のフィルム２０の材料に水蒸気透過性の低い材料を用いた場合には、第１の半導体素子１０１Ａを湿気から保護でき、半導体装置の耐湿性が向上する。水蒸気透過性の低い材料としては、例えば、ポリ塩化ビニリデン、ポリエチレンービニルアルコール等が挙げられるが、特に、高い透明性も兼備えたセラミック蒸着フィルムが好ましい。   In the example shown in FIG. 1A, a part of the surface on the second wiring layer 25 side of the laminate 50 composed of the first film 20 and the second wiring layer 25 is in close contact with the wiring substrate 301. ing. That is, the surface of the multilayer body 50 on the wiring board side is directly or indirectly joined to the first semiconductor element 101 </ b> A and the wiring board 301, so that the first space is surrounded by the multilayer body 50 and the wiring board 301. A semiconductor element 101A is arranged. Therefore, the semiconductor device 100 shown in FIG. 1A has good connection stability between the second end of the first wiring 22 and the joint portion of the first wiring layer 32. In addition, when a material having low water vapor permeability is used as the material of the first film 20, the first semiconductor element 101A can be protected from moisture, and the moisture resistance of the semiconductor device is improved. Examples of the material having low water vapor permeability include polyvinylidene chloride and polyethylene-vinyl alcohol, and a ceramic vapor-deposited film having high transparency is particularly preferable.

上記積層体５０を第１の素子電極１２ａおよび第１の素子本体部１０の第１面１０ａ等に密着させる方法としては、例えば、第１の半導体素子１０１Ａの第１の素子電極１２ａの表面を含む面に第１のフィルム２０を貼り付けた後、第１のフィルム２０を熱収縮させる方法等が挙げられる。   As a method for bringing the stacked body 50 into close contact with the first element electrode 12a and the first surface 10a of the first element body 10, the surface of the first element electrode 12a of the first semiconductor element 101A is, for example, Examples include a method in which the first film 20 is heat-shrinked after the first film 20 is attached to the surface to be included.

図１Ａに示した半導体装置１００では、第１の素子電極１２ａと第１の配線２２とが直接接合されているが、バンプ（例えば、半田バンプ、金バンプ）を介して接合されていてもよい。   In the semiconductor device 100 shown in FIG. 1A, the first element electrode 12a and the first wiring 22 are directly bonded, but may be bonded via a bump (for example, a solder bump or a gold bump). .

尚、図１Ｂおよび図２に示した例では、１６個の第１の素子電極１２ａを有した第１の半導体素子１０１Ａが用いられているが、第１の素子電極１２ａの数はこれに限定されず、例えば、１６個よりも多くてもよいし、少なくてもよい。また、図１Ｂおよび図２に示した例では、第１の素子電極１２ａが第１の素子本体部１０の周縁部に配列された第１の半導体素子１０１Ａが用いられているが、第１の半導体素子１０１Ａはこれに限定されず、第１の素子電極１２ａがアレイ状（格子状）に配列された第１の半導体素子１０１Ａを用いてもよい。   In the example shown in FIG. 1B and FIG. 2, the first semiconductor element 101A having 16 first element electrodes 12a is used, but the number of the first element electrodes 12a is limited to this. For example, it may be more or less than 16. In the example shown in FIGS. 1B and 2, the first semiconductor element 101 </ b> A in which the first element electrode 12 a is arranged on the peripheral edge of the first element body 10 is used. The semiconductor element 101A is not limited to this, and the first semiconductor element 101A in which the first element electrodes 12a are arranged in an array (lattice) may be used.

また、図１および図２に示した例では、第１の半導体素子１０１Ａ（第１の素子本体部１０）の側面に第１の配線２２が接しているが、本実施形態の半導体装置はこのような形態に制限されず、図３に示す半導体装置１００のように、第１の配線２２と第１の半導体素子１０１Ａの側面とが接していなくてもよい。また、図１Ａおよび図１Ｂに示すように、第１の配線２２の第１端によって第１の素子電極１２ａの全体が覆われていてもよいし、図３に示すように、第１の配線２２の第１端と第１の素子電極１２ａの上面のみとが接していてもよい。   In the example shown in FIG. 1 and FIG. 2, the first wiring 22 is in contact with the side surface of the first semiconductor element 101A (first element body 10). The first wiring 22 and the side surface of the first semiconductor element 101A do not have to be in contact with each other as in the semiconductor device 100 illustrated in FIG. Further, as shown in FIGS. 1A and 1B, the first element electrode 12a may be entirely covered by the first end of the first wiring 22, or as shown in FIG. The first end of 22 may be in contact with only the upper surface of the first element electrode 12a.

次に、図４Ａ〜図６Ｂを参照しながら、本実施形態の半導体装置１００の製造方法の一例について説明する。   Next, an example of a method for manufacturing the semiconductor device 100 of this embodiment will be described with reference to FIGS. 4A to 6B.

まず、図４Ａに示すように、第１の配線層３２が絶縁性基板３０の一方の主面に形成された配線基板３０１を用意する。配線基板３０１は、リジット基板であり、例えば、ガラス−エポキシ（エポキシ樹脂がガラス織布に含浸された）基板である。配線基板３０１は、ＢＴ（ビスマレイミド・トリアジン）基板、紙フェノール樹脂基板、アラミド−エポキシ（エポキシ樹脂がアラミド基板に含浸された）基板のような樹脂系基板であってもよいし、アルミナ基板、ガラス−アルミナ基板等のようなセラミック系基板であってもよい。   First, as shown in FIG. 4A, a wiring substrate 301 having a first wiring layer 32 formed on one main surface of the insulating substrate 30 is prepared. The wiring board 301 is a rigid board, for example, a glass-epoxy (epoxy resin impregnated in a glass woven fabric) board. The wiring substrate 301 may be a resin-based substrate such as a BT (bismaleimide / triazine) substrate, a paper phenolic resin substrate, an aramid-epoxy (an epoxy resin is impregnated with an aramid substrate), an alumina substrate, It may be a ceramic substrate such as a glass-alumina substrate.

図４Ａに示した配線基板３０１は、配線層が絶縁性基板３０の一方の主面にのみ形成された片面基板であるが、これに制限されない。配線基板３０１は、配線層が絶縁性基板３０の両主面に形成された両面基板、または、配線層が絶縁性基板の内部にも設けられた多層基板であってもよい。第１の配線層３２は、例えば、銅箔にて形成されている。   The wiring substrate 301 shown in FIG. 4A is a single-sided substrate in which the wiring layer is formed only on one main surface of the insulating substrate 30, but is not limited thereto. The wiring substrate 301 may be a double-sided substrate in which a wiring layer is formed on both main surfaces of the insulating substrate 30 or a multilayer substrate in which the wiring layer is also provided inside the insulating substrate. The first wiring layer 32 is made of, for example, copper foil.

次に、図４Ｂに示すように、第１の素子本体部１０の第１面１０ａに第１の素子電極１２ａが設けられた第１の半導体素子１０１Ａを用意する。次いで、第１の素子本体部１０の第２面１０ｂが配線基板の絶縁性基板３０に向くように、第１の半導体素子１０１Ａを接合材１３を用いて配線基板（絶縁性基板３０）にダイボンディングする。第１の半導体素子１０１Ａは、例えば、いわゆるベアチップである。第１の素子電極１２ａは、例えば、アルミニウムまたはアルミニウムを主成分とする合金（Ａｌ−Ｃｕ、Ａｌ−Ｃｕ−Ｓｉ等）にて形成されている。   Next, as shown in FIG. 4B, a first semiconductor element 101 </ b> A in which a first element electrode 12 a is provided on the first surface 10 a of the first element body 10 is prepared. Next, the first semiconductor element 101A is bonded to the wiring substrate (insulating substrate 30) using the bonding material 13 so that the second surface 10b of the first element body 10 faces the insulating substrate 30 of the wiring substrate. Bond. The first semiconductor element 101A is, for example, a so-called bare chip. The first element electrode 12a is formed of, for example, aluminum or an alloy containing aluminum as a main component (Al—Cu, Al—Cu—Si, or the like).

一方で、図５Ａおよび図５Ｂに示すように、フィルムの一方の主面に第２の配線層が形成されたシート状物を形成する。まず、図５Ａに示すように、フィルム２０'上に金属層２１を形成する。フィルム２０'の材料は、例えば、ポリイミド、ＰＰＳ（ポリフェニレンサルファイド）、ポリプロピレン、ポリメタクリル酸メチル等である。図５Ａに示したフィルム２０'は、透明な材料、例えば、ポリメタクリル酸メチルから形成されている。金属層２１は、例えば、銅箔である。フィルム２０'上への金属層２１の形成は、例えば、金属箔の貼り合わせや、金属メッキによって行うことができる。フィルム２０'の厚みは、例えば、約１０μｍ〜１００μｍであり、金属層２１の厚さは、例えば、約５μｍ〜３５μｍである。   On the other hand, as shown to FIG. 5A and FIG. 5B, the sheet-like material in which the 2nd wiring layer was formed in one main surface of a film is formed. First, as shown in FIG. 5A, a metal layer 21 is formed on a film 20 ′. The material of the film 20 ′ is, for example, polyimide, PPS (polyphenylene sulfide), polypropylene, polymethyl methacrylate, or the like. The film 20 ′ shown in FIG. 5A is made of a transparent material, for example, polymethyl methacrylate. The metal layer 21 is, for example, a copper foil. Formation of the metal layer 21 on the film 20 ′ can be performed by, for example, bonding metal foils or metal plating. The thickness of the film 20 ′ is, for example, about 10 μm to 100 μm, and the thickness of the metal layer 21 is, for example, about 5 μm to 35 μm.

次に、所定のパターンが得られるように金属層２１をエッチングして、図５Ｂに示すように、フィルム２０'の一方の主面に第１の配線２２を含む第２の配線層２５を形成する。エッチングは、例えば、フォトレジストを用いて所定の個所にマスクをした後、塩化鉄や塩化銅を用いて金属層２１のうちの不要な部分を化学的に除去することにより行えばよい。   Next, the metal layer 21 is etched so as to obtain a predetermined pattern, and as shown in FIG. 5B, a second wiring layer 25 including the first wiring 22 is formed on one main surface of the film 20 ′. To do. Etching may be performed, for example, by masking a predetermined portion using a photoresist and then chemically removing unnecessary portions of the metal layer 21 using iron chloride or copper chloride.

次に、図６Ａに示すように、第１の半導体素子１０１Ａの第１の素子電極１２ａの表面を含む面、および配線基板３０１の第１の半導体素子１０１Ａ側の面の一部を、第２の配線層２５とフィルム２０'とからなるシート状物５０'で覆う。この時、第２の配線層２５を構成する第１の配線２２の第１端が第１の素子電極１２ａに接し、かつ、第１の配線２２の第２端が配線基板３０１の第１の配線層３２の一部に接するように位置合わせを行う。この位置合わせは、フィルム２０'が実質的に透明であれば容易に行える。尚、第１の素子電極１２ａ上に、バンプが形成されていてもよく、バンプを介して第１の素子電極１２ａと第１の配線２２の第１端とを接合してもよい。   Next, as shown in FIG. 6A, a surface including the surface of the first element electrode 12a of the first semiconductor element 101A and a part of the surface of the wiring substrate 301 on the first semiconductor element 101A side are Is covered with a sheet-like material 50 'composed of the wiring layer 25 and the film 20'. At this time, the first end of the first wiring 22 constituting the second wiring layer 25 is in contact with the first element electrode 12 a, and the second end of the first wiring 22 is the first of the wiring substrate 301. Positioning is performed so as to contact a part of the wiring layer 32. This alignment can be easily performed if the film 20 'is substantially transparent. Note that a bump may be formed on the first element electrode 12a, and the first element electrode 12a and the first end of the first wiring 22 may be joined via the bump.

次に、図６Ｂに示すように、第１の半導体素子１０１Ａの配線基板３０１と接した面を除く全て表面および配線基板３０１の第１の半導体素子１０１Ａ側の面の一部に、フィルム２０'と第２の配線層２５とからなるシート状物５０'を密着させる。密着方法としては、フィルム２０'の熱収縮等が挙げられる。フィルム２０'を熱収縮させる際に、雰囲気を減圧してもよい。   Next, as shown in FIG. 6B, a film 20 ′ is formed on the entire surface of the first semiconductor element 101A except the surface in contact with the wiring board 301 and on a part of the surface of the wiring board 301 on the first semiconductor element 101A side. And the second wiring layer 25 are brought into close contact with each other. Examples of the adhesion method include thermal shrinkage of the film 20 ′. When the film 20 ′ is thermally contracted, the atmosphere may be reduced.

また、フィルム２０'の熱収縮によりシート状物５０'を第１の半導体素子１０１Ａ等に密着させる場合、フィルム２０'の熱収縮の程度を考慮し、熱収縮後において、第１の配線２２の第１端と第１の素子電極１２ａ、および第１の配線２２の第２端と第１の配線層３２とを電気接続することができるように、第２の配線層２５をフィルム２０'に形成しておく必要がある。例えば、フィルム２０'の熱収縮の程度を考慮して、第２の配線層２５に含まれる複数の第１の配線２２間の間隔を広めにしておけばよい。   Further, when the sheet-like material 50 ′ is brought into close contact with the first semiconductor element 101A or the like by the thermal contraction of the film 20 ′, the degree of the thermal contraction of the film 20 ′ is taken into account and the first wiring 22 The second wiring layer 25 is formed on the film 20 ′ so that the first end and the first element electrode 12 a and the second end of the first wiring 22 and the first wiring layer 32 can be electrically connected. It is necessary to form. For example, in consideration of the degree of thermal contraction of the film 20 ′, the interval between the plurality of first wirings 22 included in the second wiring layer 25 may be widened.

尚、シート状物５０'の第１の半導体素子１０１Ａ等への密着が容易に行えるように、フィルム２０'の第１の半導体素子１０１Ａ等に対向する面に、例えば、部分的に接着剤を塗布等しておいてもよい。図６Ａおよび図６Ｂにおいて、３０は、絶縁性基板である。   Note that, for example, an adhesive is partially applied to the surface of the film 20 ′ facing the first semiconductor element 101A or the like so that the sheet-like object 50 ′ can be easily adhered to the first semiconductor element 101A or the like. Application may be made. 6A and 6B, reference numeral 30 denotes an insulating substrate.

次に、第１の配線２２の第１端と第１の素子電極１２ａ、および、第１の配線２２の第２端と第１の配線層３２の一部とを、例えば、超音波振動により一括して接合する。第１の配線２２の第１端と第１の素子電極１２ａ、および、第１の配線２２の第２端と第１の配線層３２の一部は、ともに、半田等を用いて接合してもよい。   Next, the first end of the first wiring 22 and the first element electrode 12a, and the second end of the first wiring 22 and a part of the first wiring layer 32, for example, by ultrasonic vibration Join together. The first end of the first wiring 22 and the first element electrode 12a, and the second end of the first wiring 22 and a part of the first wiring layer 32 are joined together using solder or the like. Also good.

本実施形態の半導体装置の製造方法では、未硬化状態の熱硬化性樹脂を含むフィルム２０'を用い、シート状物５０'を所定の形状に加工した後、加熱により熱硬化性樹脂を硬化して、シート状物５０'を、第１の半導体素子１０１Ａの第１の素子電極１２ａの表面を含む面と配線基板３０１の第１の半導体素子側の面の少なくとも一部とを覆うことができる形状に加工してから、第１の配線２２の第１端と第１の素子電極１２ａとを接合し、第１の配線２２の第２端と第１の配線層３２の一部とを接合してもよい。   In the method for manufacturing a semiconductor device of this embodiment, a film 20 ′ containing an uncured thermosetting resin is used to process the sheet-like material 50 ′ into a predetermined shape, and then the thermosetting resin is cured by heating. Thus, the sheet-like object 50 ′ can cover the surface including the surface of the first element electrode 12a of the first semiconductor element 101A and at least a part of the surface of the wiring substrate 301 on the first semiconductor element side. After processing into a shape, the first end of the first wiring 22 and the first element electrode 12a are joined, and the second end of the first wiring 22 and a part of the first wiring layer 32 are joined. May be.

尚、図４Ａ〜図６Ｂを用いて説明した本実施形態の半導体装置の製造方法では、第１の半導体素子１０１Ａと配線基板３０１とを接合した後、第１の配線２２の第１端と第１の素子電極１２ａとを接合し、第１の配線２２の第２端と第１の配線層３２の一部とを接合しているが、本実施形態の半導体装置の製造方法はこれに制限されない。例えば、第１の配線２２の第１端と第１の素子電極１２ａとを接合した後に、第１の半導体素子１０１Ａと配線基板３０１とを接合してもよい。第１の半導体素子１０１Ａと配線基板３０１とを接合する前に、第１の配線２２の第２端と第１の素子電極１２ａとを接合する場合は、第１の配線２２の第１端と第１の素子電極１２ａとの位置合わせが容易となり、好ましい。   In the method of manufacturing the semiconductor device according to this embodiment described with reference to FIGS. 4A to 6B, the first end of the first wiring 22 and the first end of the first wiring 22 are joined after the first semiconductor element 101A and the wiring substrate 301 are joined. The first element electrode 12a is joined, and the second end of the first wiring 22 and a part of the first wiring layer 32 are joined. However, the manufacturing method of the semiconductor device of this embodiment is limited to this. Not. For example, the first semiconductor element 101A and the wiring substrate 301 may be bonded after the first end of the first wiring 22 and the first element electrode 12a are bonded. In the case where the second end of the first wiring 22 and the first element electrode 12a are bonded before bonding the first semiconductor element 101A and the wiring substrate 301, the first end of the first wiring 22 Positioning with the first element electrode 12a is easy, which is preferable.

次に、図７〜図１１を参照しながら、本実施形態の半導体装置１００の他の例について説明する。   Next, another example of the semiconductor device 100 of the present embodiment will be described with reference to FIGS.

図７に示す半導体装置１００には、第１のフィルム２０の第２の配線層２５が形成された面の反対面に電磁波遮蔽層２４が形成されているので、第１の半導体素子から放射される電磁ノイズが外部に放射されるのを抑制できる。電磁波遮蔽層２４は、上記反対面のほぼ全面に形成されている。電磁波遮蔽層２４の材料としては、例えば、銅、ニッケル、金、鉄、銀およびフェライトからなる群から選ばれる少なくとも１種が挙げられる。   In the semiconductor device 100 shown in FIG. 7, since the electromagnetic wave shielding layer 24 is formed on the surface opposite to the surface on which the second wiring layer 25 of the first film 20 is formed, it is emitted from the first semiconductor element. Can be prevented from being radiated to the outside. The electromagnetic wave shielding layer 24 is formed on almost the entire opposite surface. Examples of the material of the electromagnetic wave shielding layer 24 include at least one selected from the group consisting of copper, nickel, gold, iron, silver, and ferrite.

図８に示す半導体装置１００では、第１のフィルム２０の配線基板３０１側の面の反対面が、第１の素子本体部の第１面１０ａと同面積以上の平面２０ａを含んでいる。このように第１のフィルム２０が上記平面２０ａを含んでいると、図９に示すように、この平面２０ａ上に電子部品（この例では、第２の半導体素子１０１Ｂ）を容易に配置できる。尚、上記平面２０ａの平担度は、第２の半導体素子１０１Ｂの配置が容易となる程度であれば十分である。   In the semiconductor device 100 shown in FIG. 8, the surface opposite to the surface on the wiring board 301 side of the first film 20 includes a flat surface 20a having the same area or more as the first surface 10a of the first element body. As described above, when the first film 20 includes the plane 20a, an electronic component (in this example, the second semiconductor element 101B) can be easily arranged on the plane 20a as shown in FIG. It should be noted that the flatness of the flat surface 20a is sufficient as long as the second semiconductor element 101B can be easily arranged.

第１のフィルム２０の配線基板３０１側の面の反対面を平面とするためには、例えば、第１のフィルム２０となるフィルム２０'（図６Ａ参照）が加熱されて柔らかくなっている状態の時に、フィルム２０'をプレスすればよい。   In order to make the surface opposite to the surface on the wiring board 301 side of the first film 20, for example, the film 20 ′ (see FIG. 6A) that becomes the first film 20 is heated and softened. Sometimes film 20 'may be pressed.

図９に示した半導体装置１００では、２つの半導体素子を含んでおり、第１の半導体素子１０１Ａの上方に第２の半導体素子１０１Ｂが配置されている。第１の半導体素子１０１Ａは、第２の配線層２５の第１の配線２２によって第１の配線層の一部３２Ａに接続されている。第２の半導体素子１０１Ｂは、ボンディングワイヤ４０によって、第１の配線２２が接した第１の配線層３２の一部３２Ａとは異なる第１の配線層３２の他の一部３２Ｂに接続されている。   The semiconductor device 100 shown in FIG. 9 includes two semiconductor elements, and the second semiconductor element 101B is disposed above the first semiconductor element 101A. The first semiconductor element 101 </ b> A is connected to a part 32 </ b> A of the first wiring layer by the first wiring 22 of the second wiring layer 25. The second semiconductor element 101B is connected to another part 32B of the first wiring layer 32 different from the part 32A of the first wiring layer 32 with which the first wiring 22 is in contact by the bonding wire 40. Yes.

図９に示した半導体装置１００は、第１の半導体素子１０１Ａ、および第２の半導体装置１０１ＢがともにＷＢ法にて配線基板３０１に電気接続された半導体装置よりも、下記のような利点を有する。第１の半導体素子１０１Ａ、および第２の半導体素子１０１ＢがともにＷＢ法にて配線基板３０１に電気接続された半導体装置では、図９に示した半導体装置１００のように、ほぼ同じ寸法の複数の半導体素子を上下に配置したスタック構造を採用することは困難である。その理由は、ほぼ同じ寸法の複数の半導体素子を上下に配置する場合、下に配置される半導体素子について、ボンディングワイヤで第１の素子電極と第１の配線層とを接続することが困難だからである。これに対して、本実施形態の半導体装置１００では、図９に示すように、第１の半導体素子１０１Ａについては、第１の配線２２を介して配線基板３０１に電気接続されているので、実質的に同じ寸法の第１の半導体素子１０１Ａ、および第２の半導体素子１０１Ｂを上下に配置したスタック構造の採用が容易である。   The semiconductor device 100 shown in FIG. 9 has the following advantages over the semiconductor device in which the first semiconductor element 101A and the second semiconductor device 101B are both electrically connected to the wiring substrate 301 by the WB method. . In a semiconductor device in which both the first semiconductor element 101A and the second semiconductor element 101B are electrically connected to the wiring substrate 301 by the WB method, a plurality of semiconductor devices having substantially the same dimensions as the semiconductor device 100 shown in FIG. It is difficult to adopt a stack structure in which semiconductor elements are arranged one above the other. The reason is that when a plurality of semiconductor elements having substantially the same dimensions are arranged one above the other, it is difficult to connect the first element electrode and the first wiring layer with bonding wires for the semiconductor elements arranged below. It is. On the other hand, in the semiconductor device 100 of this embodiment, as shown in FIG. 9, the first semiconductor element 101 </ b> A is electrically connected to the wiring substrate 301 via the first wiring 22. Therefore, it is easy to adopt a stack structure in which the first semiconductor element 101A and the second semiconductor element 101B having the same dimensions are arranged vertically.

また、第１の半導体素子１０１Ａ、および第２の半導体素子１０１ＢをともにＷＢ法で配線基板３０１に電気接続する場合、第２の半導体素子１０１Ｂの下に配置された第１の半導体素子１０１Ａに接続されたボンディングワイヤのループの高さについては、できるだけ低くする必要がある。しかし、本実施形態の半導体装置１００では、第１の半導体素子１０１Ａと配線基板３０１との接続にボンディングワイヤを用いておらず、第１の配線２２を介して第１の半導体素子１０１Ａと配線基板３０１とを電気接続しているので、ループの高さについて考慮する必要がない。   When both the first semiconductor element 101A and the second semiconductor element 101B are electrically connected to the wiring board 301 by the WB method, the first semiconductor element 101A and the second semiconductor element 101B are connected to the first semiconductor element 101A disposed below the second semiconductor element 101B. The height of the bonded bonding wire loop should be as low as possible. However, in the semiconductor device 100 of the present embodiment, no bonding wire is used to connect the first semiconductor element 101A and the wiring board 301, and the first semiconductor element 101A and the wiring board are connected via the first wiring 22. Since 301 is electrically connected, it is not necessary to consider the height of the loop.

第１のフィルム２０の上に第２の半導体素子１０１Ｂを配置する場合、半導体装置１００は、図１０に示すような形態をしていてもよい。図１０に示した半導体装置１００では、第２の半導体素子１０１Ｂの第２の素子電極１２ｂの表面を含む面の反対面と第１のフィルム２０の平面２０ａとが向かい合うように、第２の半導体素子１０１Ｂが第１のフィルム２０上に配置されている。   When the second semiconductor element 101B is arranged on the first film 20, the semiconductor device 100 may have a form as shown in FIG. In the semiconductor device 100 shown in FIG. 10, the second semiconductor element 101 </ b> B has the second semiconductor element 101 </ b> B so that the opposite surface of the second element electrode 12 b including the surface of the second semiconductor element 101 </ b> B faces the plane 20 a of the first film 20. The element 101B is disposed on the first film 20.

図１０に示した半導体装置１００は、第２のフィルム４１と、第２フィルム４１の配線基板３０１側の面に形成され、第２の配線４２を含む第４の配線層４５とを備えている。第２の配線４２は、第１端と第２端とを有している。第２フィルム４１は、第２の半導体素子１０１Ｂの第２の素子電極１２ｂの表面を含む面（第２の素子電極１２ｂの表面と第２の素子本体部１１の第１のフィルム２０側の面の反対面とを含む面）と、配線基板３０１の第２の半導体素子１０１Ｂ側の面の一部とを、第２の素子電極１２ｂ側から覆っている。   The semiconductor device 100 shown in FIG. 10 includes a second film 41 and a fourth wiring layer 45 formed on the surface of the second film 41 on the wiring substrate 301 side and including the second wiring 42. . The second wiring 42 has a first end and a second end. The second film 41 is a surface including the surface of the second element electrode 12b of the second semiconductor element 101B (the surface of the second element electrode 12b and the surface of the second element body 11 on the first film 20 side). And a part of the surface of the wiring substrate 301 on the second semiconductor element 101B side from the side of the second element electrode 12b.

第２の配線４２の第１端は、第２の素子電極１２ｂに接しており、第２の配線４２の第２端は、第１の配線２２の第２端が接した第１の配線層の一部３２Ａとは異なる第１の配線層３２の他の一部３２Ｂに接している。尚、図１０に示した半導体装置１００では、２個の半導体素子１０１Ａ，１０１Ｂを積層したスタック構造をしているが、半導体素子の数について特に制限はなく、３個またはそれ以上の半導体素子が積層されていてもよい。   The first end of the second wiring 42 is in contact with the second element electrode 12 b, and the second end of the second wiring 42 is in contact with the second end of the first wiring 22. Is in contact with another portion 32B of the first wiring layer 32 different from the portion 32A of the first wiring layer 32. The semiconductor device 100 shown in FIG. 10 has a stack structure in which two semiconductor elements 101A and 101B are stacked. However, the number of semiconductor elements is not particularly limited, and three or more semiconductor elements are included. It may be laminated.

図１１に示すように、第１のフィルム２０の第２の配線層２５が形成された面の反対面に第３の配線層３６を形成し、第１のフィルムの平面２０ａに、第３の配線層３６を構成する配線の一端が配置されるようにすれば、この配線の一端上に第２の半導体素子１０１Ｂをフィリップチップ実装することもできる。上記配線の他端は、例えば、第１のフィルム２０内に設けられたビア２６を介して第１の配線層の一部３２Ｂに電気接続することができる。   As shown in FIG. 11, a third wiring layer 36 is formed on the surface opposite to the surface on which the second wiring layer 25 of the first film 20 is formed, and a third wiring layer 36 is formed on the plane 20a of the first film. If one end of the wiring constituting the wiring layer 36 is arranged, the second semiconductor element 101B can be Philip chip mounted on one end of the wiring. The other end of the wiring can be electrically connected to a part 32B of the first wiring layer through a via 26 provided in the first film 20, for example.

尚、第１のフィルム２０内にビア２６設けずに、図１１Ｂに示すように、第１のフィルム２０と第３の配線層３６とからなる積層体の端部を折り曲げて、第３の配線層３６を構成する配線と第１の配線層の一部３２Ｂとを電気接続してもよい。   In addition, without providing the vias 26 in the first film 20, as shown in FIG. 11B, the end of the laminate composed of the first film 20 and the third wiring layer 36 is bent to form the third wiring. The wiring constituting the layer 36 and the part 32B of the first wiring layer may be electrically connected.

図１〜図１１Ｂを用いて説明した本実施形態の半導体装置は、いずれも、第１の半導体素子が、接合材を介して配線基板に接合されているが、例えば、第１のフィルムによって第１の半導体素子が所定の位置に固定されれば、第１の半導体素子が配線基板に接合されていなくてもよい。   In each of the semiconductor devices according to the present embodiment described with reference to FIGS. 1 to 11B, the first semiconductor element is bonded to the wiring board via the bonding material. For example, the first film is formed by the first film. If one semiconductor element is fixed at a predetermined position, the first semiconductor element may not be bonded to the wiring board.

（実施形態２）
次に、図１２〜図１６を参照しながら、本実施形態２の半導体装置２００の一例について説明する。 (Embodiment 2)
Next, an example of the semiconductor device 200 according to the second embodiment will be described with reference to FIGS.

図１２に示すように、本実施形態の半導体装置２００では、絶縁性基板３０の第１面側に凹部３５が形成されており、その凹部３５内に第１の半導体素子１０１Ａが配置されている。この点が、実施形態１の半導体装置と異なる。他の点は、実施形態１の半導体装置と同様であるので説明を省略する。   As shown in FIG. 12, in the semiconductor device 200 of this embodiment, a recess 35 is formed on the first surface side of the insulating substrate 30, and the first semiconductor element 101 </ b> A is disposed in the recess 35. . This point is different from the semiconductor device of the first embodiment. Since other points are the same as those of the semiconductor device of the first embodiment, description thereof is omitted.

本実施形態の半導体装置２００では、第１の半導体素子１０１Ａが凹部３５内に配置されているので、半導体装置２００の外形について凹凸を減らすことがでる。また、半導体装置２００の薄型化も可能となる。   In the semiconductor device 200 of the present embodiment, since the first semiconductor element 101A is disposed in the recess 35, the unevenness of the outer shape of the semiconductor device 200 can be reduced. In addition, the semiconductor device 200 can be thinned.

図１２に示すように、第１の半導体素子１０１Ａの第１の素子本体部１０の第１面１０ａと絶縁性基板３０の第１の配線層３２が形成された面３０ａとが、実質的に同一面内にあると好ましい。半導体装置２００の外形について凹凸をさらに減らすことができるからである。図１２に示した半導体装置２００を用いれば、例えば、薄型化が求められるモバイル機器等の設計におけるレイアウトの複雑化を低減できる。   As shown in FIG. 12, the first surface 10a of the first element body 10 of the first semiconductor element 101A and the surface 30a of the insulating substrate 30 on which the first wiring layer 32 is formed are substantially It is preferable that they are in the same plane. This is because the unevenness of the outer shape of the semiconductor device 200 can be further reduced. If the semiconductor device 200 shown in FIG. 12 is used, for example, the complexity of the layout in the design of a mobile device or the like that is required to be thin can be reduced.

また、図１２に示した半導体装置２００では、第１のフィルム２０の第２の配線層２５が形成された面の反対面のほぼ全面が平面２０ａとなっている。そのため、第１のフィルム２０の上記平面２０ａ上に電子部品を配置し易い。   Further, in the semiconductor device 200 shown in FIG. 12, the almost entire surface opposite to the surface on which the second wiring layer 25 of the first film 20 is formed is a flat surface 20a. Therefore, it is easy to arrange electronic components on the plane 20 a of the first film 20.

図１３に示すように、第１の素子本体部の第１面１０ａのうちの、第１の素子電極１２ａ間に、第１のフィルム２０を密着させると、第１の素子電極１２ａ間の絶縁耐圧を高めることができる。   As shown in FIG. 13, when the first film 20 is brought into close contact between the first element electrodes 12a of the first surface 10a of the first element body portion, the insulation between the first element electrodes 12a is achieved. The breakdown voltage can be increased.

図１３に示した半導体装置２００では、凹部３５と第１の半導体素子１０１Ａとの間に隙間が存在するが、図１４に示すように、凹部３５の形状と第１の半導体素子の第１の素子本体部１０の形状とをほぼ等しくして、凹部３５と第１の半導体素子との間に隙間を無くしてもよい。凹部３５の形状と第１の素子本体部１０の形状とがほぼ等しいと、第１の素子電極１２ａと第２の配線層２５とを位置合わせがし易い。また、絶縁性基板３０と第１の素子本体部１０の側面とが接していると、第１の半導体素子の放熱性が高まる。   In the semiconductor device 200 shown in FIG. 13, there is a gap between the recess 35 and the first semiconductor element 101A. However, as shown in FIG. 14, the shape of the recess 35 and the first semiconductor element The shape of the element body 10 may be made substantially the same so that there is no gap between the recess 35 and the first semiconductor element. If the shape of the recess 35 and the shape of the first element body 10 are substantially equal, the first element electrode 12a and the second wiring layer 25 can be easily aligned. Moreover, if the insulating substrate 30 and the side surface of the first element body 10 are in contact with each other, the heat dissipation of the first semiconductor element is enhanced.

また、図１５に示すように、第１のフィルム２０の第２の配線層２５が形成された面の反対面のほぼ全面が平面２０ａであり、平面２０ａの面積は、第１の半導体素子１０１Ａの第１の素子本体部１０の第１面１０ａの面積よりも大きくてもよい。この場合、第１のフィルム２０の上記平面２０ａ上に、例えば、第１の半導体素子１０１Ａよりも平面視したときの面積が大きい他の半導体素子を配置すること、または、複数の半導体素子を配置することが可能となる。   Further, as shown in FIG. 15, almost the entire surface opposite to the surface on which the second wiring layer 25 of the first film 20 is formed is a flat surface 20a, and the area of the flat surface 20a is the first semiconductor element 101A. The area of the first surface 10a of the first element body 10 may be larger. In this case, for example, another semiconductor element having a larger area when viewed in plan than the first semiconductor element 101A is arranged on the plane 20a of the first film 20, or a plurality of semiconductor elements are arranged. It becomes possible to do.

図１６に示すように、第２の配線層２５が絶縁性基板３０の第１の配線層３２が形成された面３０ａと略平行となるように配置されていると、配線長を短くすることができるので、高速応答に有利となる。   As shown in FIG. 16, when the second wiring layer 25 is disposed so as to be substantially parallel to the surface 30a of the insulating substrate 30 on which the first wiring layer 32 is formed, the wiring length is shortened. This is advantageous for high-speed response.

本実施形態の半導体装置２００においても、実施形態１の半導体装置と同様に、２つ以上の半導体素子を含むスタック構造をしていてもよい。本実施形態の半導体装置では、第１の半導体素子１０１Ａが凹部３５内に配置されているので、スタック構造としても、実施形態１の半導体装置よりも、半導体装置の高さをより低くすることができ薄型化できる。   Also in the semiconductor device 200 of the present embodiment, similarly to the semiconductor device of the first embodiment, it may have a stack structure including two or more semiconductor elements. In the semiconductor device of this embodiment, since the first semiconductor element 101A is disposed in the recess 35, the height of the semiconductor device can be made lower than that of the semiconductor device of Embodiment 1 even in the stack structure. Can be made thinner.

図１６に示すように、本実施形態の半導体装置２００では、凹部３５の底面上に金属層３７を配置し、金属層３７の上に第１の半導体素子１０１Ａを配置してもよい。第１の半導体素子１０１Ａを金属層３７の上に配置すると、金属層３７は放熱板として機能するので、第１の半導体素子１０１Ａの放熱性が高まる。   As shown in FIG. 16, in the semiconductor device 200 of this embodiment, the metal layer 37 may be disposed on the bottom surface of the recess 35, and the first semiconductor element 101 </ b> A may be disposed on the metal layer 37. When the first semiconductor element 101A is disposed on the metal layer 37, the metal layer 37 functions as a heat dissipation plate, so that the heat dissipation of the first semiconductor element 101A is enhanced.

実施形態１および実施形態２では、第１の半導体素子１０１Ａの第１の素子電極１２ａの表面を含む面の全面が第１のフィルム２０によって覆われているが、第１の半導体素子１０１Ａの第１の素子電極１２ａの表面を含む面の一部が、第１のフィルム２０によって覆われていてもよい。また、図１０に示した例では、第２の半導体素子１０１Ｂの第２の素子電極１２ｂの表面を含む面の全面が第２のフィルム４１によって覆われているが、第２の半導体素子１０１Ｂの第２の素子電極１２ｂの表面を含む面の一部が、第２のフィルム４１によって覆われていてもよい。   In the first embodiment and the second embodiment, the entire surface including the surface of the first element electrode 12a of the first semiconductor element 101A is covered with the first film 20, but the first semiconductor element 101A includes the first semiconductor element 101A. A part of the surface including the surface of one element electrode 12 a may be covered with the first film 20. In the example shown in FIG. 10, the entire surface including the surface of the second element electrode 12b of the second semiconductor element 101B is covered with the second film 41. A part of the surface including the surface of the second element electrode 12 b may be covered with the second film 41.

実施形態１および実施形態２では、第１の半導体素子１０１Ａがベアチップである場合について説明したが、半導体素子はベアチップに限定されない。第1の半導体素子１０１Ａは、例えば、チップ・サイズ・パッケージ（ＣＳＰ）構造をしていてもよい。   In the first and second embodiments, the case where the first semiconductor element 101A is a bare chip has been described. However, the semiconductor element is not limited to a bare chip. For example, the first semiconductor element 101A may have a chip size package (CSP) structure.

また、第１の半導体素子１０１Ａは、典型的には、メモリＩＣチップや、ロジックＩＣチップ、またはシステムＬＳＩチップであるが、発光ダイオード（ＬＥＤ）チップであってもよい。第１の半導体素子１０１ＡとしてＬＥＤチップを用い、第１のフィルム２０が、ＬＥＤが発光する光に対して実質的に透明であると、発光デバイス（半導体装置）を実現できる。   The first semiconductor element 101A is typically a memory IC chip, a logic IC chip, or a system LSI chip, but may be a light emitting diode (LED) chip. When an LED chip is used as the first semiconductor element 101A and the first film 20 is substantially transparent to light emitted from the LED, a light emitting device (semiconductor device) can be realized.

第１の半導体素子１０１ＡとしてＬＥＤチップを用いる場合に、第１のフィルム２０内に蛍光体が分散されていると、ＬＥＤチップからの出射光と蛍光体から発する光との両方の光を利用した発光デバイスを実現できる。   When an LED chip is used as the first semiconductor element 101A, if the phosphor is dispersed in the first film 20, both light emitted from the LED chip and light emitted from the phosphor are used. A light emitting device can be realized.

実施形態１〜２の半導体装置が白色発光デバイスである場合、第１の半導体素子１０１Ａとして、青色光を出射する青色ＬＥＤチップを用い、第１のフィルム２０に蛍光体を分散させればよい。蛍光体としては、青色光を黄色光に変換する蛍光体を用いればよい。このようにすれば、青色光および黄色光によって白色の光が得られる。この場合、ＬＥＤチップとしては、例えば、窒化ガリウム（ＧａＮ）系材料からなるＬＥＤチップを、蛍光体としては、（Ｙ・Ｓｍ）3（Ａｌ・Ｇａ）5Ｏ12：Ｃｅ、（Ｙ0.39Ｇｄ0.57Ｃｅ0.03Ｓｍ0.01）3Ａｌ5Ｏ12等が好適に用いられる。 When the semiconductor device of Embodiments 1 and 2 is a white light emitting device, a blue LED chip that emits blue light may be used as the first semiconductor element 101 </ b> A, and a phosphor may be dispersed in the first film 20. As the phosphor, a phosphor that converts blue light into yellow light may be used. In this way, white light can be obtained by blue light and yellow light. In this case, for example, an LED chip made of a gallium nitride (GaN) -based material is used as the LED chip, and (Y · Sm) 3 (Al · Ga) 5 O 12 : Ce (Y 0.39 Gd 0.57 is used as the phosphor. Ce 0.03 Sm 0.01 ) 3 Al 5 O 12 or the like is preferably used.

第１の半導体素子１０１Ａとしては、青色ＬＥＤチップの他に、紫外光を発する紫外ＬＥＤチップも用いることができる。この場合、紫外ＬＥＤチップから発生した光により励起して、赤（Ｒ）、緑（Ｇ）および青（Ｂ）の光を発する蛍光体を第１のフィルム２０に分散させれば、白色発光デバイスを実現できる。このように、ＬＥＤチップの種類と蛍光体の種類とを適宜選択することによって、所望の色を発する発光デバイスを実現できる。   As the first semiconductor element 101A, an ultraviolet LED chip that emits ultraviolet light can be used in addition to a blue LED chip. In this case, a white light emitting device is obtained by dispersing phosphors that emit red (R), green (G), and blue (B) light in the first film 20 by being excited by light generated from the ultraviolet LED chip. Can be realized. In this manner, a light emitting device that emits a desired color can be realized by appropriately selecting the type of LED chip and the type of phosphor.

また、配線基板は、ガラス板と透明性の高い導電性材料（例えば、インジウム−スズ系酸化物）を含む配線層とを備えたガラス基板であってもよい。配線基板として、透光性を有するガラス板を用い、第１のフィルムとして、入射光に対して実質的に透明なフィルムを用いれば、第１の半導体素子１０１Ａ側から入射する光を配線基板側に透過させることが可能な、透光性を有する半導体装置を提供できる。また、この場合に、第１の半導体素子１０１ＡとしてＬＥＤチップ等を用いれば、ＬＥＤチップから生じる光を配線基板側に透過させることができる。透光性を有する半導体装置は、例えば、液晶ディスプレイ等の部品として有用であり、バックライトから生じる光を透過させることができる。   Further, the wiring substrate may be a glass substrate including a glass plate and a wiring layer containing a highly transparent conductive material (for example, indium-tin oxide). If a glass plate having translucency is used as the wiring substrate and a film substantially transparent to incident light is used as the first film, the light incident from the first semiconductor element 101A side is transmitted to the wiring substrate side. Thus, a light-transmitting semiconductor device can be provided. In this case, if an LED chip or the like is used as the first semiconductor element 101A, light generated from the LED chip can be transmitted to the wiring board side. A semiconductor device having a light-transmitting property is useful as a component such as a liquid crystal display, and can transmit light generated from a backlight.

以下、本発明の半導体装置の一例についてさらに具体的に説明するが、本発明の半導体装置は、下記の実施例に限定されない。   Hereinafter, an example of the semiconductor device of the present invention will be described more specifically, but the semiconductor device of the present invention is not limited to the following examples.

まず、厚さ０．４ｍｍのガラス−アルミナセラミックからなる配線基板（京セラ株式会社製）を用意した。この配線基板の配線層は、銅層と銅層の上に施された無電解ニッケルめっき層および無電解金めっき層からなる。   First, a wiring board (made by Kyocera Corporation) made of glass-alumina ceramic having a thickness of 0.4 mm was prepared. The wiring layer of this wiring board includes a copper layer and an electroless nickel plating layer and an electroless gold plating layer applied on the copper layer.

次に、外形４ｍｍ角、厚さ０．１５ｍｍの半導体素子を用意した。この半導体素子を配線基板にダイボンドフィルム（新日鐵化学株式会社製、ＮＥＸ−１３０）を介して接合した。次に、太さ３０μｍの金ワイヤを用いて、半導体素子の素子電極上にバンプを形成した。   Next, a semiconductor element having an outer shape of 4 mm square and a thickness of 0.15 mm was prepared. This semiconductor element was joined to the wiring substrate via a die bond film (Nex-130, manufactured by Nippon Steel Chemical Co., Ltd.). Next, bumps were formed on the element electrodes of the semiconductor element using a gold wire with a thickness of 30 μm.

一方、厚さ２５μｍのポリイミドフィルムと、ポリイミドフィルムに接合された厚さ９μｍの銅箔とからなる積層フィルム（新日鐵化学株式会社製）を用意し、上記銅箔を所定の形状にパターニングした。次いで、パターニングされた銅箔に、ニッケルめっきおよび金めっきを施して、ポリイミドフィルムの一方の主面に配線層が形成されたシート状物を形成した。   On the other hand, a laminated film (made by Nippon Steel Chemical Co., Ltd.) composed of a polyimide film having a thickness of 25 μm and a copper foil having a thickness of 9 μm bonded to the polyimide film was prepared, and the copper foil was patterned into a predetermined shape. . Next, the patterned copper foil was subjected to nickel plating and gold plating to form a sheet-like material in which a wiring layer was formed on one main surface of the polyimide film.

次に、半導体素子の素子電極と、配線層を構成する複数の配線のうちの所定の配線の第１端とが重なるように、シート状物を半導体素子上に配置した。次いで、超音波を印加しながら平板ツールでシート状物を加熱および加圧して、半導体素子の素子電極と配線とを電気接続した。   Next, the sheet-like object was arranged on the semiconductor element so that the element electrode of the semiconductor element and a first end of a predetermined wiring among the plurality of wirings constituting the wiring layer overlapped. Next, the sheet-like material was heated and pressurized with a flat plate tool while applying ultrasonic waves to electrically connect the element electrodes of the semiconductor elements and the wiring.

次に、上記所定の配線の第２端を、配線基板の配線層の所定の位置に重ね合わせた後、配線の第２端と配線層とが接した部分に、超音波ツールを押し当てて、加圧しながら超音波を印加し、上記所定の配線の第２端と、配線基板の配線層とを電気接続した。以上のようにして、半導体装置を得た。   Next, after the second end of the predetermined wiring is overlapped with a predetermined position of the wiring layer of the wiring board, an ultrasonic tool is pressed against a portion where the second end of the wiring is in contact with the wiring layer. Then, an ultrasonic wave was applied while applying pressure, and the second end of the predetermined wiring was electrically connected to the wiring layer of the wiring board. A semiconductor device was obtained as described above.

次に、半導体装置を、温度３０℃、湿度６０％の恒温恒湿槽内に１９２時間放置し、その後、ピーク温度を２６０℃とするリフロー試験を行った。リフロー試験後、素子電極とシート状物の配線との接続部分、配線基板の配線層とシート状物の配線との接続部分に、異常は認められなかった。また、リフロー試験後に、半導体装置を、−６５℃の雰囲気中に３０分間放置し、続いて１５０℃の雰囲気中に３０分間放置するという１サイクルの操作を、１０００回行った後、接続抵抗を測定した。接続抵抗の変動は、１０％以内であり、良好な電気接続が保たれていることが確認できた。   Next, the semiconductor device was left in a constant temperature and humidity chamber having a temperature of 30 ° C. and a humidity of 60% for 192 hours, and then a reflow test was performed with a peak temperature of 260 ° C. After the reflow test, no abnormality was observed in the connection portion between the element electrode and the sheet-like wiring and the connection portion between the wiring layer of the wiring board and the sheet-like wiring. In addition, after the reflow test, the semiconductor device was left in an atmosphere at −65 ° C. for 30 minutes and then left in an atmosphere at 150 ° C. for 30 minutes. It was measured. The fluctuation of the connection resistance was within 10%, and it was confirmed that a good electrical connection was maintained.

配線基板として、深さ約０．１３ｍｍの凹部を有する厚さ０．４ｍｍの４層ガラスエポキシ基板（日立化成工業株式会社製、Ｅ−６７９Ｆ）を用意した。この配線基板の配線層は、厚さ１８μｍの銅層と銅層の上に施された無電解ニッケルめっき層および無電解金めっき層からなる。   As a wiring board, a 4-layer glass epoxy board (manufactured by Hitachi Chemical Co., Ltd., E-679F) having a thickness of about 0.13 mm and a recess having a depth of about 0.13 mm was prepared. The wiring layer of this wiring board is composed of a copper layer having a thickness of 18 μm and an electroless nickel plating layer and an electroless gold plating layer applied on the copper layer.

次に、外形４ｍｍ角、厚さ０．１ｍｍの半導体素子を用意した。この半導体素子の素子電極上に、太さ２５μｍの金ワイヤを用いてバンプを形成した。   Next, a semiconductor element having an outer diameter of 4 mm square and a thickness of 0.1 mm was prepared. Bumps were formed on the device electrodes of this semiconductor device using a gold wire with a thickness of 25 μm.

一方、厚さ５０μｍの液晶ポリマーフィルムと、液晶ポリマーフィルムに接合された厚さ１２μｍの銅箔とからなる積層フィルム（新日鐵化学株式会社製）を用意し、上記銅箔を所定の形状にパターニングした。次いで、パターニングされた銅箔に、ニッケルめっきおよび金めっきを施して、液晶ポリマーフィルムの一方の主面に配線層が形成されたシート状物を形成した。   On the other hand, a laminated film (manufactured by Nippon Steel Chemical Co., Ltd.) comprising a liquid crystal polymer film having a thickness of 50 μm and a copper foil having a thickness of 12 μm bonded to the liquid crystal polymer film is prepared, and the copper foil is formed into a predetermined shape. Patterned. Next, the patterned copper foil was subjected to nickel plating and gold plating to form a sheet-like material in which a wiring layer was formed on one main surface of the liquid crystal polymer film.

次に、半導体素子の素子電極と、配線層を構成する複数の配線のうちの所定の配線の第１端とが重なるように、シート状物を半導体素子上に配置した。次いで、超音波を印加しながら平板ツールでシート状物を加熱および加圧して、半導体素子の素子電極と配線とを電気的に接続した。   Next, the sheet-like object was arranged on the semiconductor element so that the element electrode of the semiconductor element and a first end of a predetermined wiring among the plurality of wirings constituting the wiring layer overlapped. Next, the sheet-like material was heated and pressurized with a flat tool while applying ultrasonic waves to electrically connect the element electrodes of the semiconductor elements and the wiring.

次に、配線基板の配線層上の所定の位置に、導電性接着剤（ナミックス株式会社製）を印刷した。その後、配線基板の凹部内に半導体素子を収容し、シート状物の所定の配線の第２端を、配線基板の配線層の所定の位置に重ね合わせた。次いで、上記所定の配線の第２端と配線層とが接した部分を、加圧しながら加熱して導電性接着剤を硬化させ、上記所定の配線の第２端と、配線基板の配線層とを電気接続した。以上のようにして、半導体装置を得た。   Next, a conductive adhesive (manufactured by NAMICS Co., Ltd.) was printed at a predetermined position on the wiring layer of the wiring board. Thereafter, the semiconductor element was accommodated in the concave portion of the wiring board, and the second end of the predetermined wiring of the sheet-like material was superposed on a predetermined position of the wiring layer of the wiring board. Next, the portion where the second end of the predetermined wiring is in contact with the wiring layer is heated while being pressurized to cure the conductive adhesive, and the second end of the predetermined wiring, the wiring layer of the wiring substrate, The electrical connection. A semiconductor device was obtained as described above.

次に、半導体装置を、温度３０℃、湿度６０％の恒温恒湿槽内に１９２時間放置し、その後、ピーク温度を２６０℃とするリフロー試験を行った。リフロー試験後、素子電極とシート状物の配線との接続部分、配線基板の配線層とシート状物の配線との接続部分に、異常は認められなかった。また、リフロー試験後に、半導体装置を、−６５℃の雰囲気中に３０分間放置し、続いて１５０℃の雰囲気中に３０分間放置するという１サイクルの操作を、１０００回行った後、接続抵抗を測定した。接続抵抗の変動は、１０％以内であり、良好な電気接続が保たれていることが確認できた。   Next, the semiconductor device was left in a constant temperature and humidity chamber having a temperature of 30 ° C. and a humidity of 60% for 192 hours, and then a reflow test was performed with a peak temperature of 260 ° C. After the reflow test, no abnormality was observed in the connection portion between the element electrode and the sheet-like wiring and the connection portion between the wiring layer of the wiring board and the sheet-like wiring. In addition, after the reflow test, the semiconductor device was left in an atmosphere at −65 ° C. for 30 minutes and then left in an atmosphere at 150 ° C. for 30 minutes. It was measured. The fluctuation of the connection resistance was within 10%, and it was confirmed that a good electrical connection was maintained.

本発明によれば、ＷＢ法、ＦＣ法またはＴＡＢ法を採用した半導体装置が抱えていた不都合が軽減された半導体装置を提供できる。例えば、生産性が良い半導体装置を提供できるので、本発明の半導体装置およびその製造方法は有用である。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device with which the trouble which the semiconductor device which employ | adopted WB method, FC method, or TAB method had was reduced can be provided. For example, since a semiconductor device with good productivity can be provided, the semiconductor device and the manufacturing method thereof of the present invention are useful.

本発明の実施形態１の半導体装置の一例を模式的に示す断面図Sectional drawing which shows typically an example of the semiconductor device of Embodiment 1 of this invention 図１Ａの半導体装置を模式的に示す上面図FIG. 1A is a top view schematically showing the semiconductor device of FIG. 1A. 図１Ａの半導体装置を模式的に示す斜視図FIG. 1A is a perspective view schematically showing the semiconductor device of FIG. 1A. 本発明の実施形態１の半導体装置の他の例を模式的に示す断面図Sectional drawing which shows the other example of the semiconductor device of Embodiment 1 of this invention typically 実施形態１の半導体装置の製造方法の一例を説明する工程断面図Process sectional drawing explaining an example of the manufacturing method of the semiconductor device of Embodiment 1 実施形態１の半導体装置の製造方法の一例を説明する工程断面図Process sectional drawing explaining an example of the manufacturing method of the semiconductor device of Embodiment 1 実施形態１の半導体装置の製造方法の一例を説明する工程断面図Process sectional drawing explaining an example of the manufacturing method of the semiconductor device of Embodiment 1 実施形態１の半導体装置の製造方法の一例を説明する工程断面図Process sectional drawing explaining an example of the manufacturing method of the semiconductor device of Embodiment 1 実施形態１の半導体装置の製造方法の一例を説明する工程断面図Process sectional drawing explaining an example of the manufacturing method of the semiconductor device of Embodiment 1 実施形態１の半導体装置の製造方法の一例を説明する工程断面図Process sectional drawing explaining an example of the manufacturing method of the semiconductor device of Embodiment 1 本発明の実施形態１の半導体装置の他の例を模式的に示す断面図Sectional drawing which shows the other example of the semiconductor device of Embodiment 1 of this invention typically 本発明の実施形態１の半導体装置の他の例を模式的に示す断面図Sectional drawing which shows the other example of the semiconductor device of Embodiment 1 of this invention typically 本発明の実施形態１の半導体装置の他の例を模式的に示す断面図Sectional drawing which shows the other example of the semiconductor device of Embodiment 1 of this invention typically 本発明の実施形態１の半導体装置の他の例を模式的に示す断面図Sectional drawing which shows the other example of the semiconductor device of Embodiment 1 of this invention typically 本発明の実施形態１の半導体装置の他の例を模式的に示す断面図Sectional drawing which shows the other example of the semiconductor device of Embodiment 1 of this invention typically 本発明の実施形態１の半導体装置の他の例の一部の拡大図Partial enlarged view of another example of the semiconductor device of Embodiment 1 of the present invention 本発明の実施形態２の半導体装置の一例を模式的に示す断面図Sectional drawing which shows typically an example of the semiconductor device of Embodiment 2 of this invention 本発明の実施形態２の半導体装置の他の例を模式的に示す断面図Sectional drawing which shows the other example of the semiconductor device of Embodiment 2 of this invention typically 本発明の実施形態２の半導体装置の他の例を模式的に示す断面図Sectional drawing which shows the other example of the semiconductor device of Embodiment 2 of this invention typically 本発明の実施形態２の半導体装置の他の例を模式的に示す断面図Sectional drawing which shows the other example of the semiconductor device of Embodiment 2 of this invention typically 本発明の実施形態２の半導体装置の他の例を模式的に示す断面図Sectional drawing which shows the other example of the semiconductor device of Embodiment 2 of this invention typically 半導体チップとリードフレームとがボンディングワイヤにより接続された状態を説明する上面図Top view for explaining a state in which a semiconductor chip and a lead frame are connected by a bonding wire 図１７ＡのＡ−Ａ断面図AA sectional view of FIG. 17A ＷＢ法を採用した従来の半導体装置の一例を示す断面図Sectional drawing which shows an example of the conventional semiconductor device which employ | adopted WB method ＦＣ法を採用した従来の半導体装置の一例を示す断面図Sectional drawing which shows an example of the conventional semiconductor device which employ | adopted FC method ＴＡＢ法を採用した従来の半導体装置の一例を示した断面図Sectional drawing which showed an example of the conventional semiconductor device which employ | adopted TAB method 図２０に示した半導体装置を実装基板に実装した状態を説明する断面図Sectional drawing explaining the state which mounted the semiconductor device shown in FIG. 20 on the mounting board | substrate. ＴＡＢ法を用いた従来の半導体装置の他の例を示す断面図Sectional drawing which shows the other example of the conventional semiconductor device using TAB method 図２２に示した従来の半導体装置を実装基板に実装した状態を説明する断面図Sectional drawing explaining the state which mounted the conventional semiconductor device shown in FIG. 22 on the mounting board | substrate.

符号の説明Explanation of symbols

１０１Ａ 第１の半導体素子
１０１Ｂ 第２の半導体素子
１０ 第１の素子本体部
１１ 第２の素子本体部
１０ａ 第１面
１０ｂ 第２面
１２ａ 第１の素子電極
１２ｂ 第２の素子電極
２０ 第１のフィルム
２１ 金属層
２２ 第１の配線
２４ 電磁波遮蔽層
３０１ 配線基板
３０ 絶縁性基板
３２ 第１の配線層
２５ 第２の配線層
３６ 第３の配線層
３５ 凹部
３７ 金属層
１００、２００ 半導体装置
５０' シート状物 101A 1st semiconductor element 101B 2nd semiconductor element 10 1st element main-body part 11 2nd element main-body part 10a 1st surface 10b 2nd surface 12a 1st element electrode 12b 2nd element electrode 20 1st Film 21 Metal layer 22 First wiring 24 Electromagnetic wave shielding layer 301 Wiring substrate 30 Insulating substrate 32 First wiring layer 25 Second wiring layer 36 Third wiring layer 35 Recess 37 Metal layer 100, 200 Semiconductor device 50 ′ Sheet

Claims (30)

第１面と前記第１面に対向する第２面とを有する第１の素子本体部と、前記第１面に設けられた第１の素子電極とを含む第１の半導体素子と、
絶縁性基板と前記絶縁性基板の一方の主面に形成された第１の配線層とを含み、前記一方の主面が前記第１の素子本体部の前記第２面と向かい合うように配置された配線基板と、
前記第１の半導体素子の前記第１の素子電極の表面を含む面の少なくとも一部と、前記配線基板の前記第１の半導体素子側の面の少なくとも一部とを覆う第１のフィルムと、
前記第１のフィルムの前記配線基板側の面に形成され、第１端と第２端とを有する第１の配線を含む第２の配線層と、を備え、
前記第１の配線の前記第１端と前記第１の素子電極とが接合され、前記第１の配線の前記第２端と前記第１の配線層の一部とが接合された半導体装置。 A first semiconductor element including a first element body having a first surface and a second surface facing the first surface; and a first element electrode provided on the first surface;
An insulating substrate and a first wiring layer formed on one main surface of the insulating substrate, wherein the one main surface is disposed to face the second surface of the first element body. Wiring board,
A first film that covers at least a part of a surface of the first semiconductor element including a surface of the first element electrode and at least a part of a surface of the wiring board on the first semiconductor element side;
A second wiring layer formed on a surface of the first film on the wiring board side and including a first wiring having a first end and a second end;
A semiconductor device in which the first end of the first wiring and the first element electrode are joined, and the second end of the first wiring and a part of the first wiring layer are joined. 前記第１のフィルムは、実質的に透明である請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first film is substantially transparent. 前記第１の半導体素子と前記絶縁性基板とが、接合材を介して接合された請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first semiconductor element and the insulating substrate are bonded via a bonding material. 前記第１のフィルムの前記配線基板側の面の反対面に形成された電磁波遮蔽層をさらに含む請求項１に記載の半導体装置。   The semiconductor device according to claim 1, further comprising an electromagnetic wave shielding layer formed on a surface opposite to the surface on the wiring board side of the first film. 前記第１のフィルムと前記第２の配線層とからなる積層体の前記第２の配線層側の面の一部が、前記第１の半導体素子の前記第１の素子電極の表面を含む面に、直接または間接的に密着した請求項１に記載の半導体装置。   A part of a surface on the second wiring layer side of the laminate composed of the first film and the second wiring layer includes a surface of the first element electrode of the first semiconductor element. The semiconductor device according to claim 1, wherein the semiconductor device is in direct or indirect contact. 前記積層体の前記第２の配線層側の面の前記一部とは異なる他の一部と、第１の素子本体部の側面とが、直接または間接的に密着した請求項５に記載の半導体装置。   The other part different from the part of the surface on the second wiring layer side of the laminated body and the side surface of the first element body part are in direct or indirect contact. Semiconductor device. 前記第１のフィルムと前記第２の配線層とからなる積層体の前記配線基板側の面が、前記第１の半導体素子および前記配線基板に直接または間接的に接合されて、前記第１の半導体素子が、前記積層体と前記配線基板によって囲われる密閉空間内に配置された請求項１に記載の半導体装置。   The surface on the wiring board side of the laminate composed of the first film and the second wiring layer is directly or indirectly bonded to the first semiconductor element and the wiring board, so that the first The semiconductor device according to claim 1, wherein the semiconductor element is disposed in a sealed space surrounded by the stacked body and the wiring board. 前記第１の配線の前記第１端と前記第１の素子電極とが接し、前記第１の配線の前記第２端と前記第１の配線層の前記一部とが接している請求項１に記載の半導体装置。   The first end of the first wiring and the first element electrode are in contact with each other, and the second end of the first wiring and the part of the first wiring layer are in contact with each other. A semiconductor device according to 1. 前記第１のフィルムの前記配線基板側の面の反対面に形成された第３の配線層をさらに含む請求項１に記載の半導体装置。   The semiconductor device according to claim 1, further comprising a third wiring layer formed on a surface opposite to the surface on the wiring board side of the first film. 第２の素子電極を有する第２の半導体素子をさらに含み、
前記第２の素子電極と前記第３の配線層とが接合された請求項９に記載の半導体装置。 A second semiconductor element having a second element electrode;
The semiconductor device according to claim 9, wherein the second element electrode and the third wiring layer are joined. 前記第１のフィルムの前記配線基板側の面の反対面は、前記第１の素子本体部の前記第１面と同面積以上の平面を含む請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a surface opposite to the surface on the wiring board side of the first film includes a plane having the same area or more as the first surface of the first element main body. 第２の素子本体部と前記第２の素子本体部に設けられた第２の素子電極とを有する第２の半導体素子をさらに含み、
前記第２の素子本体部の前記第２の素子電極の表面を含む面の反対面と、前記第１のフィルムの前記平面とが向かい合うように、前記第１のフィルム上に前記第２の半導体素子が配置された請求項１１に記載の半導体装置。 A second semiconductor element having a second element body and a second element electrode provided on the second element body;
The second semiconductor on the first film such that a surface opposite to the surface including the surface of the second element electrode of the second element body and the plane of the first film face each other. The semiconductor device according to claim 11, wherein an element is disposed. 前記第２の半導体素子の前記第２の素子電極の表面を含む面の少なくとも一部と、前記配線基板の前記第２の半導体素子側の面の少なくとも一部とを覆う第２のフィルムと、
前記第２フィルムの前記配線基板側の面に形成され、第１端と第２端とを有する第２の配線を含む第４の配線層とをさらに備え、
前記第２の配線の前記第１端と前記第２の素子電極とが接合され、
前記第１の配線の前記第２端が接合された前記第１の配線層の前記一部とは異なる前記第１の配線層の他の一部と、前記第２の配線の前記第２端とが接合された請求項１２に記載の半導体装置。 A second film covering at least a part of a surface of the second semiconductor element including a surface of the second element electrode and at least a part of a surface of the wiring board on the second semiconductor element side;
A fourth wiring layer formed on a surface of the second film on the wiring board side and including a second wiring having a first end and a second end;
The first end of the second wiring and the second element electrode are joined,
Another part of the first wiring layer different from the part of the first wiring layer to which the second end of the first wiring is joined, and the second end of the second wiring And the semiconductor device according to claim 12. 前記絶縁性基板の前記第１の配線層が形成された面側に凹部が形成されており、
前記凹部内に、前記第１の半導体素子が配置された請求項１に記載の半導体装置。 A recess is formed on the surface of the insulating substrate on which the first wiring layer is formed,
The semiconductor device according to claim 1, wherein the first semiconductor element is disposed in the recess. 前記絶縁性基板の前記第１の配線層が形成された面と、前記第１の素子本体部の前記第１面とが、実質的に同一面内にある請求項１４に記載の半導体装置。   The semiconductor device according to claim 14, wherein a surface of the insulating substrate on which the first wiring layer is formed and the first surface of the first element main body are substantially in the same plane. 前記第１のフィルムの前記配線基板側の面の反対面は、実質的に平面である請求項１４に記載の半導体装置。   The semiconductor device according to claim 14, wherein a surface opposite to the surface on the wiring board side of the first film is a substantially flat surface. 第２の素子本体部と前記第２の素子本体部に設けられた第２の素子電極とを有する第２の半導体素子をさらに含み、
前記第２の半導体素子の前記第２の素子電極の表面を含む面の反対面と、前記第１のフィルムの前記平面とが向かい合うように、前記第２の半導体素子が前記第１のフィルム上に配置された請求項１６に記載の半導体装置。 A second semiconductor element having a second element body and a second element electrode provided on the second element body;
The second semiconductor element is on the first film such that the opposite surface of the second semiconductor element including the surface of the second element electrode faces the plane of the first film. The semiconductor device according to claim 16, which is disposed in 前記第２の半導体素子の前記第２の素子電極の表面を含む面の少なくとも一部と、前記配線基板の前記第２の半導体素子側の面の少なくとも一部とを覆う第２のフィルムと、
前記第２フィルムの前記配線基板側の面に形成され、第１端と第２端とを有する第２の配線を含む第４の配線層と、をさらに備え、
前記第２の配線の前記第１端と前記第２の素子電極とが接合され、
前記第１の配線の前記第２端が接合された前記第１の配線層の前記一部とは異なる前記第１の配線層の他の一部と、前記第２の配線の前記第２端とが接合された請求項１７に記載の半導体装置。 A second film covering at least a part of a surface of the second semiconductor element including a surface of the second element electrode and at least a part of a surface of the wiring board on the second semiconductor element side;
A fourth wiring layer formed on a surface of the second film on the wiring board side and including a second wiring having a first end and a second end;
The first end of the second wiring and the second element electrode are joined,
Another part of the first wiring layer different from the part of the first wiring layer to which the second end of the first wiring is joined, and the second end of the second wiring The semiconductor device according to claim 17, which is bonded to each other. 前記配線基板は、プリント基板またはガラス基板である請求項１〜１８のいずれかの項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the wiring board is a printed board or a glass substrate. 第１の素子本体部と前記第１の素子本体部に設けられた第１の素子電極とを有する第１の半導体素子と、絶縁性基板と前記絶縁性基板の一方の主面に形成された第１の配線層とを含む配線基板とを、前記第１の素子本体部の前記第１の素子電極が設けられた面の反対面と、前記絶縁性基板の前記一方の主面とが向かい合うように重ね、フィルムと前記フィルムの一方の主面に形成され、第１端と第２端とを有する第１の配線を含む第２の配線層とを含むシート状物の、前記第１の配線の前記第１端と前記第１の素子電極とを接合し、前記第１の配線の前記第２端と前記第１の配線層の一部とを接合して、前記フィルムで、前記第１の半導体素子の前記第１の素子電極の表面を含む面の少なくとも一部と、前記配線基板の前記第１の半導体素子側の面の少なくとも一部とを覆う実装工程を含む半導体装置の製造方法。   A first semiconductor element having a first element body and a first element electrode provided on the first element body, and formed on one main surface of the insulating substrate and the insulating substrate. A wiring board including a first wiring layer faces a surface opposite to the surface of the first element body portion on which the first element electrode is provided, and the one main surface of the insulating substrate. The first and second sheets of the sheet including the film and the second wiring layer including the first wiring having the first end and the second end formed on one main surface of the film. Bonding the first end of the wiring and the first element electrode, bonding the second end of the first wiring and a part of the first wiring layer, the film, At least a portion of a surface of the first semiconductor element including the surface of the first element electrode, and the first semiconductor element of the wiring substrate. The method of manufacturing a semiconductor device including a mounting step of covering at least a portion of the surface. 前記実装工程において、前記第１の半導体素子と前記配線基板とを接合する請求項２０に記載の半導体装置の製造方法。   21. The method of manufacturing a semiconductor device according to claim 20, wherein, in the mounting step, the first semiconductor element and the wiring board are joined. 前記実装工程において、前記第１の半導体素子と前記配線基板とを接合した後、前記第１の配線の前記第１端と前記第１の素子電極とを接合し、前記第１の配線の前記第２端と前記第１の配線層の一部とを接合する請求項２１に記載の半導体装置の製造方法。   In the mounting step, after the first semiconductor element and the wiring substrate are bonded, the first end of the first wiring and the first element electrode are bonded, and the first wiring of the first wiring is connected. The method for manufacturing a semiconductor device according to claim 21, wherein a second end is joined to a part of the first wiring layer. 前記実装工程において、前記第１の配線の前記第１端と前記第１の素子電極とを接合した後、前記第１の半導体素子と前記配線基板とを接合する請求項２１に記載の半導体装置の製造方法。   The semiconductor device according to claim 21, wherein, in the mounting step, the first semiconductor element and the wiring substrate are joined after joining the first end of the first wiring and the first element electrode. Manufacturing method. 前記実装工程において、超音波振動を用いて、前記第１の配線の前記第１端と前記第１の素子電極とを接合し、前記第１の配線の前記第２端と前記第１の配線層の一部とを接合する請求項２０に記載の半導体装置の製造方法。   In the mounting step, the first end of the first wiring and the first element electrode are joined using ultrasonic vibration, and the second end of the first wiring and the first wiring 21. The method of manufacturing a semiconductor device according to claim 20, wherein a part of the layer is bonded. 前記実装工程において、前記シート状物の前記第２の配線層側の面の一部を、前記第１の半導体素子の前記第１の素子電極の表面を含む面に、直接または間接的に密着させる請求項２０に記載の半導体装置の製造方法。   In the mounting step, a part of the surface of the sheet-like material on the second wiring layer side is directly or indirectly adhered to a surface including the surface of the first element electrode of the first semiconductor element. The method for manufacturing a semiconductor device according to claim 20. 前記フィルムは樹脂を含み、
前記実装工程において、前記フィルムを加熱して熱収縮させることにより、前記シート状物を、前記第１の半導体素子の前記第１の素子電極の表面を含む面に密着させる請求項２５に記載の半導体装置の製造方法。 The film includes a resin;
The said mounting process WHEREIN: The said sheet-like thing is closely_contact | adhered to the surface including the surface of the said 1st element electrode of a said 1st semiconductor element by heating the said film and carrying out heat shrink. A method for manufacturing a semiconductor device. 前記実装工程において、前記フィルムを加熱し、加圧して、前記フィルムの前記第２の配線層側の面の反対面を平面とする請求項２０に記載の半導体装置の製造方法。   21. The method of manufacturing a semiconductor device according to claim 20, wherein in the mounting step, the film is heated and pressed to make a surface opposite to the surface on the second wiring layer side of the film flat. 前記フィルムは未硬化状態の熱硬化性樹脂を含み、
前記実装工程において、前記シート状物を所定の形状に加工した後、加熱により前記熱硬化性樹脂を硬化して、前記シート状物を前記第１の半導体素子の前記第１の素子電極の表面を含む面の少なくとも一部と、前記配線基板の前記第１の半導体素子側の面の少なくとも一部とを覆うことができる形状に加工した後、前記第１の配線の前記第１端と前記第１の素子電極とを接合し、前記第１の配線の前記第２端と前記第１の配線層の一部とを接合する請求項２０に記載の半導体装置の製造方法。 The film includes an uncured thermosetting resin,
In the mounting step, after the sheet-like material is processed into a predetermined shape, the thermosetting resin is cured by heating, and the sheet-like material is formed on the surface of the first element electrode of the first semiconductor element. And processing to a shape that can cover at least a part of the surface including the first semiconductor element side surface of the wiring substrate, and the first end of the first wiring 21. The method of manufacturing a semiconductor device according to claim 20, wherein a first element electrode is bonded, and the second end of the first wiring and a part of the first wiring layer are bonded. 前記絶縁性基板の前記第１の配線層が形成された面側に凹部が形成されており、
前記実装工程において、前記第１の半導体素子を、前記凹部内に配置する請求項２０に記載の半導体装置の製造方法。 A recess is formed on the surface of the insulating substrate on which the first wiring layer is formed,
21. The method of manufacturing a semiconductor device according to claim 20, wherein in the mounting step, the first semiconductor element is disposed in the recess. 前記実装工程の後に、前記フィルムの前記第２の配線層が形成された面の反対面上に、第２の素子電極を有する第２の半導体素子を配置する工程をさらに含み、
前記工程において、前記第２の半導体素子の前記第２の素子電極の表面を含む面の反対面と前記フィルムの前記平面とが向かい合うように、第２の半導体素子を前記フィルム上に配置する請求項２７に記載の半導体装置の製造方法。 After the mounting step, the method further includes a step of disposing a second semiconductor element having a second element electrode on the surface opposite to the surface on which the second wiring layer of the film is formed,
2nd semiconductor element is arrange | positioned on the said film so that the surface opposite to the surface containing the surface of the said 2nd element electrode of the said 2nd semiconductor element and the said plane of the said film may face in the said process. Item 28. A method for manufacturing a semiconductor device according to Item 27.
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