JP2010258284A - Mounting method and mounting structure of electronic component - Google Patents

Mounting method and mounting structure of electronic component Download PDF

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JP2010258284A
JP2010258284A JP2009108006A JP2009108006A JP2010258284A JP 2010258284 A JP2010258284 A JP 2010258284A JP 2009108006 A JP2009108006 A JP 2009108006A JP 2009108006 A JP2009108006 A JP 2009108006A JP 2010258284 A JP2010258284 A JP 2010258284A
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sheet
circuit board
electronic component
electronic circuit
wiring
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JP5386220B2 (en
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Tsukasa Shiraishi
司 白石
Yoshitake Hayashi
林　　祥剛
Yukihiro Ishimaru
幸宏 石丸
Kazuo Otani
和夫 大谷
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Panasonic Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting structure improving a connecting efficiency of an electronic component and reducing a damage when the electronic component is mounted. <P>SOLUTION: Predetermined wiring patterns 4a, 4b are formed with a conductive ink 3 on one surface of a sheet 2 consisting principally of porous polyamide-imides and polyetherimides and the like. Electrodes 8a, 8b for the electronic component 6 are aligned with wirings 7a, 7b for an electronic circuit board 5 on the other surface of the sheet so as to reside just below predetermined parts of wirings 4a, 4b. The thickness becomes thin by impregnating the sheet 2 with N-methyl-2-pyrolidone and the like, and connecting parts of wirings 4a, 4b, electrodes 8a, 8b, and wirings 7a, 7b are brought into contact with each other. The sheet 2 is fixed so as to keep their electric connection. According to the method, even if connecting parts are increased, connecting parts are connected in batch, and it is unnecessary to apply pressure, ultrasonic sound wave or heat for connection. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は電子部品の実装方法および実装構造体に関し、特に電極を多数有する電子部品、たとえば半導体デバイスなどの電極を電子回路基板などの配線の接続部位と接続するのに適した方法と実装構造体に関する。   The present invention relates to an electronic component mounting method and mounting structure, and more particularly to a method and mounting structure suitable for connecting an electronic component having a large number of electrodes, for example, an electrode of a semiconductor device or the like, to a connection portion of a wiring such as an electronic circuit board. About.

チップ状の半導体デバイスのような多数の接続部位を有する電子部品を電子回路基板に実装する方法として、これまで、ワイヤボンディング法（たとえば特許文献１参照）やフリップチップ法（たとえば特許文献２参照）が広く用いられている。   As a method for mounting an electronic component having a large number of connection parts such as a chip-like semiconductor device on an electronic circuit board, a wire bonding method (for example, see Patent Document 1) or a flip chip method (for example, see Patent Document 2). Is widely used.

ワイヤボンディング法によれば、電子回路基板のダイパッドに半導体デバイスをダイボンドした後、その電極パッドと電子回路基板におけるランドなどの接続部位とを、ＡｕまたはＡｌなどからなるボンディングワイヤで接続する。また、フリップチップ法によれば、電子回路基板の配線の接続部位に電極パッドをパンプで接続し、半導体デバイスを電子回路基板に保持させ、さらに、それらの間の間隙部分を封止樹脂で封止している。   According to the wire bonding method, after a semiconductor device is die-bonded to a die pad of an electronic circuit board, the electrode pad and a connection site such as a land on the electronic circuit board are connected by a bonding wire made of Au or Al. Also, according to the flip chip method, electrode pads are connected by bumps to the wiring connection portions of the electronic circuit board, the semiconductor device is held on the electronic circuit board, and the gap between them is sealed with a sealing resin. It has stopped.

特開平７−１４７２９６号公報JP-A-7-147296 特開２０００−１１４３１０号公報JP 2000-114310 A

ワイヤボンディング法では、半導体デバイスの電極パッドと電子回路基板のランドなどとを、対応するもの同士一組ずつボンディングワイヤで接続する。そのため、接続箇所が多くなればなるほど、接続のための設備が高価となり、また接続に時間を要し、組立の生産性の向上に制約があった。   In the wire bonding method, electrode pads of a semiconductor device and lands of an electronic circuit board are connected to each other by a bonding wire. For this reason, as the number of connection points increases, the equipment for connection becomes expensive, and it takes time to connect, and there is a restriction in improving the productivity of assembly.

これに対して、フリップチップ法によれば、チップ状の半導体デバイスの電極パッド上に形成したバンプを、電子回路基板の対応するランドなどにそれぞれ当接させ、バンプに加圧力、超音波、および熱のうちの少なくとも一つを加えて、それを変形させて接続している。この方法によれば、ワイヤボンディング法と異なり、一つずつ接続するのではなく、一括して行うので、接続作業の手間が少なく、またその所要時間も短くて済む。しかしながら、その接続数が多くなり、バンプの数が多くなると、それに応じて加圧力を増大させたり、超音波エネルギーまたは熱エネルギーを多く加えたりしなければならない。それによって、半導体デバイスや電子回路基板にダメージを与えてしまうという新たな問題が発生する。   On the other hand, according to the flip chip method, bumps formed on the electrode pads of the chip-like semiconductor device are brought into contact with the corresponding lands of the electronic circuit board, respectively, and pressure, ultrasonic waves, and At least one of the heat is applied and it is deformed and connected. According to this method, unlike the wire bonding method, since the connection is not performed one by one, but is performed in a lump, the labor of the connection work is reduced and the time required for the connection is shortened. However, when the number of connections increases and the number of bumps increases, the applied pressure must be increased accordingly, or a greater amount of ultrasonic energy or thermal energy must be applied. This causes a new problem of damaging semiconductor devices and electronic circuit boards.

本発明は、このような従来の電子部品の実装方法が抱えていた不都合を解消しまたはそれを大幅に軽減することができる実装方法、およびこの方法を適用するのに適した構造の実装構造体を提供することを目的とする。   The present invention eliminates the disadvantages of such conventional electronic component mounting methods or can greatly reduce them, and a mounting structure having a structure suitable for applying this method The purpose is to provide.

本発明の電子部品の実装方法は、
複数の電極を有する電子部品を電子回路基板の所定位置に固定する工程、
高分子材料からなる多孔質な構造のシートの表面に、導電性インクにより、前記電子部品の各電極とこれに対応する前記電子回路基板の各接続部位とを接続するための配線を形成する工程、
前記配線を形成したシートをその裏面側が、前記配線が接続すべき前記電極と前記接続部位とにまたがるように、前記電子回路基板上に位置合わせする工程、
前記シートの所定部位に溶剤を含浸させてその厚みを減じて、前記配線を前記電極および前記接続部位に電気的に接続する工程、および
前記配線と前記電極および前記接続部位との電気的な接続が維持されるように前記シートを前記電子回路基板に固定する工程
を少なくとも具備する。 The electronic component mounting method of the present invention includes:
Fixing an electronic component having a plurality of electrodes at a predetermined position on an electronic circuit board;
A step of forming wiring for connecting each electrode of the electronic component and each corresponding connection portion of the electronic circuit board with a conductive ink on the surface of a porous structure sheet made of a polymer material ,
A step of aligning the sheet on which the wiring is formed on the electronic circuit board such that the back side thereof extends over the electrode and the connection site to which the wiring is to be connected;
A step of impregnating a predetermined portion of the sheet with a solvent to reduce the thickness thereof and electrically connecting the wiring to the electrode and the connection portion; and an electrical connection between the wiring and the electrode and the connection portion. At least a step of fixing the sheet to the electronic circuit board so as to be maintained.

前記導電性インクは、導電性ナノ粒子を主な材料として含むインクであることが好ましい。   The conductive ink is preferably an ink containing conductive nanoparticles as a main material.

また、前記電子部品の電極が突起形状をしていることが好ましい。   Moreover, it is preferable that the electrode of the electronic component has a protruding shape.

前記電子部品は受動部品、能動部品、コネクタ部品、および電子回路基板のうちの少なくとも１種であることが好ましい。   The electronic component is preferably at least one of a passive component, an active component, a connector component, and an electronic circuit board.

前記第３の工程において、前記シートにその溶剤を含浸させて空孔体積を減少させることによって厚みを減じることが好ましい。   In the third step, it is preferable to reduce the thickness by impregnating the sheet with the solvent to reduce the pore volume.

前記シートはポリアミドイミド、またはポリエーテルイミドを主成分として含み、また、前記溶剤はＮ−メチル−２−ピロリドン、Ｎ，Ｎ−ジメチルアセトアミド、ジメチルスルホキシド、γ−ブチロラクトン、シクロヘキサノンまたはスルホランであることが好ましい。   The sheet contains polyamideimide or polyetherimide as a main component, and the solvent is N-methyl-2-pyrrolidone, N, N-dimethylacetamide, dimethyl sulfoxide, γ-butyrolactone, cyclohexanone or sulfolane. preferable.

さらに、本発明の実装構造体は、複数の電極を有する電子部品、前記電極それぞれと接続すべき複数の接続部位を有し、前記電子部品が取り付けられた電子回路基板、ならびに、前記電子部品の電極と前記電子回路基板の接続部位とをそれぞれ接続する、複数の配線を有するシートを備える。   Furthermore, the mounting structure of the present invention includes an electronic component having a plurality of electrodes, a plurality of connection portions to be connected to each of the electrodes, an electronic circuit board on which the electronic component is attached, and the electronic component A sheet having a plurality of wirings for connecting the electrode and the connection portion of the electronic circuit board is provided.

前記シートは少なくとも一部分が多孔質体であることが好ましい。   It is preferable that at least a part of the sheet is a porous body.

前記配線が導電性インクで形成されていることが好ましい。   The wiring is preferably formed of a conductive ink.

前記電子部品が、前記電極を有する面とは反対側の面で、前記電子回路基板に取り付けられていることが好ましい。   It is preferable that the electronic component is attached to the electronic circuit board on a surface opposite to the surface having the electrodes.

本発明によれば、ワイヤボンディング法やフリップチップ法にあった実装の不都合さを解消しまたはいちじるしく軽減する電子部品の実装方法、ならびに信頼性の高い十増構造体を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the mounting method of the electronic component which eliminates the inconvenience of the mounting which met the wire bonding method or the flip-chip method, or remarkably reduces, and a highly reliable ten increase structure can be provided.

本発明にかかる電子部品の実装方法の、実施の形態１を説明するための工程図である。It is process drawing for demonstrating Embodiment 1 of the mounting method of the electronic component concerning this invention. 実施の形態１により作製した実装構造体の平面図である。4 is a plan view of a mounting structure manufactured according to Embodiment 1. FIG. 本発明にかかる電子部品の実装方法の、実施の形態２を説明するための工程図である。It is process drawing for demonstrating Embodiment 2 of the mounting method of the electronic component concerning this invention. 実施の形態２により作製した実装構造体の平面図である。10 is a plan view of a mounting structure manufactured according to Embodiment 2. FIG. 本発明の方法による実装構造体の接続状態の調査方法を説明するための図である。It is a figure for demonstrating the investigation method of the connection state of the mounting structure by the method of this invention. 本発明の方法による実装構造体の接続状態の調査結果を示す図である。It is a figure which shows the investigation result of the connection state of the mounting structure by the method of this invention.

（実施の形態１）
図１（ａ）に示すように、インクジェット印刷装置の吐出ノズル１から、多孔質な構造を有するシート２の一方の主面へ向けて導電性インク３を吐出させ、所定の回路パターンの接続用配線４ａ、４ｂを描画する。 (Embodiment 1)
As shown in FIG. 1A, a conductive ink 3 is discharged from a discharge nozzle 1 of an ink jet printing apparatus toward one main surface of a sheet 2 having a porous structure to connect a predetermined circuit pattern. The wirings 4a and 4b are drawn.

シート２には、ポリアミドイミド、またはポリエーテルイミドなどの高分子材料を主成分とし、その厚み方向に連通する微小な孔を多数有するシートを使用する。そして、微小な孔の平均孔径が１〜３μｍの範囲内であって、空孔率が７０〜７５％の範囲内であることが好ましい。   As the sheet 2, a sheet having a polymer material such as polyamide imide or polyether imide as a main component and a large number of minute holes communicating in the thickness direction is used. And it is preferable that the average hole diameter of minute holes is in the range of 1 to 3 μm and the porosity is in the range of 70 to 75%.

これは、たとえば、次の方法で作製することができる。まず、ポリアミドイミドまたはポリエーテルイミドなどの高分子材料を主成分とし、水溶性高分子材料たとえばポリビニルピロリドンを添加した溶液を、膜作製用基盤上にシート状に流延し、凝固させる。凝固後、基盤から剥離し、得られたシートに水を供給して、水溶性高分子材料を抽出することによって、厚み方向に連通する微小な孔を形成する。その平均孔径、シートの空孔率は、水溶性高分子材料の種類や添加比率によって所望の値とすることができる。このようなシート２として、たとえば宇部興産株式会社製のポリイミドフィルム（「ユーピレックス」（登録商標））を用いることができる。   This can be produced, for example, by the following method. First, a solution containing a polymer material such as polyamide imide or polyether imide as a main component and a water-soluble polymer material such as polyvinyl pyrrolidone is cast into a sheet form on a substrate for film production and solidified. After the solidification, the fine sheet is peeled from the substrate, and water is supplied to the obtained sheet to extract the water-soluble polymer material, thereby forming minute holes communicating in the thickness direction. The average pore diameter and sheet porosity can be set to desired values depending on the type of water-soluble polymer material and the addition ratio. As such a sheet 2, for example, a polyimide film ("Upilex" (registered trademark)) manufactured by Ube Industries, Ltd. can be used.

導電性インク３には、平均粒径が３０ｎｍ以下の微細な導電性ナノ粒子を主な成分として含み、分散媒中に分散させたものを使用することができる。導電性の粒子としては、銀、銅、および金などの金属粒子を使用することができる。また分散媒としては、テトラデカン、またはトルエンなどを用いることができる。   As the conductive ink 3, one containing fine conductive nanoparticles having an average particle size of 30 nm or less as a main component and dispersed in a dispersion medium can be used. As the conductive particles, metal particles such as silver, copper, and gold can be used. As the dispersion medium, tetradecane, toluene or the like can be used.

ノズル１から吐出された導電性インク３のナノ粒子は、シート２の表面に衝突し、微小孔を通して内部へ浸透する。これによって、シート２内に接続用配線４ａ、４ｂが形成される。また、シート２の微小孔の多くが、厚み方向に連通して形成されていることから、配線４ａ、４ｂのシート２表面での広がりや表面と平行な方向への浸透が抑制される。このため、配線を精度よく描くことができ、幅１０μｍ程度の微細な配線も容易に形成することができる。配線４ａ、４ｂの幅は、導電性インク３の吐出条件やその材料条件、およびシート２における孔の形成条件によって、制御することができる。   The nanoparticles of the conductive ink 3 discharged from the nozzle 1 collide with the surface of the sheet 2 and penetrate into the inside through the micropores. As a result, connection wirings 4 a and 4 b are formed in the sheet 2. Moreover, since many of the micropores of the sheet 2 are formed so as to communicate with each other in the thickness direction, the spreading of the wirings 4a and 4b on the surface of the sheet 2 and the penetration in the direction parallel to the surface are suppressed. Therefore, the wiring can be drawn with high accuracy, and a fine wiring having a width of about 10 μm can be easily formed. The widths of the wirings 4 a and 4 b can be controlled by the discharge conditions of the conductive ink 3, the material conditions thereof, and the hole formation conditions in the sheet 2.

配線４ａ、４ｂを描画した後、シート２を約２２０℃に加熱し、導電性インク３に含まれている分散媒成分を揮発させて、シート２の配線の形成を完了する。   After the wirings 4a and 4b are drawn, the sheet 2 is heated to about 220 ° C., and the dispersion medium component contained in the conductive ink 3 is volatilized to complete the formation of the wiring of the sheet 2.

一方、図１（ｂ）に示すように、電子回路基板５とそれに搭載するチップ状の半導体デバイス６を準備し、半導体デバイス６を電子回路基板５にダイボンドする。電子回路基板５は一方の主面上に配線７ａ、７ｂを備え、半導体デバイス６はダイボンド面とは反対側の面上に電極パッド８ａ、８ｂを備える。   On the other hand, as shown in FIG. 1B, an electronic circuit board 5 and a chip-like semiconductor device 6 mounted thereon are prepared, and the semiconductor device 6 is die-bonded to the electronic circuit board 5. The electronic circuit board 5 includes wirings 7a and 7b on one main surface, and the semiconductor device 6 includes electrode pads 8a and 8b on the surface opposite to the die bonding surface.

電子回路基板５には、フェノール樹脂、エポキシ樹脂、ポリイミド樹脂、またはフッ素樹脂などの樹脂やセラミックスを基板材料とするプリント配線基板を使用することができる。   As the electronic circuit board 5, a printed wiring board using a resin such as a phenol resin, an epoxy resin, a polyimide resin, or a fluororesin, or a ceramic as a substrate material can be used.

次に、図１（ｃ）および（ｄ）に示すように、接続用配線４ａがシート２を介して電子回路基板５の配線７ａのランドと半導体デバイス６の電極パッド８ａとにまたがり、接続用配線４ｂが配線７ｂのランドと電極パッド８ｂとにまたがるように、シート２を電子回路基板５上に位置合わせする。   Next, as shown in FIGS. 1C and 1D, the connection wiring 4 a spans the land of the wiring 7 a of the electronic circuit board 5 and the electrode pad 8 a of the semiconductor device 6 through the sheet 2. The sheet 2 is aligned on the electronic circuit board 5 so that the wiring 4b extends over the land of the wiring 7b and the electrode pad 8b.

すなわち、接続用配線４ａ、４ｂの一端の所定部位がシート２を介して半導体デバイス６の電極パッド８ａ、８ｂと、またその他端の所定部位が電子回路基板５の配線７ａ、７ｂのランドと重なるようにそれぞれ位置合わせする。こうして、半導体デバイス６を覆うようシート２を電子回路基板５に押し当て配置する。   That is, a predetermined part at one end of the connection wirings 4 a and 4 b overlaps with the electrode pads 8 a and 8 b of the semiconductor device 6 via the sheet 2, and a predetermined part at the other end overlaps the land of the wirings 7 a and 7 b of the electronic circuit board 5. Align each as follows. Thus, the sheet 2 is pressed against the electronic circuit board 5 so as to cover the semiconductor device 6.

位置合わせを終えた後に、図１（ｅ）に示すように、シート２に溶剤を含浸させる。これにより、シート２の空孔がいちじるしく縮小しまたはその多くが実質的に消滅して、厚みは当初の数分の１、たとえば５分の１程度に薄くなる。これによって、接続用配線４ａ、４ｂが、電極パッド８ａ、８ｂおよび配線７ａ、７ｂのランドとそれぞれ接触し、それらの間の電気的な接続がなされる。このとき、シート２が所望の厚さになるよう溶剤の量を制御して含浸させる。工業的に実施する際には、含浸量および含浸処理時間をあらかじめ実験的に求めておくことによって、再現性よく希望する厚さとすることができる。溶剤を含浸させるには、溶剤を噴霧ノズルから霧状にしてシート面に均一に吹き付ける方法、またはシートを溶剤に接触させる方法などを使用することができる。そして、含浸操作を停止し処理を所定の厚みで停止させるには、噴霧方法の場合には噴霧を停止し、接触方法の場合には溶剤から取り出して、加熱するなどしてシートに含まれている溶剤を揮発させればよい。   After the alignment, as shown in FIG. 1 (e), the sheet 2 is impregnated with a solvent. As a result, the pores of the sheet 2 are remarkably reduced or many of them are substantially eliminated, and the thickness is reduced to one-fifth of the original, for example, about one-fifth. As a result, the connection wirings 4a and 4b come into contact with the electrode pads 8a and 8b and the lands of the wirings 7a and 7b, respectively, and electrical connection therebetween is made. At this time, the amount of the solvent is controlled so that the sheet 2 has a desired thickness. In industrial implementation, the desired thickness can be obtained with good reproducibility by experimentally determining the amount of impregnation and the impregnation treatment time in advance. In order to impregnate the solvent, a method of spraying the solvent from the spray nozzle in a mist state and spraying it uniformly on the sheet surface, or a method of bringing the sheet into contact with the solvent can be used. In order to stop the impregnation operation and stop the treatment at a predetermined thickness, in the case of the spraying method, the spraying is stopped, and in the case of the contact method, it is removed from the solvent and heated, etc. What is necessary is just to volatilize the solvent which exists.

シート２がポリエーテルイミドなどを主成分とする場合には、その厚みを薄くするための溶剤として、Ｎ−メチル−２−ピロリドン、Ｎ，Ｎ−ジメチルアセトアミド、ジメチルスルホキシド、γ−ブチロラクトン、シクロヘキサノンまたはスルホランなどの溶剤やそれらを主成分とする溶剤を使用する。   When the sheet 2 is mainly composed of polyetherimide or the like, N-methyl-2-pyrrolidone, N, N-dimethylacetamide, dimethyl sulfoxide, γ-butyrolactone, cyclohexanone or a solvent for reducing the thickness A solvent such as sulfolane or a solvent containing them as a main component is used.

電気的に接続した後に、その接続状態を維持するために、シート２を電子回路基板５に固定する。その方法としては、まずシート２を電子回路基板５に固定した状態で減圧雰囲気中に所定時間置いて脱泡処理をする。それから、図１（ｆ）に示すように、ディスペンサ方式の吐出ノズル９を使用して、シート２の周縁に沿って液状の未硬化の絶縁性樹脂１０を塗布する。絶縁性樹脂１０は、毛細管現象によってシート２と電子回路基板５との間の微小な隙間を通って、半導体デバイス６とシート２および電子回路基板５との間の空間内に注入され充填される。なお、脱泡処理のための雰囲気圧力、処理時間については、この方法を適用する実装構造体に応じて適宜実験的に設定すればよい。   After the electrical connection, the sheet 2 is fixed to the electronic circuit board 5 in order to maintain the connection state. As the method, first, the sheet 2 is fixed to the electronic circuit board 5 and placed in a reduced pressure atmosphere for a predetermined time to perform a defoaming process. Then, as shown in FIG. 1 (f), a liquid uncured insulating resin 10 is applied along the periphery of the sheet 2 using a dispenser-type discharge nozzle 9. The insulating resin 10 is injected and filled into the space between the semiconductor device 6 and the sheet 2 and the electronic circuit board 5 through a minute gap between the sheet 2 and the electronic circuit board 5 by a capillary phenomenon. . In addition, what is necessary is just to set experimental pressure suitably according to the mounting structure to which this method is applied about the atmospheric pressure and process time for a defoaming process.

図１（ｇ）に示すように、電子回路基板５および半導体デバイス６とシート２との間の必要部分に絶縁性樹脂１０を注入し終えた後に、絶縁性樹脂１０を硬化させる。これにより、シート２は電子回路基板５に接着し固定され、配線４ａ、４ｂと、配線７ａ、７ｂおよび電極パッド８ａ、８ｂとの電気的な接続状態が安定したものとなる。絶縁性樹脂１０にはたとえばエポキシ樹脂を主成分とする熱硬化性樹脂を使用し、注入完了後に約１５０℃に加熱して硬化させる。なお、シート２を固定する方法としては、これ以外の方法を用いてもなんら構わない。   As shown in FIG. 1G, after the insulating resin 10 is injected into the necessary portions between the electronic circuit board 5 and the semiconductor device 6 and the sheet 2, the insulating resin 10 is cured. Thereby, the sheet 2 is bonded and fixed to the electronic circuit board 5, and the electrical connection state between the wirings 4a and 4b and the wirings 7a and 7b and the electrode pads 8a and 8b becomes stable. For the insulating resin 10, for example, a thermosetting resin mainly composed of an epoxy resin is used, and is cured by heating to about 150 ° C. after the completion of the injection. In addition, as a method for fixing the sheet 2, any method other than this may be used.

図２に上述の方法で作製した実装構造体の平面構造の一例を示す。   FIG. 2 shows an example of a planar structure of the mounting structure manufactured by the above method.

多孔質の構造のシート２において、その微小孔の平均径は１〜３μｍの範囲内にあることが好ましい。平均孔径が１μｍより小さくなると、シート２に対する導電性インク３の浸透力が十分でなく、配線を微細に描画することが困難となる。それが３μｍより大きくなると、孔によって形成された空孔中を伝わって、シート面に沿う横方向へ導電性インク３が広がりやすくなり、微細なパターンの配線をすることがむずかしくなる。さらに、シート２の原料となるポリイミドアミドやポリエーテルイミドの作製工程上の理由からも、孔径を過度に大きくすることは実際的でない。   In the sheet 2 having a porous structure, the average diameter of the micropores is preferably in the range of 1 to 3 μm. When the average pore diameter is smaller than 1 μm, the penetration force of the conductive ink 3 with respect to the sheet 2 is not sufficient, and it becomes difficult to draw the wiring finely. If it becomes larger than 3 μm, the conductive ink 3 tends to spread in the lateral direction along the sheet surface through the holes formed by the holes, and it becomes difficult to form a fine pattern of wiring. Furthermore, it is not practical to make the pore diameter excessively large for reasons of the production process of the polyimide amide or polyether imide that is the raw material of the sheet 2.

さらに、微小孔によるシート２における空孔率については、７０〜７５％の範囲内であることが望ましい。それが７０％より低くなると、シート２に対する導電性インク３の浸透力が不足してくる。また、空孔率が７５％よりも高くなると、シート２の機械的強度が低下し、上述した実装工程中で破損するなどして、生産効率を低下させてしまう。   Furthermore, it is desirable that the porosity of the sheet 2 due to the minute holes is in the range of 70 to 75%. If it is lower than 70%, the penetrating power of the conductive ink 3 to the sheet 2 becomes insufficient. Further, when the porosity is higher than 75%, the mechanical strength of the sheet 2 is lowered, and the production efficiency is lowered due to damage in the mounting process described above.

また、シート２の当初の厚みについては、導電性インク３の平均的な浸透深さと、溶剤の含浸処理後の厚みとの関係で決めることができる。たとえば、導電性インク３の平均的な浸透深さが３〜５μｍであり、溶剤含浸処理後のシート２の厚みが４μｍ程度であるときには、当初の厚さが２０μｍのものを使用することができる。これにより、良好で安定した接続構造を実現することができる。もちろん、これよりも薄いシートを使用することも可能ではあるが、薄くなるとその強度が低下し、取扱いがむずかしくなる。実装すべき電子部品の寸法や接続箇所数などに応じて、実験的にその厚さを選定するのが望ましい。   Further, the initial thickness of the sheet 2 can be determined by the relationship between the average penetration depth of the conductive ink 3 and the thickness after the impregnation treatment with the solvent. For example, when the average penetration depth of the conductive ink 3 is 3 to 5 μm and the thickness of the sheet 2 after the solvent impregnation treatment is about 4 μm, an initial thickness of 20 μm can be used. . Thereby, a good and stable connection structure can be realized. Of course, it is possible to use a sheet thinner than this, but when the sheet becomes thinner, its strength decreases and handling becomes difficult. It is desirable to experimentally select the thickness according to the dimensions of the electronic component to be mounted, the number of connection points, and the like.

上述の実装方法によれば、接続箇所数が増大しても、接続を一括して行うことができ、ワイヤボンディング法に比べて一つずつ接続を行わなくてもよいので、生産効率の点で非常に優れている。また、フリップチップ法のように、接続の際に大きな圧力を印加したり、大きな超音波エネルギーを与えたり、または熱を加えたりする必要がないので、半導体デバイスや電子回路基板にダメージが加わらないという特長を有する。   According to the mounting method described above, even if the number of connection points increases, it is possible to perform connection in a lump, and it is not necessary to perform connection one by one as compared with the wire bonding method. Very good. In addition, unlike the flip chip method, there is no need to apply a large pressure at the time of connection, to apply a large ultrasonic energy, or to apply heat, so that the semiconductor device and the electronic circuit board are not damaged. It has the feature.

なお、電極パッド数が１００個程度またはそれより多い場合に、工業的に実施するのに非常に効果的である。   In addition, when the number of electrode pads is about 100 or more, it is very effective for industrial implementation.

この例では、半導体デバイスの実装方法について述べたが、その他の能動部品や受動部品、コネクタ部品、または電子回路基板などの実装においても本発明の方法を適用することができるのは言うまでもないことである。
（実施の形態２） In this example, the semiconductor device mounting method has been described, but it goes without saying that the method of the present invention can also be applied to mounting other active components, passive components, connector components, or electronic circuit boards. is there.
(Embodiment 2)

この実施の形態２の方法は、実施の形態１の方法の特長を備え、さらに電気的な接続を確実なものとしたものである。そのもっとも異なるところは、電極パッド８ａ、８ｂ上に突起状のバンプ２１ａ、２１ｂを備えた半導体デバイス６を使用することにある。   The method according to the second embodiment has the features of the method according to the first embodiment, and further ensures electrical connection. The most different point is that the semiconductor device 6 having the protruding bumps 21a and 21b on the electrode pads 8a and 8b is used.

バンプ２１ａ、２１ｂは、ＡｕやＣｕ、その他金属を電極パッド８ａ、８ｂに電解メッキして形成したり、または、ボールボンディング法などの他のバンプ形成法を用いて形成したりすればよい。バンプ２１ａ、２１ｂは、後述するようにシート２を溶剤処理によって薄くした後の厚さよりも高い寸法となるよう形成する。   The bumps 21a and 21b may be formed by electroplating Au, Cu, or other metal on the electrode pads 8a and 8b, or may be formed by using another bump forming method such as a ball bonding method. As will be described later, the bumps 21a and 21b are formed to have a dimension higher than the thickness after the sheet 2 is thinned by solvent treatment.

他の構成要素や、シート２への導電性インクによる接続用配線４ａ、４ｂの形成、電子回路基板５上への半導体デバイス６のダイボンディングなどの方法は、実施の形態１と同様の要素を使用し、同様の手順で実施することができる。   Other components, the method of forming the connection wirings 4a and 4b with conductive ink on the sheet 2, and die bonding of the semiconductor device 6 on the electronic circuit board 5 are the same as those in the first embodiment. Can be used and implemented in a similar procedure.

図３（ａ）に示すように、電子回路基板５の所定の位置に半導体デバイス６をダイボンドした後、シート２を、配線４ａ、４ｂの所定部位がシート２を介して半導体デバイス６の電極パッド８ａ、８ｂおよび配線７ａ、７ｂのランドとそれぞれ重なるように位置合わせする。   As shown in FIG. 3A, after the semiconductor device 6 is die-bonded to a predetermined position of the electronic circuit board 5, the sheet 2 is connected to the electrode pads of the semiconductor device 6 with the predetermined portions of the wirings 4a and 4b interposed through the sheet 2. 8a and 8b and wirings 7a and 7b are aligned so as to overlap the lands.

位置合わせ後、図３（ｂ）に示すように、シート２を電子回路基板５に押し当てる。半導体デバイス６のバンプ２１ａ、２１ｂが、シート２の接続用配線４ａ、４ｂの所定部位を貫通してそれぞれが接触し、電気的に接続される。   After alignment, the sheet 2 is pressed against the electronic circuit board 5 as shown in FIG. The bumps 21a and 21b of the semiconductor device 6 penetrate through predetermined portions of the connection wirings 4a and 4b of the sheet 2 and are in contact with each other to be electrically connected.

それから、図３（ｃ）に示すようにシート２の所定部位に溶剤を所定量含浸させることによって、シート２の空孔をいちじるしく縮小させ、またはその多くを実質的に消滅させて、シート２の厚みを当初の数分の１、たとえば５分の１程度に薄くする。この処理によって、配線４ａ、４ｂと配線７ａ、７ｂとが接触し、電気的に接続される。   Then, as shown in FIG. 3 (c), a predetermined amount of solvent is impregnated into a predetermined portion of the sheet 2 to significantly reduce the pores of the sheet 2 or to substantially eliminate many of the holes. The thickness is reduced to one-fifth of the original, for example, about one-fifth. By this process, the wirings 4a and 4b and the wirings 7a and 7b come into contact with each other and are electrically connected.

含浸処理後、減圧雰囲気中に所定時間置いて脱泡処理をしてから、図３（ｄ）に示すように、ディスペンサ方式の吐出ノズル９を使用して、シート２の周縁に沿って液状の未硬化の絶縁性樹脂１０を塗布する。絶縁性樹脂１０は、毛細管現象によってシート２と電子回路基板５との間に存在する微小な隙間を通って、シート２下に形成された空間内に注入され充填される。なお、脱泡処理のための雰囲気圧力、処理時間については、この方法を適用する実装構造体に応じて適宜実験的に設定すればよい。   After the impregnation treatment, the defoaming treatment is performed for a predetermined time in a reduced-pressure atmosphere, and then, as shown in FIG. An uncured insulating resin 10 is applied. The insulating resin 10 is injected and filled into a space formed under the sheet 2 through a minute gap existing between the sheet 2 and the electronic circuit board 5 by capillary action. In addition, what is necessary is just to set experimental pressure suitably according to the mounting structure to which this method is applied about the atmospheric pressure and process time for a defoaming process.

図３（ｅ）に示すように、絶縁性樹脂１０を電子回路基板５および半導体デバイス６とシート２との間の必要部分に注入をし終えた後に、絶縁性樹脂１０を硬化させて、シート２を電子回路基板５に接着し固定する。絶縁性樹脂１０にはたとえばエポキシ樹脂を主成分とする熱硬化性樹脂を使用し、注入完了後に加熱して硬化させて、シート２を半導体デバイス６および電子回路基板５に固定し、配線４ａ、４ｂと電極パッド８ａ、８ｂおよび配線７ａ、７ｂとの電気的な接続状態を安定したものとする。シート２を固定する方法としては、これ以外の方法を用いてもなんら構わない。   As shown in FIG. 3 (e), after injecting the insulating resin 10 into the necessary portions between the electronic circuit board 5 and the semiconductor device 6 and the sheet 2, the insulating resin 10 is cured to obtain a sheet. 2 is bonded and fixed to the electronic circuit board 5. For the insulating resin 10, for example, a thermosetting resin mainly composed of an epoxy resin is used. After the injection is completed, the resin is heated and cured to fix the sheet 2 to the semiconductor device 6 and the electronic circuit board 5. It is assumed that the electrical connection state between 4b, the electrode pads 8a and 8b, and the wirings 7a and 7b is stable. As a method for fixing the sheet 2, any method other than this may be used.

図４に上述の方法で作製した構造体の一例の平面構造を示す。   FIG. 4 shows a planar structure of an example of a structure manufactured by the above method.

この方法によれば、バンプ２１ａ、２１ｂが、配線４ａ、４ｂの接続部位を貫通するために、バンプ２１ａ、２１ｂと配線４ａ、４ｂとがそれぞれ確実に接続される。さらに、バンプ２１ａ、２１ｂをシート２の厚さに比べて高い寸法とすることにより、それらの頂部がシート２から突き出た形態となり、配線４ａとバンプ２１ａとの間、配線４ｂとバンプ２１ｂとの間のいずれかで位置ずれがあって、接続されていなかったり、接続不良の状態であったりしても、その箇所を導電性インクで再描画することで容易に修正し接続をすることができる。すなわち、本実施の形態２は、実施の形態１の特長に加えて、それに比べてより確実な電気的な接続を行うことができ、さらにリペア・ワ−クが行えるという特長をあわせ持つ。   According to this method, since the bumps 21a and 21b penetrate through the connection portions of the wirings 4a and 4b, the bumps 21a and 21b and the wirings 4a and 4b are reliably connected to each other. Further, by setting the bumps 21a and 21b to a size higher than the thickness of the sheet 2, their tops protrude from the sheet 2, and the wiring 4b and the bump 21b are connected between the wiring 4a and the bump 21a. Even if there is a misalignment somewhere in between, it is not connected or it is in a poor connection state, it can be easily corrected and connected by redrawing the part with conductive ink . That is, in addition to the features of the first embodiment, the second embodiment has features that a more reliable electrical connection can be performed and that repair work can be performed.

（実施例１）
接続用の配線を形成するためのシートとして、平均孔径１μｍ、空孔率７５％の多孔質構造で、厚さ２０μｍのポリアミドイミドからなるシートを使用した。このシートの一方の面へ向けて、平均粒径３０ｎｍ以下の微細なＡｇ粒子を含む導電性インクをインクジェットノズルから吐出させ、シートに、幅４０μｍの配線パターンとなるよう描画した。この例では、ポリイミドシートとして、宇部興産株式会社製の「ユーピレックス」（登録商標）を、また導電性インクにはハリマ化成株式会社製のＮＰＳ−Ｊをそれぞれ使用した。描画後、２２０℃に加熱して分散媒を蒸発させて、シートにその表面からインク浸透深さまでの厚さの配線を形成した。 Example 1
As a sheet for forming a wiring for connection, a sheet made of polyamideimide having a porous structure with an average pore diameter of 1 μm and a porosity of 75% and a thickness of 20 μm was used. A conductive ink containing fine Ag particles having an average particle size of 30 nm or less was ejected from one side of the sheet from an inkjet nozzle, and the sheet was drawn to form a wiring pattern having a width of 40 μm. In this example, “UPILEX” (registered trademark) manufactured by Ube Industries, Ltd. was used as the polyimide sheet, and NPS-J manufactured by Harima Chemical Co., Ltd. was used as the conductive ink. After drawing, the dispersion medium was evaporated by heating to 220 ° C., and a wiring having a thickness from the surface to the ink penetration depth was formed on the sheet.

また、電子回路基板として、厚さ０．４ｍｍのガラス基材エポキシ基板上に厚さ１２μｍのＣｕ箔で幅４０μｍの配線を形成したプリント回路基板を使用し、ランド上に３〜５μｍの厚さにＡｕを無電解メッキした。ガラス基材エポキシ基板には、パナソニック電工株式会社製Ｒ−１７５０を使用した。   In addition, as an electronic circuit board, a printed circuit board in which a wiring having a width of 40 μm is formed on a glass substrate epoxy substrate having a thickness of 0.4 mm and a Cu foil having a thickness of 12 μm is used, and a thickness of 3 to 5 μm is formed on the land. Au was electrolessly plated. R-1750 manufactured by Panasonic Electric Works Co., Ltd. was used for the glass substrate epoxy substrate.

電子回路基板に搭載する半導体デバイスとして、大きさが８ｍｍ平方で、厚さが０．１５μｍのチップの主面周縁部に、２５６個の電極パッドが１００μｍピッチで配列されたデバイスを使用した。これら電極パッドは７０μｍ平方の寸法であり、それぞれにはＡｕが３〜５μｍの厚さに無電解メッキされている。   As a semiconductor device mounted on an electronic circuit board, a device in which 256 electrode pads were arranged at a pitch of 100 μm on the peripheral edge of the main surface of a chip having a size of 8 mm square and a thickness of 0.15 μm was used. These electrode pads have a dimension of 70 μm square, and each is electrolessly plated with Au to a thickness of 3 to 5 μm.

まず、半導体デバイスを電子回路基板の所定位置にダイボンドしてから、接続用の配線が形成されたシートを、各配線形成面とは反対側の面が半導体デバイス側となるよう配置した。この配置に際して、接続用配線の一端の接続部位と対応する電極パッドとを位置合わせし、かつ、接続用配線の他端の接続部位を電子回路基板の配線の所定部位に位置合わせした。そして、シートを半導体デバイスと電子回路基板とに押し当てた。   First, after the semiconductor device was die-bonded at a predetermined position on the electronic circuit board, the sheet on which the wiring for connection was formed was arranged so that the surface opposite to each wiring forming surface was the semiconductor device side. In this arrangement, the connection part at one end of the connection wiring and the corresponding electrode pad were aligned, and the connection part at the other end of the connection wiring was aligned with a predetermined part of the wiring of the electronic circuit board. Then, the sheet was pressed against the semiconductor device and the electronic circuit board.

次に、シートの所定部位にＮ−メチル−２−ピロリドンを含浸させ、その厚さを４μｍとした。これにより、接続用の配線と、対応する電極パッドおよび電子回路基板のランドとが電気的に接続された。電気的な接続を実現した後に、圧力１０-1の雰囲気中に５分間置いて脱泡処理をしてから、シートを電子回路基板に固定した。固定方法としては、ディスペンサ方式の吐出ノズルを使用して、シートの周縁に沿って液状の未硬化の絶縁性樹脂を塗布し、シートと半導体デバイスおよび電子回路基板との間の間隙部分に注入させた。注入完了後、約１５０℃に加熱して絶縁性樹脂を硬化させた。
（接続状態の確認） Next, a predetermined part of the sheet was impregnated with N-methyl-2-pyrrolidone, and the thickness thereof was 4 μm. Thereby, the wiring for connection and the corresponding electrode pad and the land of the electronic circuit board were electrically connected. After realizing the electrical connection, the sheet was fixed in an electronic circuit board after being defoamed by placing it in an atmosphere at a pressure of 10 −1 for 5 minutes. As a fixing method, using a dispenser-type discharge nozzle, a liquid uncured insulating resin is applied along the periphery of the sheet, and injected into a gap portion between the sheet, the semiconductor device, and the electronic circuit board. It was. After completion of the injection, the insulating resin was cured by heating to about 150 ° C.
(Check connection status)

この実施例の方法による、電極パッドと電子回路基板のランドとの間の接続状態について、次の方法で確認した。   The connection state between the electrode pad and the land of the electronic circuit board by the method of this example was confirmed by the following method.

図５に示すように、あらかじめ半導体デバイス６の電極パッド８ａと８ｂとをそれぞれ接続するアルミニウム配線膜５１を形成した以外は、上述の手順で実装を行った。そして、接続用配線７ａ、７ｂ間にデジタル・マルチメータ（Agilent Technologies社製３４４１０Ａ）５２を接続して、その間の抵抗を測定した。測定箇所数は１１２０である。   As shown in FIG. 5, the mounting was performed in the above-described procedure except that the aluminum wiring film 51 for connecting the electrode pads 8a and 8b of the semiconductor device 6 was previously formed. Then, a digital multimeter (Agilent Technologies 34410A) 52 was connected between the connection wires 7a and 7b, and the resistance between them was measured. The number of measurement points is 1120.

なお、電子回路基板として、厚さ０．４ｍｍのガラス基材エポキシ基板であるパナソニック電工株式会社製Ｒ−１７５０を使用し、導電性インクとしてハリマ化成株式会社製のＮＰＳ−Ｊを使用した。   In addition, Panasonic Electric Works Co., Ltd. R-1750 which is a 0.4 mm-thick glass base epoxy board | substrate was used as an electronic circuit board, and NPS-J by Harima Kasei Co., Ltd. was used as a conductive ink.

その結果を、図６に示す。図６において、その横軸は抵抗値を表し、縦軸はその分布数を表している。これから明らかなように、配線７ａ、７ｂ間の抵抗が６７．５ｍΩ以上、８７．５ｍΩの範囲内に分布し、７２．５ｍΩ以上、７５ｍΩ未満の範囲でピ−クを示していた。この結果から、すべての箇所で良好な電気的接続が実現されていることが確認できた。
（実施例２） The result is shown in FIG. In FIG. 6, the horizontal axis represents the resistance value, and the vertical axis represents the number of distributions. As is clear from this, the resistance between the wirings 7a and 7b was distributed in the range of 67.5 mΩ or more and 87.5 mΩ, and the peak was shown in the range of 72.5 mΩ or more and less than 75 mΩ. From this result, it was confirmed that good electrical connection was realized at all locations.
(Example 2)

この例では、電子回路基板上に搭載する電子部品として、実施例１におけるものと同じ半導体デバイスを使用し、各電極パッド上に高さ３０μｍのバンプを金の無電解メッキ法で形成した。   In this example, the same semiconductor device as in Example 1 was used as an electronic component to be mounted on an electronic circuit board, and a bump having a height of 30 μm was formed on each electrode pad by an electroless plating method of gold.

接続用配線を保持するためのシートとして、平均孔径３μｍ、空孔率７５％のポリエーテルイミドを使用し、その一方の表面にインクジェット法で導電性インクによる幅４０μｍの接続用の配線パターンを描画した。導電性インクにはハリマ化成株式会社ＮＰＳ−Ｊを使用した。パターン形成後、約２２０℃で加熱して、導電性インクの分散媒を揮発させて、接続用の配線を形成した。   Polyetherimide with an average pore diameter of 3 μm and a porosity of 75% is used as a sheet for holding the connection wiring, and a wiring pattern for connection with a width of 40 μm is drawn by conductive ink on one surface of the surface. did. Harima Kasei Co., Ltd. NPS-J was used for the conductive ink. After the pattern formation, heating was performed at about 220 ° C. to volatilize the dispersion medium of the conductive ink, thereby forming connection wiring.

まず、電子回路基板上の所定位置に半導体デバイスをダイボンドした後、ポリイミドシートを、それを介して配線の所定部位が対応するバンプおよび電子回路基板のランドと重なるように位置合わせをして配置した。   First, the semiconductor device was die-bonded at a predetermined position on the electronic circuit board, and then the polyimide sheet was positioned so that the predetermined portion of the wiring overlapped with the corresponding bump and the land of the electronic circuit board through the polyimide sheet. .

それから、シートに溶剤を含浸させ、当初２０μｍの厚さであったものを約４μｍまで薄くした。これにより、バンプの先端部分がシートの配線部分を貫通し、電気的に接続された。   Then, the sheet was impregnated with a solvent, and the original thickness of 20 μm was reduced to about 4 μm. Thereby, the front-end | tip part of bump penetrated the wiring part of the sheet | seat, and was electrically connected.

そして、１０-1Ｐａの減圧雰囲気中に５分間置いて脱泡処理をしてから、ディスペンサ方式の吐出ノズルを使用して、シートの周縁に沿うよう電子回路基板に液状の未硬化の絶縁性樹脂を塗布して、それらの隙間を通して、電子回路基板および半導体デバイスとシートとの間にある空間内に充填した。この絶縁性樹脂にはナミックス株式会社製チップコート８４２２を使用した。 Then, after 5 minutes of defoaming treatment in a reduced pressure atmosphere of 10 −1 Pa, using a dispenser-type discharge nozzle, the liquid uncured insulating property is applied to the electronic circuit board along the periphery of the sheet. Resin was applied and filled in the space between the electronic circuit board and the semiconductor device and the sheet through the gaps. A chip coat 8422 manufactured by Namics Co., Ltd. was used for this insulating resin.

絶縁性樹脂を必要部分に注入をし終えた後に、絶縁性樹脂を硬化させて、シートを電子回路基板に接着し固定した。   After the insulative resin was injected into the necessary portion, the insulative resin was cured, and the sheet was adhered and fixed to the electronic circuit board.

上述の確認方法と同様の方法で、シートに形成した配線による接続状態を調査したところ、シートの配線が半導体デバイスのバンプおよび電子回路基板の配線と確実にかつ低抵抗で接続されていた。   When the connection state of the wiring formed on the sheet was examined by the same method as the above-described confirmation method, the sheet wiring was reliably connected to the bumps of the semiconductor device and the wiring of the electronic circuit board with low resistance.

また、上述した位置合わせにおいてバンプとシートの配線との間で若干の位置ずれがあった場合には、その箇所を導電性インクで再描画することによって、容易に電気的に接続することができた。   In addition, if there is a slight misalignment between the bump and the sheet wiring in the above-described alignment, it can be easily electrically connected by redrawing the portion with conductive ink. It was.

本発明の電子部品の実装方法によれば、接続点数が増大しても、一度に接続するので生産効率に優れている。また、実装に際して圧力、超音波、熱を加えなくてもよいので、半導体チップや回路基板にダメージが加わらないという効果を有し、多数の外部電極端子を有する半導体デバイス等の実装方法として有用である。また、本発明の実装構造体によれば、接続点数の多いデバイスであっても量産に適した構造であるため、その製造コストが安価であり、また製造過程で圧力、超音波、熱等によるダメージを受けないため、高信頼性を要求される電子装置の構成要素として有用である。   According to the electronic component mounting method of the present invention, even if the number of connection points is increased, the connection is performed at a time, so that the production efficiency is excellent. In addition, since it is not necessary to apply pressure, ultrasonic waves, or heat when mounting, it has the effect of not damaging the semiconductor chip and circuit board, and is useful as a mounting method for semiconductor devices having a large number of external electrode terminals. is there. In addition, according to the mounting structure of the present invention, even a device with a large number of connection points is a structure suitable for mass production, so its manufacturing cost is low, and pressure, ultrasonic waves, heat, etc. are produced during the manufacturing process. Since it is not damaged, it is useful as a component of an electronic device that requires high reliability.

１ インクジェット印刷装置の吐出ノズル
２ 多孔質な構造を有するシート
３ 導電性インク
４ａ、４ｂ 接続用配線
５ 電子回路基板
６ 半導体デバイス
７ａ、７ｂ 配線
８ａ、８ｂ 電極パッド
９ ディスペンサ方式の吐出ノズル
１０ 絶縁性樹脂
２１ａ、２１ｂ バンプ
５１ アルミニウム配線膜
５２ デジタル・マルチメータ DESCRIPTION OF SYMBOLS 1 Discharge nozzle of inkjet printer 2 Sheet | seat which has porous structure 3 Conductive ink 4a, 4b Connection wiring 5 Electronic circuit board 6 Semiconductor device 7a, 7b Wiring 8a, 8b Electrode pad 9 Dispensing type discharge nozzle 10 Insulation Resin 21a, 21b Bump 51 Aluminum wiring film 52 Digital multimeter

Claims (10)

（１）複数の電極を有する電子部品を電子回路基板の所定位置に固定する工程、
（２）高分子材料からなる多孔質な構造のシートの表面に、導電性インクにより、前記電子部品の各電極とこれに対応する前記電子回路基板の各接続部位とを接続するための配線を形成する工程、
（３）前記配線を形成したシートをその裏面側が、前記配線が接続すべき前記電極と前記接続部位とにまたがるように、前記電子回路基板上に位置合わせする工程、
（４）前記シートの所定部位に溶剤を含浸させてその厚みを減じて、前記配線を前記電極および前記接続部位に電気的に接続する工程、および
（５）前記配線と前記電極および前記接続部位との電気的な接続が維持されるように前記シートを前記電子回路基板に固定する工程、
を具備することを特徴とする電子部品の実装方法。 (1) a step of fixing an electronic component having a plurality of electrodes at a predetermined position on an electronic circuit board;
(2) Wiring for connecting each electrode of the electronic component and each corresponding connection portion of the electronic circuit board to the surface of the porous structure sheet made of a polymer material with conductive ink. Forming step,
(3) a step of aligning the sheet on which the wiring is formed on the electronic circuit board so that a back surface thereof spans the electrode and the connection portion to which the wiring is to be connected;
(4) impregnating a predetermined portion of the sheet with a solvent to reduce its thickness and electrically connecting the wiring to the electrode and the connection portion; and (5) the wiring, the electrode and the connection portion. Fixing the sheet to the electronic circuit board so that electrical connection with the electronic circuit board is maintained;
An electronic component mounting method comprising: 前記導電性インクは、導電性ナノ粒子を主たる材料として含んでいることを特徴とする請求項１記載の電子部品の実装方法。   2. The electronic component mounting method according to claim 1, wherein the conductive ink contains conductive nanoparticles as a main material. 前記電極が突起形状をしていることを特徴とする請求項１または２記載の電子部品の実装方法。   3. The electronic component mounting method according to claim 1, wherein the electrode has a protruding shape. 前記電子部品は受動部品、能動部品、コネクタ部品、および電子回路基板のうちの少なくとも１種であることを特徴とする請求項１から３のいずれかに記載の電子部品の実装方法。   4. The electronic component mounting method according to claim 1, wherein the electronic component is at least one of a passive component, an active component, a connector component, and an electronic circuit board. 前記第３の工程において、前記溶剤を含浸させて前記シートの空孔体積を減少させることによって厚みを減じることを特徴とする請求項１から４のいずれかに記載の電子部品の実装方法。   5. The electronic component mounting method according to claim 1, wherein, in the third step, the thickness is reduced by impregnating the solvent to reduce a void volume of the sheet. 前記シートはポリアミドイミド、またはポリエーテルイミドを主成分として含み、また、前記溶剤はＮ−メチル−２−ピロリドン、Ｎ，Ｎ−ジメチルアセトアミド、ジメチルスルホキシド、γ−ブチロラクトン、シクロヘキサノンまたはスルホランであることを特徴とする請求項１から５のいずれかに記載の電子部品の実装方法。   The sheet contains polyamideimide or polyetherimide as a main component, and the solvent is N-methyl-2-pyrrolidone, N, N-dimethylacetamide, dimethyl sulfoxide, γ-butyrolactone, cyclohexanone or sulfolane. The electronic component mounting method according to claim 1, wherein the electronic component is mounted. 複数の電極を有する電子部品、前記電極それぞれと接続すべき複数の接続部位を有し、前記電子部品が取り付けられた電子回路基板、ならびに、前記電子部品の電極と前記電子回路基板の接続部位とをそれぞれ接続する複数の配線を有するシートを備えた実装構造体。   An electronic component having a plurality of electrodes, a plurality of connection parts to be connected to each of the electrodes, an electronic circuit board on which the electronic parts are attached, and a connection part between the electrodes of the electronic component and the electronic circuit board A mounting structure including a sheet having a plurality of wirings that respectively connect the two. 前記シートは少なくとも一部分が多孔質体である請求項７記載の実装構造体。   The mounting structure according to claim 7, wherein at least a part of the sheet is a porous body. 前記配線が、導電性インクで形成された請求項７または８記載の実装構造体。 The mounting structure according to claim 7 or 8, wherein the wiring is formed of a conductive ink. 前記電子部品が、前記電極を有する面とは反対側の面で、前記電子回路基板に取り付けられた請求項７から９のうちのいずれかに記載の実装構造体。   The mounting structure according to claim 7, wherein the electronic component is attached to the electronic circuit board on a surface opposite to a surface having the electrodes.
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