JP4279388B2 - The optical semiconductor device and method of forming - Google Patents

The optical semiconductor device and method of forming Download PDF

Info

Publication number
JP4279388B2
JP4279388B2 JP2323699A JP2323699A JP4279388B2 JP 4279388 B2 JP4279388 B2 JP 4279388B2 JP 2323699 A JP2323699 A JP 2323699A JP 2323699 A JP2323699 A JP 2323699A JP 4279388 B2 JP4279388 B2 JP 4279388B2
Authority
JP
Japan
Prior art keywords
optical semiconductor
flat plate
semiconductor device
semiconductor element
step
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2323699A
Other languages
Japanese (ja)
Other versions
JP2000223752A (en
Inventor
良馬 末永
洋一 松岡
Original Assignee
富士機工電子株式会社
日亜化学工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士機工電子株式会社, 日亜化学工業株式会社 filed Critical 富士機工電子株式会社
Priority to JP2323699A priority Critical patent/JP4279388B2/en
Publication of JP2000223752A publication Critical patent/JP2000223752A/en
Application granted granted Critical
Publication of JP4279388B2 publication Critical patent/JP4279388B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明はスイッチ内照明やドットマトリクスディスプレイの各種光源や光センサなど、SMD(Surface Maunt Device)などとして利用される表面実装用の光半導体装置に係わり、特に小型化可能であり、信頼性の高い光半導体装置及びその形成方法に関するものである。 The invention various light sources and light sensors in the illumination and a dot matrix display switch relates to a SMD (Surface Maunt Device) The optical semiconductor device for surface mounting which is used as such, in particular can be downsized, high reliability to an optical semiconductor device and a method of forming the same.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
今日、発光素子や受光素子はスイッチ内照明、ドットマトリクスディスプレイ等の各種光源やセンサとして種々利用されている。 Today, the light emitting element and the light receiving element is a switch in the lighting, it has been variously utilized as various light sources and sensors, such as a dot matrix display. 利用分野の広がりと共により小型化され回路基板上に直接実装できるようなSMD(Surface Maunt Device)などとして利用される表面実装用の光半導体装置が開発されつつある。 More miniaturized as directly mounted on a circuit board SMD (Surface Maunt Device) The optical semiconductor device for surface mounting which is used as such together with the FIELD spread are being developed. 光半導体装置は極めて小さく形成できると共に内部に配置される光半導体素子を保護するパッケージなどにより、扱い安さを向上させることができる。 Due packaged optical semiconductor device for protecting the optical semiconductor element arranged inside it is possible to extremely small formation, it is possible to improve the handling inexpensiveness.
【0003】 [0003]
このような光半導体装置として特開平8−125227号などが挙げられる。 Etc. JP 8-125227 can be mentioned as such an optical semiconductor device. 光半導体装置の具体的一例として本発明と比較のためのチップ部品型発光ダイオードを図6に示す。 The chip-type light emitting diode for comparison with this invention as a specific example of the optical semiconductor device shown in FIG. 図6に示す表面実装型発光ダイオード600は、貫通孔602を有する樹脂基板601に金属薄板604を設けたパッケージを利用してある。 A surface mount-type light-emitting diode 600 shown in FIG. 6, are utilized to package provided with a thin metal plate 604 to a resin substrate 601 having through holes 602. パッケージの表面から側面、裏面にかけては一対の配線パターン605、606が形成されている。 Side from the surface of the package, a pair of wiring patterns 605 and 606 are formed over the back surface. 一方の配線パターン606は、貫通孔内の側壁に沿って延びた金属薄板となっている。 One wiring pattern 606 has a thin metal plate which extends along the side wall of the through hole. 金属薄板上にはAgペースト607を用いてLEDチップを固定すると共にLEDチップ603の一方の電極と導通を取っている。 The on the metal sheet has taken the conduction with one of the electrodes of the LED chip 603 is fixed to the LED chip using the Ag paste 607. 他方の配線パターン605はパッケージに設けられた貫通孔の外側上面においてLEDチップ603の他方の電極と金属細線608を用いて導通を取っている。 Taking the conduction with the other electrode and the metal thin wires 608 of the LED chip 603 in the outer top surface of the other wiring patterns 605 through holes provided in the package. LEDチップ上に透明樹脂609を設けることにより表面実装型発光ダイオード600を形成してある。 By providing the transparent resin 609 on the LED chip is formed with a surface-mount type light emitting diode 600.
【0004】 [0004]
こうして形成された表面実装型発光ダイオードは貫通孔602及び金属薄板604を利用した凹部にLEDチップ603を配置させてあるため、全体の厚みを極めて薄くすることができる。 Thus formed surface mount-type light-emitting diodes for which had been placed an LED chip 603 in the recess using the through hole 602 and the metal sheet 604, it can be extremely thin total thickness. そのため、量産性よく小型化可能な表面実装型発光ダイオードを形成することができる。 Therefore, it is possible to form a high mass productivity can be downsized surface mounted light emitting diode.
【0005】 [0005]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
しかしながら、使用環境の広がりと共に求められるより厳しい環境下で使用されるにつれ、上記構成の表面実装型発光ダイオードなどにおいては十分な信頼性を得ることが難しくさらなる改良が求められていた。 However, as used in harsh environments than obtained with the spread of the use environment, a surface-mount type light emitting diode further improvement it is difficult to obtain sufficient reliability in such the above configuration has been demanded. 本発明は上記問題点に鑑み、信頼性が高く且つ薄型化が可能な光半導体装置を提供することを目的とする。 In view of the above problems, and an object thereof is high and thinner reliable to provide an optical semiconductor device capable.
【0006】 [0006]
【課題を解決するための手段】 In order to solve the problems]
本発明は、貫通孔が形成された絶縁性平板の一方の面側に設けられ該絶縁性平板よりも薄い薄板と、貫通孔を利用したキャビティ底面の薄板上に少なくとも樹脂を有するダイボンド部材によりダイボンドされた光半導体素子と、絶縁性平板に設けられた光半導体素子と外部とを電気的に接続させるリード電極と、キャビティ内の光半導体素子を被覆する透光性樹脂とを有する光半導体装置である。 The present invention, die-bonding a thin sheet than the insulative flat plate provided on one side of the through holes are formed insulating flat plate, the die bonding member having at least a resin on a thin plate of the cavity bottom surface using through holes in the optical semiconductor device including the optical semiconductor element is a lead electrode to electrically connect the optical semiconductor element and an external provided in the insulating flat plate, and a translucent resin that covers the optical semiconductor element in the cavity is there. 特に、 薄板が金属であり、その表面が、少なくとも樹脂又は多孔質材料である光半導体装置である。 In particular, the thin plate is a metal, the surface of an optical semiconductor device is at least a resin or a porous material. これにより、光半導体装置を量産性よく小型化できると共に信頼性を著しく向上し得るものである。 Thus, it is capable of significantly improving the reliability with an optical semiconductor device can mass production well downsized.
【0007】 [0007]
本発明の請求項2に記載の光半導体装置は、 多孔質材料がセラミックである。 The optical semiconductor device according to claim 2 of the present invention, the porous material is a ceramic. これにより光半導体素子からの放熱性を向上させるばかりでなく機械的強度を向上し得る。 Thus it can improve the mechanical strength not only to improve the heat dissipation from the optical semiconductor element. さらに、光利用効率を向上させ得ることもできる。 Furthermore, it is also possible can improve the light use efficiency.
【0008】 [0008]
本発明の請求項3に記載の光半導体装置は、薄板を構成する金属が樹脂によって封止され前記リード電極と電気的に独立している。 The optical semiconductor device according to claim 3 of the present invention, the metal constituting the sheet are sealed independently the so lead electrode electrically sealed by a resin. 接着シートなど接着剤で絶縁性平板と薄膜とを添設させた場合、光半導体装置の半田などの実装時に接着シートの界面から半田などが浸入する場合がある。 If is additionally provided with an insulating flat plate and a thin film with an adhesive such as an adhesive sheet, there is a case where such a surface of the adhesive sheet during mounting of solder of the optical semiconductor device solder from entering. 同様に水分が浸入することもある。 Similarly also the moisture from entering. 本発明はこのような水分や半田の浸入を防止すると共に薄板に導電性の部材を利用していたとしてもリード電極から電気的に独立しているため、薄板を介してリード電極間がショートすることを極めて低減することができる。 Because the present invention are electrically independent from even lead electrode as have utilized conductive member to the thin plate while preventing such moisture and solder penetration, between the lead electrodes are short-circuited through the sheet it is possible to extremely reduce it. また、薄板上の樹脂は、絶縁性を高める他に半田塗れ性を高め、光半導体装置を半田付け等する場合における電極間の短絡を防止する効果をも有する。 The resin of the sheet also has an effect of preventing short circuit between electrodes when the enhanced solder wettability in addition to improve the insulating properties, the optical semiconductor device such as soldering.
【0009】 [0009]
本発明の請求項4に記載の光半導体装置の形成方法は、絶縁性平板に貫通穴を形成する工程と、接着シートを介して絶縁性平板と金属とを添設する工程と、絶縁性平板上に少なくとも一対のリード電極を形成する工程と、貫通穴を利用したキャビティ底面の接着シート上に光半導体素子を少なくとも樹脂を有するダイボンド部材によってダイボンドする工程と、光半導体素子の各電極と絶縁性平板に形成されたリード電極とを導電性材料でそれぞれ電気的に接続する工程と、少なくとも光半導体素子を透光性樹脂で被覆する工程とを有する。 Forming method for an optical semiconductor device according to claim 4 of the present invention includes the steps of forming a through hole in the insulating flat plate, a step of additionally provided an insulating flat plate and the metal through an adhesive sheet, insulating flat plate forming at least a pair of lead electrodes on the steps of die-bonding the die bonding member having at least a resin an optical semiconductor element on the adhesive sheet of the cavity bottom surface using through holes, each of the electrodes and the insulating of the optical semiconductor element a step of electrically connecting each of the lead electrodes that are formed over a flat plate of a conductive material, and a step of coating a light resin translucent at least the optical semiconductor element. これにより比較的簡単な工程で小型化可能且つ信頼性の高い光半導体装置を量産性よく形成させることができる。 Thus miniaturization possible and high light reliable semiconductor device can be formed with good mass productivity by a relatively simple process.
【0010】 [0010]
本発明の請求項5に記載の光半導体装置の形成方法は、接着シートを有する絶縁性平板に貫通穴を形成する工程と、接着シートを介して絶縁性平板と、少なくとも絶縁性平板と対向する表面にセラミックを有する金属層とを添設する工程と、絶縁性平板に少なくとも一対のリード電極を形成する工程と、貫通穴を利用したキャビティ底面のセラミック上に光半導体素子を少なくとも樹脂を有するダイボンド部材によってダイボンドする工程と、光半導体素子の各電極と、絶縁性平板に形成されたリード電極とを導電性材料でそれぞれ電気的に接続する工程と、少なくとも光半導体素子を透光性樹脂で被覆する工程とを有する。 Forming method for an optical semiconductor device according to claim 5 of the present invention includes the steps of forming a through hole in an insulating flat plate having an adhesive sheet, and insulating flat plate via an adhesive sheet, facing the least insulating flat plate die bonding with a step of additionally provided with a metal layer having a ceramic surface and forming at least a pair of lead electrodes on an insulating flat plate, at least a resin and an optical semiconductor element on the ceramic cavity bottom using through hole a step of die-bonding the member, and each electrode of the optical semiconductor element, a step of connecting the lead electrodes respectively electrically with a conductive material formed on the insulating flat plate, at least covering the optical semiconductor element with light-transmitting resin and a step of. これにより上述と同様、比較的簡単な工程で小型化可能且つ信頼性の高い光半導体装置を量産性よく形成させることができる。 Thus as described above, it can be relatively simple process miniaturization possible and highly reliable optical semiconductor device may mass productivity in the formation.
【0011】 [0011]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
本発明者らは種々の実験の結果、貫通孔を持った絶縁性平板に特定の表面を持った薄板を添設することにより、小型化と信頼性とを向上させ得ることを見いだし本発明をなすに至った。 The present inventors have results of various experiments, by additionally provided a thin plate having a specific surface insulating flat plate having a through-hole, the present invention found that can improve and downsizing and reliability It led to the eggplant.
【0012】 [0012]
本発明の構成による信頼性向上の作用は定かではないが、貫通孔を持った絶縁性平板に添付された薄板の表面形状が大きく影響すると考えられる。 Although not clear the effect of the reliability improvement by the configuration of the present invention, the surface shape of the thin plate attached to an insulating flat plate having a through-hole is thought to greatly influence. 即ち、貫通孔を持った絶縁性平板及び薄板を利用することにより、量産性よく小型化を図ることができる。 That is, by utilizing the insulating flat plate and a thin plate having a through hole, it is possible to mass production well downsized. 特に、キャビティの凹部底面を構成する薄板は、絶縁性平板よりも薄くするなどすると光半導体素子からの熱を外部に放出しやすくなり駆動安定性や信頼性などの特性が向上できる。 In particular, the thin plate constituting the bottom surface of the recess of the cavity can improve the characteristics such as heat tends to release the external drive stability and reliability of the optical semiconductor element when such thinner than the insulating plates. 他方、光半導体装置の半田接続時や外部環境などからの種々の熱を薄板を介して光半導体素子や貫通孔内部に直接繰り返し与えられる影響も大きくなる。 On the other hand, the greater variety of heat directly repeated given effect within an optical semiconductor element and the through-hole through the sheet from the solder connections or when the external environment of the optical semiconductor device.
【0013】 [0013]
このような熱は光半導体素子を被覆する透光性樹脂と貫通孔の側壁や薄板との熱膨張率の差や形成時に混入した水分の膨張などにより光半導体素子を薄板などから剥離すると考えられる。 Believed Such heat peeling the optical semiconductor element such as a thin plate by thermal expansion difference or formed during the expansion of the water which is mixed with the side wall or sheet of the translucent resin and the through-hole covering the optical semiconductor element . 特に金属薄板を用いた場合は、光半導体素子を被覆する樹脂との密着性が相対的に低いばかりでなく、熱伝導性が高く樹脂との熱膨張率が著しく異なるために剥離傾向が極めて強いと考えられる。 Particularly in the case of using the metal sheet, it is not only relatively low adhesion to a resin for covering the optical semiconductor element, a very strong peeling tends to have significantly different coefficients of thermal expansion of the high thermal conductivity resin it is conceivable that. 光半導体素子と薄板との剥離は光学特性を変化させるばかりでなく、電極近傍の導電性部材である金属細線の断線などを生じさせる。 Peeling of the optical semiconductor element and the thin plate not only by changing the optical properties, causing the disconnection of the metal thin wire is a conductive member of the electrode vicinity. 場合によっては光半導体素子と外部との電気的に導通がとれないという不都合を生ずる。 When causing inconvenience is not possible to electrically conduct between the optical semiconductor element and the outside by.
【0014】 [0014]
本発明は、図1の斜視図に示す如く、貫通孔が形成された絶縁性平板101の一方の面側に設けられ絶縁性平板よりも薄い薄板111と、貫通孔を利用したキャビティ底面の薄板上に少なくとも樹脂を有するダイボンド部材によりダイボンドされた光半導体素子103と、絶縁性平板に設けられた光半導体素子103と外部とを電気的に接続させるリード電極105と、キャビティ内の光半導体素子を被覆する透光性樹脂109とを有する光半導体装置である。 The present invention, as shown in the perspective view of FIG. 1, and one provided on the surface side insulating flat thin sheet 111 than the insulating flat plate 101 having a through hole formed, a thin plate of a cavity bottom using a through-hole an optical semiconductor element 103 is die-bonded by die bonding member having at least a resin on a lead electrode 105 for electrically connecting the external and the optical semiconductor element 103 provided on an insulating flat plate, an optical semiconductor device in the cavity an optical semiconductor device having a light-transmitting resin 109 covering. 特に、キャビティ底面を構成する薄板111の表面は、少なくとも樹脂112となっている。 In particular, the surface of the thin plate 111 constituting the cavity bottom surface has a least a resin 112. これにより、小型化、量産性を維持しつつ、光半導体素子を被覆する透光性樹脂、光半導体素子を実装するダイボンド部材などとの密着性を向上させた薄板を利用することで、より信頼性を向上せしめ得るものである。 Thus, size reduction, while maintaining the mass production, by using a translucent resin for covering the optical semiconductor element, a thin plate having improved adhesion between such die bonding member for mounting optical semiconductor elements, more reliable it is capable allowed improving sexual. 以下、本発明の実施例について詳述するがこれのみに限られないことはいうまでもない。 Hereinafter, it is needless to say that although described is not limited only to this for the embodiment of the present invention.
【0015】 [0015]
【実施例】 【Example】
(実施例1)以下、本発明の実施例を図面を用いて説明する。 (Example 1) Hereinafter, an embodiment of the present invention with reference to the drawings. 図2、図3は本発明の一実施例を示すものであり、その製造工程を図3に基づいて説明する。 2, FIG. 3 shows an embodiment of the present invention will be described with reference to the manufacturing process in FIG. あらかじめ、リード電極の一部を構成する銅箔が好適に形成されたガラスエポキシを絶縁性平板101として利用する(図3A工程)。 Advance, utilizes a glass epoxy copper foil is preferably formed to constitute a part of the lead electrode as an insulating flat plate 101 (FIG. 3A step).
【0016】 [0016]
絶縁性平板101には後に、光半導体素子であるLEDチップ103が配置されるキャビティを構成する貫通孔を形成する。 After the insulating flat plate 101, to form through holes constituting the cavity LED chip 103 is an optical semiconductor element is arranged. 絶縁性平板101は、LEDチップなどの光半導体素子103を外部から保護すると共に薄型化が可能なものが好ましく、具体的にはガラスエポキシ、液晶ポリマー、アクリル樹脂、エポキシ樹脂やセラミックなど種々のものを利用することができる。 Insulating flat plate 101 is preferably one that can be thinned while protecting the optical semiconductor element 103 such as an LED chip from outside, specifically glass epoxy, a liquid crystal polymer, various acrylic resins, epoxy resins and ceramic ones it can be utilized. 絶縁性平板101に設けられる貫通孔は、内部に光半導体素子を配置させる程度の大きさでよく、光半導体素子として、RGB(赤色、緑色、青色)のLEDチップを配置させる場合、YB(黄色、青色)のLEDチップを配置させる場合や発光素子と受光素子とを共に配置させる場合など複数個利用する場合はそれぞれが配置可能な大きさとすればよい。 If the through hole provided in the insulating flat plate 101, inside well large enough to place the optical semiconductor element, which as an optical semiconductor element, RGB (red, green, blue) to place the LED chip, YB (yellow , respectively when the plurality utilized may be the size that can be placed such case of co-located or if the light emitting element and a light receiving element for placing the LED chip of the blue). したがって、絶縁性平板に形成される貫通孔は光半導体素子の大きさ、形状や数に合わせて絶縁性平板の種々の位置に複数設けることもできる。 Therefore, the through hole formed in the insulating flat plate size of the optical semiconductor element can be provided more on the various positions of the insulating flat plate in accordance with the shape and number.
【0017】 [0017]
同様に、絶縁性平板101の厚みは貫通孔を利用することによりキャビティの深さを構成するため、所望に応じて種々の厚みのものを利用することができる。 Similarly, the thickness of the insulating flat plate 101 for constituting the depth of the cavity by utilizing the through-holes, can be utilized a variety of thicknesses as desired. また、特に光半導体素子として窒化物半導体である活性層をダブルへテロ構造とした発光素子を利用する場合、活性層の端面方向から放出される光が極めて多いため、キャビティの側壁となる貫通孔に反射性の高い材質を利用することが好ましい。 In particular when using a light-emitting element in which the active layer is a nitride semiconductor as an optical semiconductor element to double the heterostructure, because the light is very often emitted from the end surface direction of the active layer, through holes serving as the side walls of the cavity it is preferable to use a highly reflective material to. これにより貫通孔を形成するだけで光利用効率の高い光半導体装置とすることができる。 This makes it possible to light use efficient optical semiconductor device by simply forming the through-hole. 具体的には、キャビティ側壁には可視光の短波長側で光の吸収の大きいAuメッキなどを形成させることなく、絶縁性樹脂平板の白色材質面を露出させることで効果的に光を利用することができる。 Specifically, the cavity side wall without forming such large Au plating absorption of light in the short wavelength side of visible light, effectively utilizing light by exposing the white material surface of the insulating resin flat plate be able to.
【0018】 [0018]
キャビティを構成する貫通孔は絶縁性平板が薄くとも貫通孔により比較的簡単に制御性よく形成できるため、極めて浅く形成することができる。 Since the through holes constituting the cavity can be formed with favorable relatively easily controllability by the through-holes with a thin insulating flat plate, can be very shallow. 具体的には約200μm以下程度の厚さとすることもできる。 More specifically, the CPU 11 can also be a thickness of the order of about 200μm or less. このような貫通孔は、絶縁性平板をエッチングすることにより構成することができるし、ドリルを用いて機械的に構成することもできる。 Such through-holes, it can be configured by etching the insulating flat plate, it may be mechanically configured using a drill. さらに、炭酸ガスを利用したガスレーザー、YAGを利用した固体レーザーなど各種レーザーを用いて貫通孔を形成することもできる。 Furthermore, it is also possible to form a through hole by using gas lasers using carbon dioxide, various lasers such as a solid state laser using a YAG. エッチング溶液の選択、ドリルの刃先形状やレーザー光の集光を調整することで貫通孔の形状をすり鉢状や円柱状など所望に調整することもできる。 Selection of the etching solution, the shape of the through hole can be adjusted to the desired, such as bowl shape or a cylindrical shape by adjusting the condensing drill tip shape or a laser beam. 同様に正面から見た貫通孔の形状も円形のみに限定されず、楕円形、正方形、長方形、縁なしの矩形や複数の円形が連続して貫通した形状など所望に応じて種々のものを選択することができる。 Similarly not limited shape of the through-hole is also only circular as viewed from the front selection, oval, square, rectangular, having various as desired, such as a shape rectangular or more circular penetrates successively frameless can do.
【0019】 [0019]
次に、略中央に貫通穴が形成された絶縁性平板に薄板として厚さ約60μmのエポキシ樹脂からなる接着シート112を介して金属層111を張り合わせ貫通孔を利用したキャビティ102を形成する。 Next, a cavity 102 using a through hole bonding the metal layer 111 through the adhesive sheet 112 having a thickness of about 60μm of the epoxy resin as a sheet on an insulating flat plate having a through hole is formed substantially in the center. 薄板111を絶縁性平板101よりも薄くすることで光半導体装置100全体の厚みを薄くできると共に放熱性を向上させ得ることができる。 Can be obtained to improve the heat dissipation properties with a thin plate 111 can be made thin optical semiconductor device 100 total thickness by thinner than the insulating flat plate 101. 絶縁性平板101は光半導体素子103を保護する或いは光利用効率を向上させるなどのために厚みの制限が設けられやすいのに対し、薄板111は光半導体素子103を支持することができればよいからである。 While easy to thickness limitations provided for an insulating flat plate 101 improves the or light use efficiency to protect the optical semiconductor element 103, the thin plate 111 because it is only necessary to support the optical semiconductor element 103 is there.
【0020】 [0020]
薄板111として約30から170μmの厚さのものを好適に利用することができる。 It can be suitably used those of about 30 to a thickness of 170μm as a thin plate 111. 本発明の薄板111はダイボンド樹脂を介して光半導体素子を固定する。 Sheet 111 of the present invention for fixing the optical semiconductor element through the die bonding resin. 或いは、透光性樹脂であるモールド部材109などと接する場合があり、ダイボンド樹脂107や樹脂モールド部材109などとの密着性が優れた表面を持つ。 Alternatively, there are cases where contact with such mold member 109 is a translucent resin, having an excellent surface adhesion and the like die bonding resin 107 and the resin mold member 109. 薄板の具体的表面としてはダイボンド樹脂などとの化学的や機械的に結合できるような密着性の優れた樹脂表面112や多孔質表面を持ったセラミックなどを利用することができる。 Specific surface of the thin plate can be utilized such as a ceramic having a chemical and mechanical bond can such adhesion excellent resin surface 112 and porous surface with such die bonding resin. 極めて薄い接着性樹脂シートなどを利用した薄板の場合、機械的強度が得られ難いため補強用部材として金属やセラミックなどを添設させることもできる。 If thin plate using such extremely thin adhesive resin sheet, it is also possible mechanical strength to additionally provided a metal or ceramic as a reinforcing member for difficult to obtain. 補強用に金属を利用した場合、光半導体装置の各電極との短絡を防止するためにレジストインクなどの樹脂を利用して絶縁性被覆していることが好ましい。 When using metal for the reinforcement, it is preferable to use a resin such as a resist ink has insulating covering in order to prevent a short circuit between the electrodes of the optical semiconductor device.
【0021】 [0021]
なお、接着シート112を白色系の反射率の高い材質を利用すると共に光半導体素子103を窒化物半導体発光素子を利用するとさらに光利用効率を高めることもできる。 Incidentally, an adhesive sheet 112 may be further enhanced light use efficiency when the optical semiconductor element 103 utilizes a nitride semiconductor light emitting device with utilizes a material having higher reflectivity of white. 同様に、樹脂絶縁性平板101であり側壁となる白色材質面が露出したキャビティ102内に絶縁性基板上に少なくとも発光層がダブルへテロ構造の窒化物半導体であり同一面側に一対の電極を有する光半導体素子103を、配置させることにより光利用効率をさらに高めることもできる。 Similarly, a pair of electrodes are on the same side nitride semiconductor heterostructure least a light emitting layer is a double on an insulating substrate a white material surface exposed cavity 102 as a and the sidewall resin insulating flat plate 101 the optical semiconductor element 103 having, it is also possible to further enhance the light utilization efficiency by placing. また、接着シート112の組成や溶媒を光半導体素子103を接着するダイボンド樹脂107の組成に同一或いは近づけることにより、より強固な接着強度を得ることもできる。 Further, by the same or close to the composition of the die bonding resin 107 for bonding the optical semiconductor element 103 the composition and the solvent of the adhesive sheet 112, it is also possible to obtain a more firm adhesion strength.
【0022】 [0022]
次に、薄板111となる銅板をキャビティ底面が絶縁性平板に固定される部位を残してエッチングした(図3のB工程)。 Then, a copper plate as a thin plate 111, leaving a portion cavity bottom is fixed to the insulating plates were etched (B process of FIG. 3).
【0023】 [0023]
また、好適には銅板の密着強度を高めると共に絶縁性を確保するために露出した薄板111である銅板を樹脂113により封止した。 Also, preferably the copper plate is a thin plate 111 exposed in order to ensure insulation to increase the adhesion strength of the copper plate was sealed with a resin 113. 続いて、光半導体装置の外部リード電極105、106を形成する。 Subsequently, to form external lead electrodes 105 and 106 of the optical semiconductor device. 外部リード電極105、106は電解及び無電解メッキ法を利用して絶縁性平板101の発光或いは入射側上面、上面と対向する下面及び側面にメッキ層を形成することにより極めて薄膜のリード電極を比較的簡単に形成することができる。 External lead electrodes 105 and 106 compares the extremely thin film of the lead electrodes by forming a plating layer emitting or incident side upper surface of the insulating flat plate 101 by using the electrolytic and electroless plating method, the lower and side surfaces facing the upper surface it can be specifically formed easily. さらに、写真法を利用して、絶縁性平板の発光側上面及び下面のメッキ層を補強することもできる。 Furthermore, by utilizing photography, it is also possible to reinforce the emission side upper and lower surfaces of the plated layer of insulating plates. こうして、光半導体素子が配置されるキャビティ102及びリード電極105、106が形成されたパッケージを形成することができる(図3C工程)。 Thus, it is possible to form a package cavity 102 and the lead electrodes 105, 106 an optical semiconductor element is disposed is formed (FIG. 3C step).
【0024】 [0024]
なお、キャビティを構成する薄板の補強部材である金属板とリード電極105、106とは電気的に独立している。 Note that electrically independent of the metal plate and the lead electrodes 105 and 106 is a reinforcing member of the thin plate constituting the cavity. また、樹脂113によってその端部を封止すると共に絶縁性を高めている。 Furthermore, to enhance the insulating properties as well as seal the end by a resin 113. ここでは、リード電極を形成させた後に樹脂によって薄板を封止することを開示したが、薄板を封止した後に樹脂によって封止することもできることはいうまでもない。 Here, it disclosed the sealing sheet with a resin after forming the lead electrode, it is needless to say that can be sealed with a resin after sealing the sheet.
【0025】 [0025]
続いて、貫通穴を利用して形成されたキャビティ102底面の接着シート112上にダイボンド樹脂107として透光性エポキシ接着剤により、少なくとも発光層が窒化ガリウム系化合物半導体のLEDチップ103をダイボンド機器を用いてダイボンドする。 Subsequently, the light transmissive epoxy adhesive as the die bonding resin 107 on the adhesive sheet 112 of the cavity 102 bottom surface formed by utilizing the through holes, the die bonding apparatus at least a light-emitting layer is a gallium nitride compound semiconductor LED chip 103 to die bonding using. キャビティ102内に配置されたLEDチップ103とパッケージに形成された発光側上面のリード電極105、106とを直径約30μmのAuを利用してワイヤボンドする(図3D工程)。 And a light emitting side upper surface of the lead electrodes 105 and 106 formed on the LED chip 103 and the package disposed in the cavity 102 by using the Au with a diameter of about 30μm wire bonding (Fig. 3D step).
【0026】 [0026]
LEDチップ103とパッケージに形成されたリード電極105、106との接続は、小型化、接続強度や量産性等を考慮して20から40μmの導電性ワイヤ108を利用して電気的に導通を取ることができる。 Connection between the lead electrodes 105 and 106 formed on the LED chip 103 and the package is compact, taking electrical continuity from to 20 consider the connection strength and mass productivity by utilizing the conductive wire 108 of 40μm be able to. また、導電性ワイヤの材料としては金、アルミニウムなど種々の特性に合わせて適宜選択することができる。 As a material of the conductive wires can be appropriately selected depending on gold, in various properties such as aluminum.
【0027】 [0027]
同様に、光半導体素子とリード電極との導通を取るためだけであれば薄膜との密着性を損なわない限り光半導体素子の電極同士がショートしないように酸化珪素などの絶縁性保護膜で電極を除く半導体素子部分を被覆した後、銀、カーボン、ITOなどの導電性フィラーを含有させた導電性樹脂や半田などをダイボンド部材兼導電性部材として利用することもできる(不示図)。 Similarly, the electrode with an insulating protective film such as silicon oxide as electrodes of the optical semiconductor device as long as it does not impair the adhesion between the thin film if only does not short to take the continuity between the optical semiconductor element and the lead electrode after coating the semiconductor element portion excluding, silver, carbon, conductive conductive filler was contained, such as ITO resin or solder, etc. can be used as a die bonding member Kenshirube conductive member (not 示図). また、ダイボンド樹脂としては金、銀、銅などの金属やITO、酸化錫などの金属酸化物、さらには導線性に優れたカーボンなどを所望に応じて混入させることができる他、ダイボンド樹脂の耐光性を向上させるためにガラスなどの無機物質などを混入させることもできる。 Further, gold as the die bonding resin, silver, metal, ITO, such as copper, metal oxides such as tin oxide, other and further can be mixed as desired, such as carbon which is excellent in wire resistance, the die bonding resin light etc. can also be mixed with inorganic materials such as glass in order to improve the resistance. これにより半導体層を介して一対の電極を持った光半導体素子においても本発明を適用することができる。 Thus also possible to apply the present invention in an optical semiconductor device having a pair of electrodes through the semiconductor layer.
【0028】 [0028]
本発明において光半導体素子103とは、種々の半導体を利用した発光素子や受光素子を利用することができる。 The optical semiconductor element 103 in the present invention can be used a light emitting element and a light receiving element using various semiconductor. 具体的な発光素子としては、サファイア、スピネル、SiCやGaN基板上に窒化物半導体を積層したものを好適に利用することができる。 Specific emitting element can sapphire, spinel, be suitably used a material obtained by laminating the nitride semiconductor SiC or GaN substrate. 窒化物半導体はそのバンドギャップにより紫外域から可視域まで種々の電磁波を放出することができる。 Nitride semiconductor can emit various electromagnetic waves to the visible region from ultraviolet region by the bandgap. 特に、窒化物半導体はサファイア基板上に形成させることで結晶性と量産性の両立した発光素子とすることができる。 In particular, it can be crystalline and the mass productivity of both the light emitting element by the nitride semiconductor is formed on a sapphire substrate. また、サファイア基板上に窒化ガリウム系化合物半導体を有し同一平面側に一対の電極を形成させたLEDチップは、サファイア基板及び窒化ガリウム共に硬度が高いためサファイア基板を研磨するなど約150μm以下の薄型にすることができる。 Further, LED chips to form a pair of electrodes on the same plane side has a gallium nitride-based compound semiconductor on a sapphire substrate, such as polishing the sapphire substrate has high hardness sapphire substrate and gallium nitride both about 150μm or less thin it can be. より具体的には、全高が70〜90μmのLEDチップを利用すると、光半導体装置の高さを約0.3mm以下とすることができる。 More specifically, the overall height to use a LED chip 70~90Myuemu, can be the height of the optical semiconductor device about 0.3mm or less.
【0029】 [0029]
このような光半導体素子103は絶縁性基板上に一対の電極を形成するため小型化且つ光利用効率の向上を図ることができ、本発明の効果が特に大きい。 Such an optical semiconductor element 103 can be improved in size and light utilization efficiency for forming a pair of electrodes on an insulating substrate, is particularly large effect of the present invention. なお、他の半導体素子としてはガリウム燐やガリウム砒素基板上にインジウム・アルミニウム・ガリウム・燐である発光層を持った発光素子を利用することもできる。 It is also possible to use a light-emitting element having a light-emitting layer is indium-aluminum-gallium phosphide on gallium phosphide or gallium arsenide substrate as other semiconductor elements. 同様に、シリコン基板上に不純物を高濃度にドープしたシリコンである受光層を持った受光素子とすることもできる。 Similarly, it may be a light receiving element having a light receiving layer is silicon doped at a high concentration impurity on a silicon substrate.
【0030】 [0030]
最後に、キャビティ102内にLEDチップ103が配置され、金線108でLEDチップの各電極とパッケージのリード電極105、106とを接続させたパッケージ表面を部分的にモールド部材109として透光性エポキシ樹脂により射出成型によって封止させる(図3E工程)。 Finally, the LED chip 103 is disposed in the cavity 102, light-transmitting epoxy partly as mold member 109 of each electrode and the package surface obtained by connecting package of the lead electrodes 105 and 106 of the LED chip gold wires 108 thereby sealed by injection molding of a resin (Fig. 3E step).
【0031】 [0031]
モールド部材はLEDチップや導電性ワイヤなどを外部環境や外力から保護するために好適に設けられるものであり、エポキシ樹脂、シリコーン樹脂、ユリア樹脂や低融点ガラスなど種々のものを利用することができる。 The mold member is intended to be suitably provided to protect the LED chip and the conductive wires from the external environment or an external force, it can be used epoxy resins, silicone resins, any of various such urea resin or low melting point glass . モールド部材は光半導体素子に入射される光や光半導体素子から放出される光を集光或いは拡散させるために凸レンズ形状や凹レンズ形状とすることができる。 Mold member may be a convex shape or concave shape in order to condensing or diffusing light emitted from the light and the optical semiconductor element is incident to the optical semiconductor element. また、凸レンズも所望となる指向特性に合わせて単なる凸レンズや楕円レンズ形状など種々選択させることができる。 Further, it is possible to variously selected such mere convex and oval lens shape to fit the directional characteristic convex lens is also desired. また、モールド部材には不要な波長をカットする目的で種々の着色剤、拡散光を得る目的で酸化チタン、酸化珪素などの拡散材を含有させることができる。 Further, the mold member may contain various colorants in order to cut unnecessary wavelengths, titanium oxide for the purpose of obtaining a diffused light, a diffusing material such as silicon oxide.
【0032】 [0032]
また、発光素子から放出される電磁波の少なくとも一部を他の波長に変換させるペリレン系誘導体やセリウムで付活されたイットリウム・アルミニウム・ガーネット系酸化物などの蛍光体を含有させ白色発光可能な光半導体装置とすることもできる。 Further, at least a portion is containing a phosphor such as activated yttrium-aluminum-garnet based oxide with a perylene derivative and cerium which is converted into another wavelength white emission can light the electromagnetic wave emitted from the light emitting element It can also be a semiconductor device. こうして一辺がそれぞれ約1.2mm、約1.8mmの矩形状であって、厚さが約0.3mmとなる極めて小型な光半導体装置を比較的簡単に形成することができる。 Thus one side each about 1.2 mm, a rectangular shape of approximately 1.8 mm, can be relatively easily form a very compact optical semiconductor device having a thickness of about 0.3 mm.
【0033】 [0033]
(実施例2) (Example 2)
次に、図4に示す構造の光半導体装置について詳述する。 Next, it will be described in detail an optical semiconductor device having the structure shown in FIG. 実施例1と同様の絶縁性平板401を利用して薄板411を添設しリード電極405、406をメッキさせることによりパッケージを形成させた。 To form a package by plating the additionally provided with lead electrodes 405 and 406 of the thin plate 411 by using the same insulating flat plate 401 as in Example 1. なお、実施例1とは異なり、絶縁性平板にエポキシ樹脂からなる接着シートを張り合わせ接着層を形成させた(図5A工程)後、接着層ごと貫通孔を形成させた。 Unlike the first embodiment, after to form an adhesive layer laminated an adhesive sheet made of an epoxy resin insulating flat plate (Fig. 5A step), to form an adhesive layer by through holes.
【0034】 [0034]
キャビティ402を構成する貫通孔を形成させた絶縁性平板401の接着層412が形成された面に、あらかじめ銅箔上にセラミック414を蒸着させた薄膜411をキャビティの底面として利用するため添設した(図5B工程)。 A plane adhesive layer 412 is formed of an insulating flat plate 401 through holes were formed to constitute a cavity 402 was additionally provided to use the thin film 411 was deposited the ceramic 414 in advance on the copper foil as the bottom surface of the cavity (Figure 5B step). 薄板を添設後、銅箔をキャビティ底部を残して銅箔をエッチングし、リード電極405、406と電気的に独立させるべく絶縁樹脂413によって封止してある(図5C工程)。 After additionally provided a thin plate, the copper foil was etched copper foil, leaving a cavity bottom, are sealed by a lead electrode 405 and 406 and electrically independent insulated resin 413 in order to (Figure 5C step). なお、キャビティの底面となる部位を切り抜いた接着シートを張り付けた薄膜により絶縁性平板に添設させることもできる。 It is also possible to additionally provided on the insulating flat plate by a thin film stuck to adhesive sheet cut out portion to be the bottom surface of the cavity.
【0035】 [0035]
薄板として具体的には厚さ約35μmのCu泊上にセラミックを蒸着させ総膜厚約50μmで表面が白色で多孔性のセラミック複合金属層20である。 Specifically, a ceramic composite metal layer 20 surface of the porous white total thickness of about 50μm by depositing a ceramic on the Cu foil having a thickness of about 35μm as sheet. これ以外は実施例1と同様にして光半導体素子403をマウント部材407としてエポキシ樹脂によりダイボンドすると共に電気的に導通を取った(図5D工程)。 Other took electrically conductive as well as die bonding with epoxy resin an optical semiconductor element 403 in the same manner as in Example 1 as the mount member 407 (FIG. 5D step). これにモールド部材409を形成させ光半導体装置400を形成させた(図5E工程)。 This was a molding member 409 is formed to form an optical semiconductor device 400 (FIG. 5E step). 実施例2で形成された光半導体装置は実施例1に比べて放熱性が優れている反面、外部からの熱も受けやすい。 Although the optical semiconductor device formed in Example 2 has excellent heat dissipation properties than in Example 1, heat is also susceptible to external. しかしながら、形成された光半導体装置の熱衝撃試験では実施例1とほとんど遜色なかった。 However, in the thermal shock test of the formed optical semiconductor device it was little inferior to Example 1.
【0036】 [0036]
なお、本発明の具体的実施例においては、それぞれ一個ずつの光半導体装置において説明しているが、量産性よく形成させるためには絶縁性平板にドットマトリックス状に複数の貫通穴を形成する。 In the specific embodiment of the present invention has been described in the optical semiconductor device of one by one, respectively, in order to form good productivity to form a plurality of through-holes in a dot matrix on an insulating flat plate. 絶縁性平板全体に接着シートを介して絶縁性平板と金属を個々の貫通孔に対応などして添設した後、上述の工程を介して光半導体装置を形成する。 After additionally it provided in such corresponding to each of the through holes of the insulating flat plate and the metal through an adhesive sheet to the whole insulating flat plate, to form an optical semiconductor device through the above steps. 形成させた光半導体装置を個々に分離させることによって複数個の光半導体装置を量産することができる。 It can be mass-produced a plurality of optical semiconductor devices by causing an optical semiconductor device having formed individually separated. また、個々に分離させなければドットマトリックス状の光半導体装置を形成することもできる。 It is also possible to form a dot matrix of the optical semiconductor device to be brought individually separated.
【0037】 [0037]
(比較例1) (Comparative Example 1)
薄板を厚さ約50μmの銅板とし銅板上にエポキシ樹脂により直接LEDをダイボンドさせた以外は実施例1と同様にして光半導体装置を形成させた。 Except that was die-bonded directly LED with epoxy resin on a copper plate and a copper plate having a thickness of about 50μm thin plates in the same manner as in Example 1 to form an optical semiconductor device. 形成させた実施例1及び比較例1の光半導体装置を1400個用いて、それぞれ−20℃30分、80℃30分で500サイクルの条件で熱衝撃試験を行った。 Using 1400 pieces of optical semiconductor device was formed in Example 1 and Comparative Example 1, -20 ° C. 30 minutes, respectively, were subjected to a thermal shock test under the conditions of 500 cycles at 80 ° C. 30 minutes. 試験後、実施例1の不灯となった発光ダイオードは比較例1の発光ダイオードの3割にも満たなかった。 After the test, the light emitting diode has become non-lighting of Example 1 was less than 30% of the light-emitting diode of Comparative Example 1. 不灯となった比較例1の発光ダイオードを調べたところ薄膜となる銅板とダイボンド部材とが剥離していると共にワイヤの断線も生じていた。 And the copper plate and the die bonding member made of a thin film was examined emitting diode of Comparative Example 1 became Fuakari has occurred also disconnection of the wires together are detached.
【0038】 [0038]
【発明の効果】 【Effect of the invention】
本発明は、小型化可能な光半導体装置の薄板表面状態を特定の表面とさせることにより、光半導体装置を小型化できると共に信頼性を著しく向上し得るものである。 The present invention, by a thin surface condition of miniaturization possible optical semiconductor device with a specific surface, in which an optical semiconductor device capable of remarkably improving the reliability with can be miniaturized. また、本発明の方法は上述の光半導体装置を量産性よく形成することができるものである。 The method of the present invention is capable of forming good mass productivity of the above optical semiconductor device.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】 本発明の光半導体装置の模式的斜視図である。 1 is a schematic perspective view of an optical semiconductor device of the present invention.
【図2】 本発明の光半導体装置の模式的断面図である。 2 is a schematic cross-sectional view of an optical semiconductor device of the present invention.
【図3】 図1に示す光半導体装置の形成方法を説明するための工程図である。 3 is a process diagram for explaining a method of forming an optical semiconductor device shown in FIG.
【図4】 本発明の他の光半導体装置の模式的断面図である。 4 is a schematic cross-sectional view of another optical semiconductor device of the present invention.
【図5】 図3に示す光半導体装置の形成方法を説明するための工程図である。 5 is a process diagram for explaining a method of forming an optical semiconductor device shown in FIG.
【図6】 本発明と比較のために示す光半導体装置の模式的断面図である。 6 is a schematic cross-sectional view of an optical semiconductor device shown for the present invention and comparative.
【符号の説明】 DESCRIPTION OF SYMBOLS
100・・・光半導体装置101・・・絶縁平板102・・・キャビティ103・・・光半導体素子105、106・・・リード電極107・・・マウント部材108・・・ワイヤ109・・・モールド部材111・・・薄板112・・・接着シート113・・・薄板の少なくとも端部を覆う樹脂400・・・光半導体装置401・・・絶縁平板402・・・キャビティ403・・・光半導体素子405、406・・・リード電極407・・・マウント部材409・・・モールド部材411・・・薄板412・・・接着層413・・・絶縁樹脂414・・・光半導体素子が配置される側の薄板表面を構成するセラミック601・・・樹脂基板602・・・貫通孔603・・・LEDチップ604・・・金属薄板605、606・・・配線パタ 100 ... optical semiconductor device 101 ... insulating flat plate 102 ... cavity 103 ... optical semiconductor element 105, 106 ... lead electrodes 107 ... mount member 108 ... wire 109 ... molding member 111 ... sheet 112 ... adhesive sheet 113 ... at least an end portion resin 400 ... optical semiconductor device covering the thin plates 401 ... insulating flat plate 402 ... cavity 403 ... optical semiconductor element 405, 406 ... lead electrodes 407 ... mount member 409 ... mold member 411 side of the sheet surface ... sheet 412 ... adhesive layer 413 ... insulating resin 414 ... optical semiconductor element is arranged constituting the ceramic 601 ... resin substrate 602 ... through hole 603 ... LED chips 604 ... sheet metal 605, 606 ... wire pattern ンとなるリード電極607・・・Agペースト608・・・ワイヤとなる金属細線609・・・モールド部材となる透明樹脂 The emission lead electrodes 607 ... Ag paste 608 ... wire become fine metal wires 609 ... sealing member to become transparent resin

Claims (5)

  1. 貫通孔が形成された絶縁性平板の一方の面側に設けられ該絶縁性平板よりも薄い薄板と、前記貫通孔を利用したキャビティ底面の薄板上に少なくとも樹脂を有するダイボンド部材によりダイボンドされた光半導体素子と、前記絶縁性平板に設けられた光半導体素子と外部とを電気的に接続させるリード電極と、前記キャビティ内の光半導体素子を被覆する透光性樹脂とを有する光半導体装置であって、前記キャビティ底面を構成する薄板が金属であり、その表面は、少なくとも樹脂又は多孔質材料であることを特徴とする光半導体装置。 Thin and thin than the insulative flat plate provided on one side of the through holes are formed insulating flat plate, the light is die-bonded by die bonding member having at least a resin on a thin plate of the cavity bottom surface utilizing the through hole there an optical semiconductor device having a semiconductor element, wherein the lead electrode for electrically connecting the optical semiconductor element provided on the insulating flat plate and the outside, and a translucent resin that covers the optical semiconductor element in the cavity Te, the thin plate constituting the cavity bottom is a metal, the surface optical semiconductor device, characterized in that at least a resin or a porous material.
  2. 前記多孔質材料はセラミックである請求項1に記載の光半導体装置。 The porous material is an optical semiconductor device according to claim 1, wherein the ceramic.
  3. 前記薄板を構成する金属が樹脂によって封止され前記リード電極と電気的に独立している請求項1または2に記載の光半導体装置。 The optical semiconductor device according to claim 1 or 2 metal constituting the sheet are sealed independently the so lead electrode electrically sealed by a resin.
  4. 内部に光半導体素子が配置された光半導体装置の形成方法において、(a)絶縁性平板に貫通穴を形成する工程と、(b)接着シートを介して絶縁性平板と金属とを添設する工程と、(c)前記絶縁性平板上に少なくとも一対のリード電極を形成する工程と、(d)前記貫通穴を利用したキャビティ底面の接着シート上に光半導体素子を少なくとも樹脂を有するダイボンド部材によってダイボンドする工程と、(e)前記光半導体素子の各電極と前記絶縁性平板に形成されたリード電極とを導電性材料でそれぞれ電気的に接続する工程と(f)少なくとも前記光半導体素子を透光性樹脂で被覆する工程とを有することを特徴とする光半導体装置の形成方法。 In the method of forming an optical semiconductor device optical semiconductor element disposed therein and additionally provided a step, an insulating flat plate and the metal via (b) the adhesive sheet for forming the through hole in the (a) insulating flat plate a step, by die bonding member having at least a step of forming a pair of lead electrodes, at least a resin and an optical semiconductor device in (d) of the adhesive sheet of the cavity bottom surface using a through hole (c) the insulative flat plate a step of die bonding, the (e) the light and the electrodes of the semiconductor element and the and the step of connecting the leads are formed in the insulating plate electrode respectively electrically with a conductive material (f) at least the optical semiconductor element Toru method of forming an optical semiconductor device characterized by a step of coating a light resin.
  5. 内部に光半導体素子が配置された光半導体装置の形成方法において、(a)接着シートを有する絶縁性平板に貫通穴を形成する工程と、(b)前記接着シートを介して絶縁性平板と、少なくとも絶縁性平板と対向する表面にセラミックを有する金属層とを添設する工程と、(c)前記絶縁性平板に少なくとも一対のリード電極を形成する工程と、(d)前記貫通穴を利用したキャビティ底面のセラミック上に光半導体素子を少なくとも樹脂を有するダイボンド部材によってダイボンドする工程と、(e)前記光半導体素子の各電極と、前記絶縁性平板に形成されたリード電極とを導電性材料でそれぞれ電気的に接続する工程と(f)少なくとも前記光半導体素子を透光性樹脂で被覆する工程とを有することを特徴とする光半導体装置の形成方 In the method of forming an optical semiconductor device optical semiconductor element disposed therein, forming a through hole in the insulating flat plate having (a) an adhesive sheet, and insulating flat plate through the (b) the adhesive sheet, a step of additionally provided with a metal layer having a ceramic on at least an insulating flat plate and the opposite surfaces, forming at least a pair of lead electrodes (c) the insulating plates to use (d) is the through-hole a step of die-bonding the die bonding member having at least a resin an optical semiconductor element on a ceramic cavity bottom, (e) and the electrodes of the optical semiconductor element, a lead electrode of a conductive material formed on the insulating flat plate each formation side of the optical semiconductor device characterized by a step of coating in the step and (f) a light resin permeable at least the optical semiconductor element electrically connected .
JP2323699A 1999-01-29 1999-01-29 The optical semiconductor device and method of forming Expired - Fee Related JP4279388B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2323699A JP4279388B2 (en) 1999-01-29 1999-01-29 The optical semiconductor device and method of forming

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2323699A JP4279388B2 (en) 1999-01-29 1999-01-29 The optical semiconductor device and method of forming

Publications (2)

Publication Number Publication Date
JP2000223752A JP2000223752A (en) 2000-08-11
JP4279388B2 true JP4279388B2 (en) 2009-06-17

Family

ID=12104987

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2323699A Expired - Fee Related JP4279388B2 (en) 1999-01-29 1999-01-29 The optical semiconductor device and method of forming

Country Status (1)

Country Link
JP (1) JP4279388B2 (en)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY145695A (en) * 2001-01-24 2012-03-30 Nichia Corp Light emitting diode, optical semiconductor device, epoxy resin composition suited for optical semiconductor device, and method for manufacturing the same
JP2002270901A (en) * 2001-03-12 2002-09-20 Citizen Electronics Co Ltd Light emitting diode and its manufacturing method
DE10308890A1 (en) * 2003-02-28 2004-09-09 Opto Tech Corporation A housing structure with a substrate, two electrodes, and a transparent insulated carrier with a depression useful for light emitting diodes
JP4613489B2 (en) * 2003-12-08 2011-01-19 ソニー株式会社 Element array method and a display device
JP4516337B2 (en) * 2004-03-25 2010-08-04 シチズン電子株式会社 Semiconductor light-emitting device
JP3956965B2 (en) 2004-09-07 2007-08-08 日立エーアイシー株式会社 Chip-type light emitting device and the wiring board therefor
JP2006173182A (en) * 2004-12-13 2006-06-29 Kyocera Corp Light emitting device and package for storing same
US7821023B2 (en) 2005-01-10 2010-10-26 Cree, Inc. Solid state lighting component
US9793247B2 (en) 2005-01-10 2017-10-17 Cree, Inc. Solid state lighting component
US8669572B2 (en) 2005-06-10 2014-03-11 Cree, Inc. Power lamp package
JP2007110060A (en) * 2005-09-15 2007-04-26 Nichia Chem Ind Ltd Light emitting device
JP2007150233A (en) * 2005-11-02 2007-06-14 Trion:Kk Color-temperature controllable light-emitting device
JP4744335B2 (en) * 2006-01-30 2011-08-10 京セラ株式会社 A light-emitting device and a lighting device
US7675145B2 (en) 2006-03-28 2010-03-09 Cree Hong Kong Limited Apparatus, system and method for use in mounting electronic elements
US8748915B2 (en) 2006-04-24 2014-06-10 Cree Hong Kong Limited Emitter package with angled or vertical LED
US7635915B2 (en) 2006-04-26 2009-12-22 Cree Hong Kong Limited Apparatus and method for use in mounting electronic elements
US8735920B2 (en) 2006-07-31 2014-05-27 Cree, Inc. Light emitting diode package with optical element
US8367945B2 (en) 2006-08-16 2013-02-05 Cree Huizhou Opto Limited Apparatus, system and method for use in mounting electronic elements
WO2008059650A1 (en) * 2006-11-14 2008-05-22 Harison Toshiba Lighting Corp. Light emitting device, its manufacturing method and its mounted substrate
JP2008300773A (en) * 2007-06-04 2008-12-11 Daisho Denshi:Kk Manufacturing method of light emitting element mounting wiring board and light emitting element mounting wiring board
JP5167977B2 (en) * 2007-09-06 2013-03-21 日亜化学工業株式会社 Semiconductor device
US9070850B2 (en) 2007-10-31 2015-06-30 Cree, Inc. Light emitting diode package and method for fabricating same
USD615504S1 (en) 2007-10-31 2010-05-11 Cree, Inc. Emitter package
US8866169B2 (en) 2007-10-31 2014-10-21 Cree, Inc. LED package with increased feature sizes
US8455882B2 (en) 2010-10-15 2013-06-04 Cree, Inc. High efficiency LEDs
USD633631S1 (en) 2007-12-14 2011-03-01 Cree Hong Kong Limited Light source of light emitting diode
USD634863S1 (en) 2008-01-10 2011-03-22 Cree Hong Kong Limited Light source of light emitting diode
JP2009182091A (en) * 2008-01-30 2009-08-13 C I Kasei Co Ltd Light emitting device
JP5121544B2 (en) * 2008-04-11 2013-01-16 スタンレー電気株式会社 Semiconductor light-emitting device
US8049230B2 (en) 2008-05-16 2011-11-01 Cree Huizhou Opto Limited Apparatus and system for miniature surface mount devices
US8791471B2 (en) 2008-11-07 2014-07-29 Cree Hong Kong Limited Multi-chip light emitting diode modules
US8368112B2 (en) 2009-01-14 2013-02-05 Cree Huizhou Opto Limited Aligned multiple emitter package
US8415692B2 (en) 2009-07-06 2013-04-09 Cree, Inc. LED packages with scattering particle regions
JP2009260395A (en) * 2009-08-07 2009-11-05 Hitachi Aic Inc Wiring substrate and method for manufacturing the same
US8598809B2 (en) 2009-08-19 2013-12-03 Cree, Inc. White light color changing solid state lighting and methods
US9012938B2 (en) 2010-04-09 2015-04-21 Cree, Inc. High reflective substrate of light emitting devices with improved light output
US8564004B2 (en) 2011-11-29 2013-10-22 Cree, Inc. Complex primary optics with intermediate elements
USD735683S1 (en) 2013-05-03 2015-08-04 Cree, Inc. LED package
US9461024B2 (en) 2013-08-01 2016-10-04 Cree, Inc. Light emitter devices and methods for light emitting diode (LED) chips
USD758976S1 (en) 2013-08-08 2016-06-14 Cree, Inc. LED package
US9601670B2 (en) 2014-07-11 2017-03-21 Cree, Inc. Method to form primary optic with variable shapes and/or geometries without a substrate
USD790486S1 (en) 2014-09-30 2017-06-27 Cree, Inc. LED package with truncated encapsulant
USD777122S1 (en) 2015-02-27 2017-01-24 Cree, Inc. LED package
USD783547S1 (en) 2015-06-04 2017-04-11 Cree, Inc. LED package

Also Published As

Publication number Publication date
JP2000223752A (en) 2000-08-11

Similar Documents

Publication Publication Date Title
JP5175488B2 (en) led package having a multilayer reflective surface structure
JP4961887B2 (en) Solid state device
US8608349B2 (en) Power surface mount light emitting die package
KR100586944B1 (en) High power light emitting diode package and method of producing the same
CN1306626C (en) Semiconductor luminescent device
KR100693969B1 (en) Solid element device and method for manufacture thereof
US8530915B2 (en) Power surface mount light emitting die package
CN100442546C (en) Luminance element and making method thereof and lead frame for making said element
CN100420043C (en) Optoelectronic component and a module based thereon
KR101010230B1 (en) Light-emitting device
US8378374B2 (en) Semiconductor light emitting device packages including submounts
EP1537603B1 (en) Power surface mount light emitting die package
CN1317776C (en) Light-emitting diode lamp
EP2218116B1 (en) Slim led package
US9496473B2 (en) Semiconductor light emitting device
JP4747726B2 (en) The light-emitting device
US7833811B2 (en) Side-emitting LED package and method of manufacturing the same
JP4359195B2 (en) The semiconductor light emitting device and a manufacturing method and a semiconductor light-emitting unit
US20110169037A1 (en) Wiring Board for Light-Emitting Element
US7391153B2 (en) Light emitting device provided with a submount assembly for improved thermal dissipation
EP1670073A1 (en) Light emitting device
US8035121B2 (en) Package for light emitting device having a lens spaced from a light emitting device module
JP4791381B2 (en) Method of manufacturing a light emitting device
JP4122784B2 (en) The light-emitting device
US6998777B2 (en) Light emitting diode and light emitting diode array

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051212

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080909

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080909

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081110

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090217

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090312

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120319

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130319

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130319

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140319

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees