JP4750080B2 - 配線基板 - Google Patents

配線基板 Download PDF

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Publication number
JP4750080B2
JP4750080B2 JP2007165464A JP2007165464A JP4750080B2 JP 4750080 B2 JP4750080 B2 JP 4750080B2 JP 2007165464 A JP2007165464 A JP 2007165464A JP 2007165464 A JP2007165464 A JP 2007165464A JP 4750080 B2 JP4750080 B2 JP 4750080B2
Authority
JP
Japan
Prior art keywords
film
insulating film
wiring pattern
semiconductor substrate
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007165464A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009004648A5 (https=
JP2009004648A (ja
Inventor
啓 村山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007165464A priority Critical patent/JP4750080B2/ja
Priority to EP08158268A priority patent/EP2006911B1/en
Priority to US12/142,039 priority patent/US7911048B2/en
Publication of JP2009004648A publication Critical patent/JP2009004648A/ja
Publication of JP2009004648A5 publication Critical patent/JP2009004648A5/ja
Application granted granted Critical
Publication of JP4750080B2 publication Critical patent/JP4750080B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2007165464A 2007-06-22 2007-06-22 配線基板 Expired - Fee Related JP4750080B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007165464A JP4750080B2 (ja) 2007-06-22 2007-06-22 配線基板
EP08158268A EP2006911B1 (en) 2007-06-22 2008-06-13 Wiring substrate
US12/142,039 US7911048B2 (en) 2007-06-22 2008-06-19 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007165464A JP4750080B2 (ja) 2007-06-22 2007-06-22 配線基板

Publications (3)

Publication Number Publication Date
JP2009004648A JP2009004648A (ja) 2009-01-08
JP2009004648A5 JP2009004648A5 (https=) 2010-05-13
JP4750080B2 true JP4750080B2 (ja) 2011-08-17

Family

ID=39816765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007165464A Expired - Fee Related JP4750080B2 (ja) 2007-06-22 2007-06-22 配線基板

Country Status (3)

Country Link
US (1) US7911048B2 (https=)
EP (1) EP2006911B1 (https=)
JP (1) JP4750080B2 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100990943B1 (ko) 2008-11-07 2010-11-01 주식회사 하이닉스반도체 반도체 패키지
US8847387B2 (en) * 2009-10-29 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Robust joint structure for flip-chip bonding
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
JP2012156327A (ja) 2011-01-26 2012-08-16 Elpida Memory Inc 半導体装置、及び積層型半導体装置
KR102111474B1 (ko) 2013-11-20 2020-06-08 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
JP2019054199A (ja) * 2017-09-19 2019-04-04 東芝メモリ株式会社 半導体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000077477A (ja) * 1998-09-02 2000-03-14 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法並びにこれに用いる金属基板
US6265312B1 (en) * 1999-08-02 2001-07-24 Stmicroelectronics, Inc. Method for depositing an integrated circuit tungsten film stack that includes a post-nucleation pump down step
US6521970B1 (en) * 2000-09-01 2003-02-18 National Semiconductor Corporation Chip scale package with compliant leads
JP2003198068A (ja) * 2001-12-27 2003-07-11 Nec Corp プリント基板、半導体装置、およびプリント基板と部品との電気的接続構造
US7265045B2 (en) * 2002-10-24 2007-09-04 Megica Corporation Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
US6806570B1 (en) * 2002-10-24 2004-10-19 Megic Corporation Thermal compliant semiconductor chip wiring structure for chip scale packaging
JP4492233B2 (ja) * 2003-11-27 2010-06-30 株式会社デンソー 半導体チップの実装構造および半導体チップの実装方法
JP4343044B2 (ja) * 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
JP4889974B2 (ja) * 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
JP2007165464A (ja) 2005-12-12 2007-06-28 Stanley Electric Co Ltd 半導体光学装置

Also Published As

Publication number Publication date
EP2006911B1 (en) 2012-11-28
JP2009004648A (ja) 2009-01-08
US7911048B2 (en) 2011-03-22
EP2006911A3 (en) 2011-08-03
EP2006911A2 (en) 2008-12-24
US20080315367A1 (en) 2008-12-25

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