JP4740590B2 - 層転写方法 - Google Patents
層転写方法 Download PDFInfo
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- JP4740590B2 JP4740590B2 JP2004520666A JP2004520666A JP4740590B2 JP 4740590 B2 JP4740590 B2 JP 4740590B2 JP 2004520666 A JP2004520666 A JP 2004520666A JP 2004520666 A JP2004520666 A JP 2004520666A JP 4740590 B2 JP4740590 B2 JP 4740590B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Recrystallisation Techniques (AREA)
- Laminated Bodies (AREA)
- Medicinal Preparation (AREA)
- Detergent Compositions (AREA)
- Weting (AREA)
- Lining Or Joining Of Plastics Or The Like (AREA)
- Element Separation (AREA)
- Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
- Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
- Ropes Or Cables (AREA)
- Separation By Low-Temperature Treatments (AREA)
- Prostheses (AREA)
- Electroluminescent Light Sources (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
ソース基板の「前面」と呼ばれる面の一つ、もしくは、サポート基板の前面、または、上記面の両方に補助的な材料を堆積するステップと、
それぞれの前面が互いに対向する上記ソース基板と上記サポート基板を互いに接触させるステップと、
機械的に発生する応力を加えることにより、転写対象の上記層を弱いゾーンに沿ってソース基板の残りの部分から取り外すステップと、
を少なくとも含む方法によって達成される。
・上記凹部は、当該凹部が形成された基板の後面と連通する。
・凹部は、当該凹部が形成された基板の前面へ通じる環状溝の形をなす。
・凹部は、ウェットエッチング、ドライエッチング、または、ソー(saw)もしくはレーザービームを使用する機械加工によって生成可能である。
・弱いゾーンは、核種注入によって形成され、または、多孔性層もしくは剥離可能な結合界面によって形成される。
・ソース基板に設けられた凹部は、核種を注入するステップの前に生成される。
・転写対象の層は、半導体材料により構成される。
・補助的な材料は、接着剤または接着材料である。
Claims (10)
- エレクトロニクス、オプティクス、または、オプトエレクトロニクスの分野におけるアプリケーション用の複合基板を製造するためソース基板(4)からサポート基板(5)へ材料の層(41)を転写する方法であって、
前記ソース基板(4)が、転写対象の前記材料の層(41)と前記ソース基板の残りの部分(42)との間に挿入された弱いゾーン(43)を有し、
前記ソース基板(4)の「前面」と呼ばれる面(44)の一つ、もしくは、前記サポート基板(5)の前面(56)、または、前記面の両方に補助的な材料(6)を堆積するステップと、
それぞれの前面(44,54)が、互いに対向する前記ソース基板(4)と前記サポート基板(5)を互いに接触させるステップと、
機械的に発生する応力を加えることにより、前記弱いゾーンに沿って、転写対象の前記層(41)を前記ソース基板(4)の前記残りの部分(42)から取り外すステップと、を少なくとも含み、
前記材料(6)を堆積するステップの前に、余分な補助的な材料(6)を収容する少なくとも一つの凹部(46,47)が前記ソース基板(4)に形成され、前記凹部は前記ソース基板(4)の前記前面(44)に通じ、
前記層(41)を取り外すステップにおいて、前記弱いゾーン(43)および前記凹部(46)に沿って前記層(41)を取り外す、方法。 - 前記凹部(46)の深さは、前記弱いゾーン(43)の位置する前記ソース基板(4)の深さに少なくとも等しい、請求項1に記載の方法。
- 前記凹部(46,47;56,57)が、ウェットエッチングまたはドライエッチングによって生成される、請求項1または請求項2のいずれかに記載の方法。
- 前記凹部(46,47;56,57)が、ソーもしくはレーザービームを使用する機械加工によって生成される、請求項1または請求項2のいずれかに記載の方法。
- 前記弱いゾーン(43)が、核種注入によって形成される、請求項1から4のいずれかに記載の方法。
- 前記弱いゾーン(43)が、多孔性層によって形成される、請求項1から4のいずれかに記載の方法。
- 前記弱いゾーン(43)が、剥離可能な結合界面によって形成される、請求項1から4のいずれかに記載の方法。
- 前記ソース基板(4)に設けられた凹部(46)が、前記核種を注入するステップの前に生成される、請求項4および請求項5に記載の方法。
- 前記転写対象の層(41)が、半導体材料により構成される、請求項1から8のいずれかに記載の方法。
- 前記補助的な材料(6)が、接着剤または接着材料である、請求項1から9のいずれかに記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR02/09018 | 2002-07-17 | ||
FR0209018A FR2842647B1 (fr) | 2002-07-17 | 2002-07-17 | Procede de transfert de couche |
PCT/EP2003/007853 WO2004008526A1 (en) | 2002-07-17 | 2003-07-16 | A layer transfer method |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005533374A JP2005533374A (ja) | 2005-11-04 |
JP4740590B2 true JP4740590B2 (ja) | 2011-08-03 |
Family
ID=29797483
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004520666A Expired - Fee Related JP4740590B2 (ja) | 2002-07-17 | 2003-07-16 | 層転写方法 |
Country Status (10)
Country | Link |
---|---|
US (1) | US6913971B2 (ja) |
EP (1) | EP1543553B1 (ja) |
JP (1) | JP4740590B2 (ja) |
AT (1) | ATE498201T1 (ja) |
AU (1) | AU2003250992A1 (ja) |
DE (1) | DE60335995D1 (ja) |
FR (1) | FR2842647B1 (ja) |
MY (1) | MY135493A (ja) |
TW (1) | TWI286816B (ja) |
WO (1) | WO2004008526A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1571705A3 (fr) * | 2004-03-01 | 2006-01-04 | S.O.I.Tec Silicon on Insulator Technologies | Réalisation d'une entité en matériau semiconducteur sur substrat |
EP1978554A3 (en) * | 2007-04-06 | 2011-10-12 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor substrate comprising implantation and separation steps |
FR2939962B1 (fr) * | 2008-12-15 | 2011-03-18 | Soitec Silicon On Insulator | Procede d'amincissement d'une structure. |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
US9847243B2 (en) | 2009-08-27 | 2017-12-19 | Corning Incorporated | Debonding a glass substrate from carrier using ultrasonic wave |
US8932910B2 (en) * | 2010-05-20 | 2015-01-13 | Ev Group E. Thallner Gmbh | Method for producing chip stacks, and a carrier for carrying out the method |
FR2961948B1 (fr) * | 2010-06-23 | 2012-08-03 | Soitec Silicon On Insulator | Procede de traitement d'une piece en materiau compose |
JP5939881B2 (ja) * | 2012-05-02 | 2016-06-22 | 株式会社ディスコ | 研削方法 |
US9481566B2 (en) | 2012-07-31 | 2016-11-01 | Soitec | Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices |
US9171809B2 (en) * | 2013-03-05 | 2015-10-27 | Flextronics Ap, Llc | Escape routes |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61208842A (ja) * | 1985-03-14 | 1986-09-17 | Nippon Telegr & Teleph Corp <Ntt> | 半導体ウエハ支持基板 |
JPH0521480A (ja) * | 1991-07-12 | 1993-01-29 | Dainippon Printing Co Ltd | リードフレーム |
JPH0737768A (ja) * | 1992-11-26 | 1995-02-07 | Sumitomo Electric Ind Ltd | 半導体ウェハの補強方法及び補強された半導体ウェハ |
JPH07335817A (ja) * | 1994-06-10 | 1995-12-22 | Dainippon Printing Co Ltd | リードフレーム部材 |
JPH0963912A (ja) * | 1995-08-18 | 1997-03-07 | Hoya Corp | 貼り合わせ基板製造方法 |
JPH09232199A (ja) * | 1996-02-27 | 1997-09-05 | Victor Co Of Japan Ltd | 薄膜プロセス用複合ウェハ基板 |
JP2001196566A (ja) * | 2000-01-07 | 2001-07-19 | Sony Corp | 半導体基板およびその製造方法 |
JP2001230274A (ja) * | 2000-02-14 | 2001-08-24 | Fujitsu Ltd | 実装基板及び実装方法 |
JP2001296650A (ja) * | 2000-04-17 | 2001-10-26 | Nec Corp | レチクル |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
SG67458A1 (en) * | 1996-12-18 | 1999-09-21 | Canon Kk | Process for producing semiconductor article |
US6534380B1 (en) * | 1997-07-18 | 2003-03-18 | Denso Corporation | Semiconductor substrate and method of manufacturing the same |
US6406336B1 (en) * | 1998-01-20 | 2002-06-18 | Fci Americas Technology, Inc. | Contact with anti-skiving feature |
US6054370A (en) * | 1998-06-30 | 2000-04-25 | Intel Corporation | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer |
FR2781925B1 (fr) * | 1998-07-30 | 2001-11-23 | Commissariat Energie Atomique | Transfert selectif d'elements d'un support vers un autre support |
JP2000223683A (ja) * | 1999-02-02 | 2000-08-11 | Canon Inc | 複合部材及びその分離方法、貼り合わせ基板及びその分離方法、移設層の移設方法、並びにsoi基板の製造方法 |
US6236103B1 (en) * | 1999-03-31 | 2001-05-22 | International Business Machines Corp. | Integrated high-performance decoupling capacitor and heat sink |
US6406636B1 (en) * | 1999-06-02 | 2002-06-18 | Megasense, Inc. | Methods for wafer to wafer bonding using microstructures |
JP2001007362A (ja) * | 1999-06-17 | 2001-01-12 | Canon Inc | 半導体基材および太陽電池の製造方法 |
FR2811807B1 (fr) * | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
EP1364398A4 (en) * | 2001-01-02 | 2011-11-30 | Draper Lab Charles S | METHOD FOR MICROUSING STRUCTURES USING SILICON MATERIAL ON INSULATION |
FR2837620B1 (fr) * | 2002-03-25 | 2005-04-29 | Commissariat Energie Atomique | Procede de transfert d'elements de substrat a substrat |
-
2002
- 2002-07-17 FR FR0209018A patent/FR2842647B1/fr not_active Expired - Fee Related
-
2003
- 2003-07-09 US US10/616,586 patent/US6913971B2/en not_active Expired - Lifetime
- 2003-07-16 AU AU2003250992A patent/AU2003250992A1/en not_active Abandoned
- 2003-07-16 JP JP2004520666A patent/JP4740590B2/ja not_active Expired - Fee Related
- 2003-07-16 AT AT03763890T patent/ATE498201T1/de not_active IP Right Cessation
- 2003-07-16 EP EP03763890A patent/EP1543553B1/en not_active Expired - Lifetime
- 2003-07-16 WO PCT/EP2003/007853 patent/WO2004008526A1/en active Application Filing
- 2003-07-16 DE DE60335995T patent/DE60335995D1/de not_active Expired - Lifetime
- 2003-07-16 TW TW092119343A patent/TWI286816B/zh not_active IP Right Cessation
- 2003-07-17 MY MYPI20032677A patent/MY135493A/en unknown
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61208842A (ja) * | 1985-03-14 | 1986-09-17 | Nippon Telegr & Teleph Corp <Ntt> | 半導体ウエハ支持基板 |
JPH0521480A (ja) * | 1991-07-12 | 1993-01-29 | Dainippon Printing Co Ltd | リードフレーム |
JPH0737768A (ja) * | 1992-11-26 | 1995-02-07 | Sumitomo Electric Ind Ltd | 半導体ウェハの補強方法及び補強された半導体ウェハ |
JPH07335817A (ja) * | 1994-06-10 | 1995-12-22 | Dainippon Printing Co Ltd | リードフレーム部材 |
JPH0963912A (ja) * | 1995-08-18 | 1997-03-07 | Hoya Corp | 貼り合わせ基板製造方法 |
JPH09232199A (ja) * | 1996-02-27 | 1997-09-05 | Victor Co Of Japan Ltd | 薄膜プロセス用複合ウェハ基板 |
JP2001196566A (ja) * | 2000-01-07 | 2001-07-19 | Sony Corp | 半導体基板およびその製造方法 |
JP2001230274A (ja) * | 2000-02-14 | 2001-08-24 | Fujitsu Ltd | 実装基板及び実装方法 |
JP2001296650A (ja) * | 2000-04-17 | 2001-10-26 | Nec Corp | レチクル |
Also Published As
Publication number | Publication date |
---|---|
EP1543553A1 (en) | 2005-06-22 |
MY135493A (en) | 2008-04-30 |
US20040082147A1 (en) | 2004-04-29 |
AU2003250992A1 (en) | 2004-02-02 |
AU2003250992A8 (en) | 2004-02-02 |
JP2005533374A (ja) | 2005-11-04 |
WO2004008526A1 (en) | 2004-01-22 |
FR2842647B1 (fr) | 2004-09-17 |
ATE498201T1 (de) | 2011-02-15 |
TW200416943A (en) | 2004-09-01 |
US6913971B2 (en) | 2005-07-05 |
DE60335995D1 (de) | 2011-03-24 |
FR2842647A1 (fr) | 2004-01-23 |
EP1543553B1 (en) | 2011-02-09 |
TWI286816B (en) | 2007-09-11 |
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