JP4730192B2 - 半導体回路設計方法 - Google Patents
半導体回路設計方法 Download PDFInfo
- Publication number
- JP4730192B2 JP4730192B2 JP2006127703A JP2006127703A JP4730192B2 JP 4730192 B2 JP4730192 B2 JP 4730192B2 JP 2006127703 A JP2006127703 A JP 2006127703A JP 2006127703 A JP2006127703 A JP 2006127703A JP 4730192 B2 JP4730192 B2 JP 4730192B2
- Authority
- JP
- Japan
- Prior art keywords
- module
- modules
- reconfigurable
- standard
- soc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000013461 design Methods 0.000 title claims description 49
- 238000000034 method Methods 0.000 title claims description 42
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000010410 layer Substances 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 13
- 230000006870 function Effects 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 3
- 230000008672 reprogramming Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 19
- 230000008569 process Effects 0.000 description 18
- 235000012431 wafers Nutrition 0.000 description 16
- 238000011161 development Methods 0.000 description 10
- 230000004075 alteration Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Landscapes
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
104 メモリモジュール
106 ロジックモジュール
108 データバス配置領域
200 カスタムSOC
300 SOC製品チップ
Claims (4)
- マルチプロジェクトウェーハ上に少なくとも1つの半導体回路を設計する半導体回路設計方法であって、
確認済みの機能を有する1つあるいはそれ以上の標準モジュールを供給するステップと、
マルチプロジェクトウェーハ上の回路に基づき、製品ウェーハ上の不必要な標準モジュールを除去するステップと、
1つの再構成可能なメモリユニットと複数の再構成可能なロジックユニットとを含む少なくとも1つの再構成可能なモジュールを、1つあるいはそれ以上の接続層を介して1つあるいはそれ以上の接続を行なうことで、プログラムするステップと、
前記標準モジュールを、あらかじめ決められた設計にしたがって、プログラムされた前記再構成可能なモジュールと接続するステップと、
前記製品ウェーハ上に残るべきモジュールを、要求された回路の基板が最小となるように再配置するステップと、を有し、
前記標準モジュールが、少なくとも1つのメモリモジュールと少なくとも1つの入力/出力モジュールを含み、
プログラム前の前記標準モジュールと前記再構成可能なモジュールに、少なくとも1つの金属配線層を形成し、前記少なくとも1つの金属配線層の形成後に、1つあるいはそれ以上の接続層にて前記プログラムと接続のステップが行なわれることを特徴とする半導体回路設計方法。 - 前記標準モジュールが、異なる設計のモジュールを含むことを特徴とする請求項1記載の半導体回路設計方法。
- 前記標準モジュールの全部または一部が利用されることを特徴とする請求項1記載の半導体回路設計方法。
- 前記接続層が、金属配線と層間接続を含むことを特徴とする請求項1記載の半導体回路設計方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/119,086 US7401302B2 (en) | 2004-04-29 | 2005-04-29 | System on chip development with reconfigurable multi-project wafer technology |
US11/119,086 | 2005-04-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006310869A JP2006310869A (ja) | 2006-11-09 |
JP4730192B2 true JP4730192B2 (ja) | 2011-07-20 |
Family
ID=37195497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006127703A Active JP4730192B2 (ja) | 2005-04-29 | 2006-05-01 | 半導体回路設計方法 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP4730192B2 (ja) |
CN (3) | CN100538881C (ja) |
TW (2) | TWI315610B (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130191572A1 (en) * | 2012-01-23 | 2013-07-25 | Qualcomm Incorporated | Transaction ordering to avoid bus deadlocks |
US10176855B2 (en) * | 2013-11-21 | 2019-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional (3-D) write assist scheme for memory cells |
US9275180B1 (en) * | 2014-07-14 | 2016-03-01 | Xilinx, Inc. | Programmable integrated circuit having different types of configuration memory |
KR102201566B1 (ko) * | 2017-08-18 | 2021-01-11 | 주식회사 엘지화학 | 맞춤형 bms 모듈 및 그 설계 방법 |
TWI661676B (zh) * | 2018-08-01 | 2019-06-01 | 新唐科技股份有限公司 | 可程式陣列邏輯 |
CN110364203B (zh) * | 2019-06-20 | 2021-01-05 | 中山大学 | 一种支撑存储内计算的存储系统及计算方法 |
US11088693B2 (en) * | 2019-07-08 | 2021-08-10 | Hossein Asadi | Configurable logic block for implementing a Boolean function |
WO2022032551A1 (en) | 2020-08-13 | 2022-02-17 | Yangtze Memory Technologies Co., Ltd. | Flash memory device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002289817A (ja) * | 2001-03-27 | 2002-10-04 | Toshiba Corp | 半導体集積回路装置及びその製造方法 |
WO2005086035A1 (en) * | 2004-02-27 | 2005-09-15 | Rapid Bridge Llc | Method and architecture for integrated circuit design and manufacture |
JP2007502014A (ja) * | 2003-07-31 | 2007-02-01 | アクテル・コーポレイシヨン | プログラマブルシステムオンチップ |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0695569B2 (ja) * | 1984-11-20 | 1994-11-24 | 富士通株式会社 | ゲ−トアレイlsi装置 |
US5200907A (en) * | 1990-04-16 | 1993-04-06 | Tran Dzung J | Transmission gate logic design method |
JPH04240768A (ja) * | 1991-01-25 | 1992-08-28 | Matsushita Electron Corp | 読み出し専用半導体記憶装置 |
JPH06224300A (ja) * | 1993-01-26 | 1994-08-12 | Hitachi Ltd | 半導体集積回路の設計方法および評価用半導体集積回路 |
JP3407975B2 (ja) * | 1994-05-20 | 2003-05-19 | 株式会社半導体エネルギー研究所 | 薄膜半導体集積回路 |
US6237132B1 (en) * | 1998-08-18 | 2001-05-22 | International Business Machines Corporation | Toggle based application specific core methodology |
-
2006
- 2006-04-28 TW TW095115248A patent/TWI315610B/zh not_active IP Right Cessation
- 2006-04-28 TW TW095115249A patent/TWI321841B/zh active
- 2006-04-28 CN CNB200610077245XA patent/CN100538881C/zh not_active Expired - Fee Related
- 2006-04-28 CN CN200810145354XA patent/CN101359908B/zh not_active Expired - Fee Related
- 2006-04-29 CN CNB200610078986XA patent/CN100508190C/zh active Active
- 2006-05-01 JP JP2006127703A patent/JP4730192B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002289817A (ja) * | 2001-03-27 | 2002-10-04 | Toshiba Corp | 半導体集積回路装置及びその製造方法 |
JP2007502014A (ja) * | 2003-07-31 | 2007-02-01 | アクテル・コーポレイシヨン | プログラマブルシステムオンチップ |
WO2005086035A1 (en) * | 2004-02-27 | 2005-09-15 | Rapid Bridge Llc | Method and architecture for integrated circuit design and manufacture |
Also Published As
Publication number | Publication date |
---|---|
CN100538881C (zh) | 2009-09-09 |
TWI321841B (en) | 2010-03-11 |
TW200723501A (en) | 2007-06-16 |
CN101359908B (zh) | 2010-08-18 |
TWI315610B (en) | 2009-10-01 |
JP2006310869A (ja) | 2006-11-09 |
CN101359908A (zh) | 2009-02-04 |
CN100508190C (zh) | 2009-07-01 |
CN1917082A (zh) | 2007-02-21 |
CN1855485A (zh) | 2006-11-01 |
TW200644426A (en) | 2006-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8261219B2 (en) | System on chip development with reconfigurable multi-project wafer technology | |
JP4730192B2 (ja) | 半導体回路設計方法 | |
US7770144B2 (en) | Modular array defined by standard cell logic | |
US9547736B2 (en) | Timing exact design conversions from FPGA to ASIC | |
US6747478B2 (en) | Field programmable gate array with convertibility to application specific integrated circuit | |
US8332794B2 (en) | Circuits and methods for programmable transistor array | |
US4866508A (en) | Integrated circuit packaging configuration for rapid customized design and unique test capability | |
US8716809B2 (en) | Hardened programmable devices | |
US6791355B2 (en) | Spare cell architecture for fixing design errors in manufactured integrated circuits | |
US5214655A (en) | Integrated circuit packaging configuration for rapid customized design and unique test capability | |
US7310758B1 (en) | Circuit for and method of implementing programmable logic devices | |
US7692309B2 (en) | Configuring structured ASIC fabric using two non-adjacent via layers | |
US7491579B2 (en) | Composable system-in-package integrated circuits and process of composing the same | |
US6745358B1 (en) | Enhanced fault coverage | |
JPH09246501A (ja) | 半導体集積回路およびそのレイアウト設計方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080327 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100524 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100823 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100826 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100908 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20101101 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110228 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20110307 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110322 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110404 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140428 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4730192 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |