TW200723501A - System on chip development with reconfigurable multi-project wafer technology - Google Patents

System on chip development with reconfigurable multi-project wafer technology

Info

Publication number
TW200723501A
TW200723501A TW095115249A TW95115249A TW200723501A TW 200723501 A TW200723501 A TW 200723501A TW 095115249 A TW095115249 A TW 095115249A TW 95115249 A TW95115249 A TW 95115249A TW 200723501 A TW200723501 A TW 200723501A
Authority
TW
Taiwan
Prior art keywords
project wafer
chip development
wafer technology
reconfigurable multi
standard modules
Prior art date
Application number
TW095115249A
Other languages
Chinese (zh)
Other versions
TWI321841B (en
Inventor
Kun-Lung Chen
Yung-Chin Hou
Shine-Chien Chung
Yu-Chun Wu
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/119,086 external-priority patent/US7401302B2/en
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW200723501A publication Critical patent/TW200723501A/en
Application granted granted Critical
Publication of TWI321841B publication Critical patent/TWI321841B/en

Links

Landscapes

  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.
TW095115249A 2005-04-29 2006-04-28 System on chip development with reconfigurable multi-project wafer technology TWI321841B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/119,086 US7401302B2 (en) 2004-04-29 2005-04-29 System on chip development with reconfigurable multi-project wafer technology

Publications (2)

Publication Number Publication Date
TW200723501A true TW200723501A (en) 2007-06-16
TWI321841B TWI321841B (en) 2010-03-11

Family

ID=37195497

Family Applications (2)

Application Number Title Priority Date Filing Date
TW095115249A TWI321841B (en) 2005-04-29 2006-04-28 System on chip development with reconfigurable multi-project wafer technology
TW095115248A TWI315610B (en) 2005-04-29 2006-04-28 Configurable logic and memory block, and programmable pass gate based configurable logic device

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW095115248A TWI315610B (en) 2005-04-29 2006-04-28 Configurable logic and memory block, and programmable pass gate based configurable logic device

Country Status (3)

Country Link
JP (1) JP4730192B2 (en)
CN (3) CN101359908B (en)
TW (2) TWI321841B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI489288B (en) * 2012-01-23 2015-06-21 高通公司 Transaction ordering to avoid bus deadlocks

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10176855B2 (en) * 2013-11-21 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional (3-D) write assist scheme for memory cells
US9275180B1 (en) * 2014-07-14 2016-03-01 Xilinx, Inc. Programmable integrated circuit having different types of configuration memory
KR102201566B1 (en) * 2017-08-18 2021-01-11 주식회사 엘지화학 Customized bms module and method for designing thereof
TWI661676B (en) * 2018-08-01 2019-06-01 新唐科技股份有限公司 Programmable array logic
CN110364203B (en) * 2019-06-20 2021-01-05 中山大学 Storage system supporting internal calculation of storage and calculation method
US11088693B2 (en) * 2019-07-08 2021-08-10 Hossein Asadi Configurable logic block for implementing a Boolean function
CN112106139A (en) * 2020-08-13 2020-12-18 长江存储科技有限责任公司 Flash memory device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0695569B2 (en) * 1984-11-20 1994-11-24 富士通株式会社 Gate array LSI device
US5200907A (en) * 1990-04-16 1993-04-06 Tran Dzung J Transmission gate logic design method
JPH04240768A (en) * 1991-01-25 1992-08-28 Matsushita Electron Corp Read-only semiconductor memory device
JPH06224300A (en) * 1993-01-26 1994-08-12 Hitachi Ltd Designing method for semiconductor integrated circuit and semiconductor integrated circuit for evaluation
JP3407975B2 (en) * 1994-05-20 2003-05-19 株式会社半導体エネルギー研究所 Thin film semiconductor integrated circuit
US6237132B1 (en) * 1998-08-18 2001-05-22 International Business Machines Corporation Toggle based application specific core methodology
JP2002289817A (en) * 2001-03-27 2002-10-04 Toshiba Corp Semiconductor integrated circuit device and its manufacturing method
US7170315B2 (en) * 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
US7032191B2 (en) * 2004-02-27 2006-04-18 Rapid Bridge Llc Method and architecture for integrated circuit design and manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI489288B (en) * 2012-01-23 2015-06-21 高通公司 Transaction ordering to avoid bus deadlocks

Also Published As

Publication number Publication date
TWI315610B (en) 2009-10-01
CN100538881C (en) 2009-09-09
TW200644426A (en) 2006-12-16
CN101359908A (en) 2009-02-04
TWI321841B (en) 2010-03-11
CN100508190C (en) 2009-07-01
JP4730192B2 (en) 2011-07-20
CN1917082A (en) 2007-02-21
JP2006310869A (en) 2006-11-09
CN101359908B (en) 2010-08-18
CN1855485A (en) 2006-11-01

Similar Documents

Publication Publication Date Title
TW200723501A (en) System on chip development with reconfigurable multi-project wafer technology
CN103268380B (en) A kind of method for designing of the analog integrated circuit layout improving layout efficiency
TW200717002A (en) Electronic device having and interface supported testing mode
WO2007149495A3 (en) Program binding system, method and software for a resilient integrated circuit architecture
FI20030292A0 (en) Method for manufacturing an electronic module and an electronic module
TW200614900A (en) A substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same
TW200951359A (en) LED lamp module and its fabricating method
WO2010053821A3 (en) Technique for interconnecting integrated circuits
SG144030A1 (en) Method and apparatus for providing void structures
US9183339B1 (en) System and method for preparing partially reconfigurable circuit designs
TW200745874A (en) Computer and main circuit board thereof
WO2009158551A3 (en) Integrated circuit with ribtan interconnects
WO2010011448A3 (en) Predictive modeling of interconnect modules for advanced on-chip interconnect technology
CN102637226A (en) PCB (printed circuit board) packaging architecture method
TW201130112A (en) Semiconductor integrated circuit
TW200721438A (en) Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device
CN103915407A (en) Configurable circuit and mesh structure for integrated circuit
CN102891114B (en) Manufacturing method of chips of up-and-down stacked system-on-chip
CN104576440B (en) The method of technical module quantity and robot speed in configuration coating developing machine
CN103699706A (en) Power supply PCB (printed circuit board) wiring modularization system and method
TW200727328A (en) Method of optimizing layout of semiconductor device, manufacturing method of photomask, and manufacturing method and program of semiconductor device
CN102193898B (en) CPU core unlocking device applied to computer system
US7491579B2 (en) Composable system-in-package integrated circuits and process of composing the same
CN104992003B (en) Simulation design method of switching power supply
ATE325512T1 (en) AVOIDING TRANSCODING OR ABSORPTION DURING PAYLOAD CODING CHANGES IN EXISTING CONNECTIONS