CN102891114B - Manufacturing method of chips of up-and-down stacked system-on-chip - Google Patents
Manufacturing method of chips of up-and-down stacked system-on-chip Download PDFInfo
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- CN102891114B CN102891114B CN201210410099.3A CN201210410099A CN102891114B CN 102891114 B CN102891114 B CN 102891114B CN 201210410099 A CN201210410099 A CN 201210410099A CN 102891114 B CN102891114 B CN 102891114B
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Abstract
The invention discloses a manufacturing method of chips of an up-and-down stacked system-on-chip. The manufacturing method comprises the following steps of: implementing a circuit unit which can reduce the area along with the reduction in size of a manufacturing process on a first chip, and connecting with a standard system bus of a system microcontroller on the first chip; implementing a circuit unit which can not reduce the area along with the reduction in the size of the manufacturing process on a second chip, and connecting with a standard system bus of a system microcontroller on the second chip; and performing up-and-down connection by taking the standard system bus of the system microcontroller on the first chip and the standard system bus of the system microcontroller on the second chip as interconnection pins to obtain the chips of the system-on-chip. The manufacturing method disclosed by the invention is based on a chip stacking technology, and the different circuit units in the system-on-chip are implemented on the different process chips, so that the cost of the chips of the digital-analog hybrid system-on-chip can be optimized.
Description
Technical field
The present invention relates to chip-stacked technical field, particularly relate to a kind of manufacture method of on-chip system chip of stacked on top.
Background technology
Tradition numerical model analysis on-chip system chip; as shown in Figure 2; chip comprises usually clock module on sheet, central processing unit, graphic process unit, embedded non-volatile memory, static data memory SRAM, analog peripheral, power management module, interrupt management module, externally input and output pin, standard system bus.Clock module, central processing unit, graphic process unit, embedded non-volatile memory, static data memory SRAM on sheet, analog peripheral, power management module, interrupt management module, externally input and output pin are all connected with standard system bus.Wherein, digital logic unit area can reduce along with process node and reduce, but because the requirement simulation of performance and input-output unit can not reduce along with process node and reduce, if a kind of process manufacture of such on-chip system chip, such as use large scale process node, as 130 nanometers and above technique, the area of every chips will be very large, the chip amount that each like this wafer can cut out is just relatively less, thus the cost of every chips would not reach minimum.Otherwise, if use small size process node, as 90 nanometers and following technique.Although, the area of every chips can comparatively before the area of chip much little, but due to analog circuit and imput output circuit area not scaled, so the cost of produced every chips does not still reach optimization in expensive advanced technologies size.
Summary of the invention
Instant invention overcomes the area of digital-to-analog circuit in traditional on-chip system chip because simultaneously can not reduce along with process node and reduce, cause the cost of every chips can not optimized defect, propose a kind of manufacture method of on-chip system chip of stacked on top.The present invention is based on chip-stacked technology; originally the digital logic unit in the SOC (system on a chip) realized on same chips and analog circuit are separated; area constantly can be reduced along with process and the unit of scaled down realizes on the small size processing chip of advanced person; area constantly can not be reduced along with process and the circuit realiration of scaled down on the complete and cheap large scale processing chip of depreciation, thus make the cost of numerical model analysis on-chip system chip reach optimization.
The present invention proposes a kind of manufacture method of on-chip system chip of stacked on top, it is characterized in that, comprising:
Step one: area can be reduced with manufacturing process size and the circuit unit that reduces realize on the first chip, be connected with system microcontroller standard system bus on the first be arranged on described first chip;
Step 2: area can not be reduced with manufacturing process size and the circuit unit that reduces realize on the second chip, be connected with the second SOC (system on a chip) microcontroller standard system bus be arranged on described second chip;
Step 3: by system microcontroller standard system bus on the first of described first chip being connected up and down as interconnect pin with the second SOC (system on a chip) microcontroller standard system bus of the second chip, obtain on-chip system chip.
Wherein, described area can reduce with manufacturing process size and the circuit unit that reduces comprise: the digital peripherals module that static data memory, embedded non-volatile memory, central processing unit, graphic process unit, not external with on-chip system chip input and output pin are connected.
Wherein, described area can not reduce with manufacturing process size and the circuit unit that reduces comprise: clock module on analog peripheral, power management module, sheet, on-chip system chip external input and output pin, the digital peripherals module, the interrupt management module that are connected with the external input and output pin of described on-chip system chip.
Wherein, on described first, system microcontroller standard system bus and the second SOC (system on a chip) microcontroller standard system bus are the microcontroller standard system bus based on different microcontroller core, comprise based on the AMBA microcontroller standard system bus of ARM kernel, the microcontroller standard system bus based on 8051 kernels, the OCP microcontroller standard system bus based on MIPS kernel.
Wherein, in described step 3, described interconnect pin adopts wirebond interconnections line or silicon through hole connection interconnection line to connect up and down.
Wherein, comprise further: described on-chip system chip is connected by the chip stacked on top of more than three or three; The chip of described more than three or three is connected as interconnect pin up and down by SOC (system on a chip) microcontroller standard system bus.
All modules on first chip of the present invention can reduce along with process and reduce, thus whole first chip area also can diminish, and the number of chips that each wafer cuts also increases thereupon, make the cost of the first chip reach optimization.
Module on second chip of the present invention is due to the demand of systematic function, can not reduce along with process and reduce, so the cheap large technique selecting depreciation complete manufactures, the cost of light shield manufacture can be saved, thus make the cost of the second chip reach optimization.
The present invention's SOC (system on a chip) standard system bus interconnects up and down as pin can reduce the number of upper and lower interconnect pin.During the stacking connection of multiple chips, interface pin number is more, causes the area of each chip to increase like this.Meanwhile, interfaces interconnect number of pins increases also makes interconnection line between multiple chip (comprising: wirebond interconnections line is connected interconnection line etc. with silicon through hole) increase, and encapsulation overhead becomes large.The manufacture method of the on-chip system chip of the stacked on top that the present invention proposes is particularly outstanding to minimizing number of ports.Because the signal number in SOC (system on a chip) microcontroller standard system bus is fixing, die is not upper outside like this establishes how how complicated expanded function is, and the number of ports interconnected between the first chip and the second chip is changeless.
Accompanying drawing explanation
Fig. 1 is the flow chart of the on-chip system chip manufacture method of stacked on top of the present invention.
Fig. 2 is traditional on-chip system chip Organization Chart.
Fig. 3 is the schematic diagram of the on-chip system chip of stacked on top of the present invention.
Fig. 4 is the schematic diagram of the on-chip system chip of stacked on top of the present invention.Embodiment
Below in conjunction with drawings and Examples, specific embodiments of the present invention are further described in detail, but should not limit the scope of the invention with this.
As Figure 1-4, 1-first chip, 11-static data memory, 12-embedded non-volatile memory, 13-central processing unit, 14-graphic process unit, the digital peripherals module that not external with the on-chip system chip input and output pin of 15-is connected, microcontroller standard system bus on 16-first chip, 2-second chip, 21-analog peripheral, 22-power management module, clock module on 23-sheet, the external input and output pin of 24-on-chip system chip, the digital peripherals module that 25-is connected with the external input and output pin of on-chip system chip, 26-interrupt management module, microcontroller standard system bus on 27-second chip.
The manufacture method of the on-chip system chip of a kind of stacked on top of the present invention, as shown in Figure 1, comprising:
Step one: area can be reduced with manufacturing process size and the circuit unit that reduces realize on the first chip 1, be connected with system microcontroller standard system bus 16 on the first be arranged on the first chip 1.Wherein, area can reduce with manufacturing process size and the circuit unit that reduces comprise: digital peripherals module 15 that static data memory 11, embedded non-volatile memory 12, central processing unit 13, graphic process unit 14, not external with on-chip system chip input and output pin are connected etc.
Step 2: area can not be reduced with manufacturing process size and the circuit unit that reduces realize on the second chip 2, be connected with the second SOC (system on a chip) microcontroller standard system bus 27 be arranged on the second chip 2.Wherein, area can not reduce with manufacturing process size and the circuit unit that reduces comprise: clock module 23 on analog peripheral 21, power management module 22, sheet, on-chip system chip external input and output pin two 4, the digital peripherals module 25, interrupt management module 26 etc. that are connected with the external input and output pin two 4 of on-chip system chip.
Step 3: by system microcontroller standard system bus 16 on the first of the first chip 1 being connected up and down as interconnect pin with the second SOC (system on a chip) microcontroller standard system bus 27 of the second chip 2, obtain on-chip system chip.Wherein, on first, system microcontroller standard system bus 16 and the second SOC (system on a chip) microcontroller standard system bus 27 are the microcontroller standard system bus based on different microcontroller core, comprise based on the AMBA microcontroller standard system bus of ARM kernel, the microcontroller standard system bus based on 8051 kernels, the OCP microcontroller standard system bus based on MIPS kernel etc.Interconnect pin adopts wirebond interconnections line or silicon through hole connection interconnection line to connect up and down.
In the present invention, comprise further: on-chip system chip is connected by the chip stacked on top of more than three or three; The chip of more than three or three is connected as interconnect pin up and down by SOC (system on a chip) microcontroller standard system bus.
Embodiment 1:
As shown in Figure 3, area to be reduced with manufacturing process size and the circuit unit that reduces, comprise the digital peripherals module 15 that central processing unit 13, graphic process unit 14, static data memory 11, embedded non-volatile memory 12 and not external with on-chip system chip input and output pin are connected, by little manufacture technics (such as, 90nm and following little technique), above each circuit unit is realized on the first chip 1.Each unit is all connected with system microcontroller standard system bus 16 on the first of the first chip 1 above.
Then area can not to be reduced with manufacturing process size and the circuit unit that reduces, comprise clock module 23 on analog peripheral 21, power management module 22, sheet, interrupt management module 26, the digital peripherals module 25 be connected with input and output pin, externally input and output pin two 4, by large process manufacture, above unit is realized on the second chip 2.Each unit is all connected with the second SOC (system on a chip) microcontroller standard system bus 27 of the second chip 2 above.
First chip 1 superposes with the second chip about 2, the second SOC (system on a chip) microcontroller standard system bus 27 on the upper first of first chip (1) on system microcontroller standard system bus 16 and the second chip (2) is as interconnect pin, connect interconnection line by wirebond interconnections line or silicon through hole upper for the first chip (1) SOC (system on a chip) microcontroller standard system bus 16 is connected with the upper second SOC (system on a chip) microcontroller standard system bus 27 of the second chip (2), thus obtain the on-chip system chip of stacked on top.
Embodiment 2:
If when on 90nm and some following small size technique, when can not provide embedded non-volatile memory 12, embedded non-volatile memory 12 is arranged on the second chip.As shown in Figure 4, area to be reduced with manufacturing process size and the circuit unit that reduces, comprise the digital peripherals module 15 that central processing unit 13, graphic process unit 14, static data memory 11 and not external with on-chip system chip input and output pin are connected, by little technique, above each unit is realized on the first chip 1.Each unit is all connected with system microcontroller standard system bus 16 on the first on the first chip (1) above.
Then area can not to be reduced with manufacturing process size and the circuit unit that reduces, comprise clock module 23 on analog peripheral 21, power management module 22, sheet, interrupt management module 26, the digital peripherals module 25 be connected with on-chip system chip external input and output pin, the external input and output pin two 4 of on-chip system chip, and above unit is realized on the second chip (2) by large technique by embedded non-volatile memory 12.Each unit is all connected with the second SOC (system on a chip) microcontroller standard system bus 27 on the second chip (2) above.
First chip 1 superposes with the second chip about 2, the second SOC (system on a chip) microcontroller standard system bus 27 on first on first chip (1) on system microcontroller standard system bus 16 and the second chip (2) is as interconnect pin, connect interconnection line by wirebond interconnections line or silicon through hole system microcontroller standard system bus 16 on first is connected with the second microcontroller standard system bus 27, thus obtain the on-chip system chip of stacked on top.
The foregoing is only preferred embodiment of the present invention, be not used for limiting practical range of the present invention.Have in any art and usually know the knowledgeable, without departing from the spirit and scope of the present invention, when doing various variation and retouching, the protection range that scope should define with claims is as the criterion.
Claims (5)
1. a manufacture method for the on-chip system chip of stacked on top, is characterized in that, comprising:
Step one: area can be reduced with manufacturing process size and the circuit unit that reduces realize on the first chip (1), be connected with system microcontroller standard system bus (16) on the first be arranged on described first chip (1);
Step 2: area can not be reduced with manufacturing process size and the circuit unit that reduces realize on the second chip (2), be connected with the second SOC (system on a chip) microcontroller standard system bus (27) be arranged on described second chip (2);
Step 3: by system microcontroller standard system bus (16) on the first of described first chip (1) being connected up and down as interconnect pin with the second SOC (system on a chip) microcontroller standard system bus (27) of the second chip (2), obtain on-chip system chip;
Wherein, on described first, system microcontroller standard system bus (16) and the second SOC (system on a chip) microcontroller standard system bus (27) are the microcontroller standard system bus based on different microcontroller core, comprise based on the AMBA microcontroller standard system bus of ARM kernel, the microcontroller standard system bus based on 8051 kernels, the OCP microcontroller standard system bus based on MIPS kernel.
2. the manufacture method of the on-chip system chip of stacked on top as claimed in claim 1, it is characterized in that, described area can reduce with manufacturing process size and the circuit unit that reduces comprise: the digital peripherals module (15) that static data memory (11), embedded non-volatile memory (12), central processing unit (13), graphic process unit (14), not external with described on-chip system chip input and output pin are connected.
3. the manufacture method of the on-chip system chip of stacked on top as claimed in claim 1, it is characterized in that, described area can not reduce with manufacturing process size and the circuit unit that reduces comprise: clock module (23) on analog peripheral (21), power management module (22), sheet, on-chip system chip external input and output pin (24), the digital peripherals module (25), the interrupt management module (26) that are connected with the external input and output pin (24) of described on-chip system chip.
4. the manufacture method of the on-chip system chip of stacked on top as claimed in claim 1, is characterized in that, in described step 3, described interconnect pin adopts wirebond interconnections line or silicon through hole to connect interconnection line to connect up and down.
5. the manufacture method of the on-chip system chip of stacked on top as claimed in claim 1, is characterized in that, comprise further: described on-chip system chip is connected by the chip stacked on top of more than three or three; The chip of described more than three or three is connected as interconnect pin up and down by SOC (system on a chip) microcontroller standard system bus.
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| CN201210410099.3A CN102891114B (en) | 2012-10-24 | 2012-10-24 | Manufacturing method of chips of up-and-down stacked system-on-chip |
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| KR102029682B1 (en) * | 2013-03-15 | 2019-10-08 | 삼성전자주식회사 | Semiconductor device and semiconductor package |
| CN104037128B (en) * | 2014-06-12 | 2017-06-13 | 上海新储集成电路有限公司 | The preparation method of configurable microcontroller chip |
| US10381330B2 (en) | 2017-03-28 | 2019-08-13 | Silicon Storage Technology, Inc. | Sacrificial alignment ring and self-soldering vias for wafer bonding |
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