CN102945823B - Method for reducing area of interconnected input-output pins on stacked chips - Google Patents
Method for reducing area of interconnected input-output pins on stacked chips Download PDFInfo
- Publication number
- CN102945823B CN102945823B CN201210410947.0A CN201210410947A CN102945823B CN 102945823 B CN102945823 B CN 102945823B CN 201210410947 A CN201210410947 A CN 201210410947A CN 102945823 B CN102945823 B CN 102945823B
- Authority
- CN
- China
- Prior art keywords
- input
- output pin
- reduce
- size
- stacked chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a method for reducing the area of interconnected input-output pins on stacked chips. In the manufacturing process of the stacked chips, the area of the interconnected input-output pins is reduced by reducing the number and size of driving transistors in the interconnected input-output pins and reducing the number and size of anti-static discharge devices transistors in the interconnected input-output pins, wherein the stacked chips are interconnected by microcontroller standard system buses as pins. According to the invention, the area of the interconnected input-output pins is reduced by reducing the size of the driving circuit and the size of the anti-static discharge circuit in the interconnected input-output pins on the plurality of chips stacked up and down and interconnected by microcontroller standard system bus as pins, and reducing the number of the driving circuit transistor and the number of the anti-static discharge circuit transistor, as a result, the area of the chip is reduced and the cost of the chip is reduced.
Description
Technical field
The present invention relates to chip-stacked technical field, particularly relate to a kind of method of the input and output pin area that reduces stacked chips interconnects.
Background technology
Because digital and analog circuit can not simultaneously constantly reducing and scaled down along with integrated circuit fabrication process size; so when technique is constantly more and more advanced time, the cost that numerical model analysis SOC (system on a chip) realizes on same chips will more and more not optimized by same technique.Now based on chip-stacked technology, digital logic unit in SOC (system on a chip) and analog circuit are separated, area can be realized on the small size processing chip of advanced person by the digital logic unit of scaled down along with waiting process constantly to reduce, area constantly can not be reduced along with process and the analog circuit of scaled down realizes on the complete and cheap large scale processing chip of depreciation, the method doing pin interconnection stacked on top chip by microcontroller standard system bus also occurs thereupon.
Due to the internal mutual line that these microcontroller standard system bus are SOC (system on a chip) (SOC), be not used in external encapsulation, so these interconnection line signals can not go to drive external circuit, and these pins for many stacked chips up and down of interconnecting can not be subject to coming from the impact of SOC external electrostatic discharges (ESD) after whole encapsulation, so these are for interconnecting stacked on top chip and the driving force of pin done by microcontroller standard system bus and the ability of anti-ESD do not need very strong.This is unlike legacy memory industry; such as DRAM; FLAH etc.; in order to obtain Large Copacity; frequent meeting is encapsulated multiple DRAM or FLASH chip by chip-stacked technology, in order to reduce costs, driving force and the anti-ESD ability of the input and output pin of these DRAM and FLASH are all very strong; can accomplish that single chips and many stackingly can realize, so the driving of their input and output pin and anti-ESD ability all can not reduce.
Summary of the invention
To instant invention overcomes in background technology interconnect pin driving force in stacked chips excessive with anti-static electrictity release hyperenergia, thus to cause between stacked chips interconnection to export the excessive problem of input pin area, propose a kind of method of the input and output pin area that reduces stacked chips interconnects.Present invention reduces output pin driving force and interconnection input and output pin anti-static electrictity release ability to reach the object reducing the area exporting input pin.
The present invention proposes a kind of method of the input and output pin area that reduces stacked chips interconnects, in the process making stacked chips, by reducing quantity, the size of driving transistors in interconnection input and output pin, and reduce quantity, the size of anti-electrostatic discharging device transistor in described interconnection input and output pin, reduce described interconnection input and output pin area; Wherein said stacked chips adopts microcontroller standard system bus to interconnect as pin.
Wherein, described driving transistors comprises PMOS transistor, nmos pass transistor.
Wherein, described anti-electrostatic discharging device transistor comprises metal-oxide-semiconductor, diode.
Wherein, in described input and output pin, the size of driving transistors is at least decreased to 10% of original size; In described input and output pin, the quantity of driving transistors is reduced at most 1.
Wherein, in described interconnection input and output pin, the size of anti-static electrictity release circuit or quantity reduce at most 1/4 of original size or quantity.
Wherein, described stacked chips passes through microcontroller standard system bus as interconnect pin stacked on top.
Wherein, comprise further: the quantity and the size that reduce driving transistors in described interconnection input and output pin make described driving transistors be enough to drive the input and output pin with described driving transistors other end on same interconnection line.
Wherein, comprise further: the quantity and the size that reduce anti-electrostatic discharging device transistor in described interconnection input and output pin make the anti-static electrictity release ability of described anti-electrostatic discharging device transistor be enough to resist the electrostatic produced when interconnect stack chip pin.
The present invention is by reducing to interconnect drive circuit size and anti-static electrictity release circuit size in input and output pin on the stacked on top multiple chips doing pin interconnection by microcontroller standard system bus, and reduce driving transistors quantity and anti-static electrictity release number of transistors, thus reduce interconnection input and output pin area, final reduction chip area, reduces chip cost.
Accompanying drawing explanation
Fig. 1 is output pin drive circuit figure general in embodiment.
Fig. 2 is principal and subordinate's chip circuit connection layout in common printed circuit board.
Fig. 3 is the upper and lower interconnection line connection layout of stacked chips.
Embodiment
Below in conjunction with drawings and Examples, specific embodiments of the present invention are further described in detail, but should not limit the scope of the invention with this.
Reduction stacked chips of the present invention interconnects the method for input and output pin area, in the process making stacked chips, by reducing quantity, the size of driving transistors in interconnection input and output pin, and reduce quantity, the size of anti-electrostatic discharging device transistor in interconnection input and output pin, reduce interconnection input and output pin area; Wherein stacked chips adopts microcontroller standard system bus to interconnect as pin.
Wherein, driving transistors comprises PMOS transistor, nmos pass transistor.
Wherein, anti-electrostatic discharging device transistor comprises metal-oxide-semiconductor, diode.
Wherein, in input and output pin, the size of driving transistors is at least decreased to 10% of original size; In input and output pin, the quantity of driving transistors is reduced at most 1.
Wherein, the size of anti-static electrictity release circuit in input and output pins of interconnecting or quantity reduce at most 1/4 of original size or quantity.
Wherein, stacked chips passes through microcontroller standard system bus as interconnect pin stacked on top.
Wherein, comprise further: the quantity and the size that reduce driving transistors in interconnection input and output pin make driving transistors be enough to drive the input and output pin with driving transistors other end on same interconnection line.
Wherein, comprise further: the quantity and the size that reduce anti-electrostatic discharging device transistor in interconnection input and output pin make the anti-static electrictity release ability of anti-electrostatic discharging device transistor be enough to resist the electrostatic produced when interconnect stack chip pin.
Embodiment 1:
The stacked on top multiple chips being done pin interconnection in the present embodiment by reduction microcontroller standard system bus interconnects input and output pin driving force and reduce the performance of its electrostatic discharge protection; thus reduce the size that its interconnection exports input pin area; the size using microcontroller standard system bus to do the stacked on top multiple chips of pin interconnection reduces further, and SOC cost is reduced further.
Fig. 2 display be a common printed circuit board, have a main driving chip and 3 above it from chip.An output pin of main driving chip is connected from the input pin chip with 3 respectively, be used for driving 3 from chip simultaneously, so for this output pin on main driving chip, its driving force must be very large, and such as drive current is at more than 20mA.But for the stacked on top multiple chips using microcontroller standard system bus to do pin interconnection, as shown in Figure 3,4 pins of upper strata chip can be connected with 4 of a lower layer chip pin, other 4 pins of lower layer chip can be connected to middle island, are then connected on the external pin after encapsulation.Wherein, 4 pins up and down of pin interconnection are done by microcontroller standard system bus, as the input pin that interconnection line is connected, what it was connected with chip internal is a signal in microcontroller standard system bus, the signal that chip internal uses, so the input impedance of this input pin is very little, so the output pin driving force be connected as same interconnection line does not just need 20mA, below 1mA can be reduced to, thus driving force can reduce more than 20 times.
Fig. 1 display be a general output pin drive circuit figure, above a row pmos pipe be used to drive high level, below a row nmos pipe be used to drive low level.P1, P2, Pn are pmos control signals.N1, N2, Nn are NMOS tube control signals.By reducing the size of driving transistors in pin in this enforcement, while reducing driving force, reduce interconnection input and output pin area.Reduce quantity and the size of driving transistors in interconnection input and output pin in the present invention, its driving force is reduced at least can drive the input and output pin of other end on same interconnection line with it.In the present embodiment, transistor size is reduced to 10% to 5%, and driving force is corresponding is reduced to 10% to 5%, thus output pin area can be decreased to original 10% to 5%.
The present embodiment is also by reducing the quantity of driving transistors, and quantity reduces at most most original 1/N (N is the quantity of original pin driving transistors), is namely reduced at most 1.While reducing the ability driving high or low level, reduce interconnection input and output pin area.In the present embodiment, the quantity of transistor is reduced to 1 from 3, and driving force reduces 2 times, output pin area thus reduce 2/3.
Embodiment 2
The interconnect pin of the upper strata chip in the present invention is not directly connected with the pin of encapsulating package after completing encapsulation, and therefore the upper strata chip generation probability of ESD and the requirement of ESD will reduce.The ESD of packaged rear whole chips is determined by the ESD performance of lower layer chip.Therefore, under the prerequisite not reducing the final ESD performance of chip, by reducing single tube size or the number on upper strata chip ESD transistor (comprising metal-oxide-semiconductor, diode or other ESD antistatic structures), ESD requirement can be reduced.
Such as be reduced to HBM 500V by common HBM 2000V, chip ESD area partly in upper strata just can be reduced to original 1/4th.
The ESD transistor that such as originally can bear HBM2000V by 12 wide for 30um length be that wide for 30um length is 0.55um, PMOS transistor forms for the nmos pass transistor of 0.45um and 20, HBM 500V can be born as being reduced to, then ESD transistor can become by 3 wide for 30um length be that the nmos pass transistor of 0.45um and the PMOS transistor of 5 long 0.55um of wide 30um form, therefore ESD area becomes original 1/4th.
The stacked on top multiple chips doing pin interconnection by reduction microcontroller standard system bus in the present embodiment interconnects the anti-ESD performance of input and output pin, namely reduce the size of anti-ESD transistor (comprising the device such as metal-oxide-semiconductor and diode) and reduce the quantity of anti-ESD transistor, to reduce interconnection input and output pin area.In the present invention, reduce quantity and the size of transistor in interconnection input and output pin anti-static electrictity release circuit, make its anti-static electrictity release ability reduce to the electrostatic that at least can resist and produce when interconnect stack chip pin.
Above two embodiments can effectively reduce the area of the input and output pin that to interconnect between stacked chips, thus reduction microcontroller standard system bus does the area of stacked on top multiple chips of pin interconnection, thus the cost of SOC chip after decreasing whole encapsulation.
The foregoing is only preferred embodiment of the present invention, be not used for limiting practical range of the present invention.Have in any art and usually know the knowledgeable, without departing from the spirit and scope of the present invention, when doing various variation and retouching, the protection range that scope should define with claims is as the criterion.
Claims (7)
1. the method for the input and output pin area that reduces stacked chips interconnects, it is characterized in that, in the process making stacked chips, by reducing quantity, the size of driving transistors in interconnection input and output pin, and reduce quantity, the size of anti-electrostatic discharging device in described interconnection input and output pin, reduce described interconnection input and output pin area; Wherein said stacked chips adopts microcontroller standard system bus to interconnect as pin; The interconnect pin of its chip at the middle and upper levels is not directly connected with the pin of encapsulating package.
2. reduce stacked chips interconnects the method for input and output pin area as claimed in claim 1, and it is characterized in that, described driving transistors comprises PMOS transistor, nmos pass transistor.
3. reduce stacked chips interconnects the method for input and output pin area as claimed in claim 1, and it is characterized in that, described anti-electrostatic discharging device comprises metal-oxide-semiconductor, diode.
4. reduce stacked chips interconnects the method for input and output pin area as claimed in claim 1, and it is characterized in that, in described input and output pin, the size of driving transistors is at least decreased to 10% of original size; In described input and output pin, the quantity of driving transistors is reduced at most 1.
5. reduce stacked chips interconnects the method for input and output pin area as claimed in claim 1, it is characterized in that, in described interconnection input and output pin, the size of anti-electrostatic discharging device or quantity reduce at most 1/4 of original size or quantity.
6. reduce stacked chips interconnects the method for input and output pin area as claimed in claim 4, it is characterized in that, comprise further: the quantity and the size that reduce driving transistors in described interconnection input and output pin make described driving transistors be enough to drive the input and output pin with described driving transistors other end on same interconnection line.
7. reduce stacked chips interconnects the method for input and output pin area as claimed in claim 5, it is characterized in that, comprise further: the quantity and the size that reduce anti-electrostatic discharging device in described interconnection input and output pin make the anti-static electrictity release ability of described anti-electrostatic discharging device be enough to resist the electrostatic produced when interconnect stack chip pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210410947.0A CN102945823B (en) | 2012-10-24 | 2012-10-24 | Method for reducing area of interconnected input-output pins on stacked chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210410947.0A CN102945823B (en) | 2012-10-24 | 2012-10-24 | Method for reducing area of interconnected input-output pins on stacked chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102945823A CN102945823A (en) | 2013-02-27 |
| CN102945823B true CN102945823B (en) | 2015-05-27 |
Family
ID=47728753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210410947.0A Active CN102945823B (en) | 2012-10-24 | 2012-10-24 | Method for reducing area of interconnected input-output pins on stacked chips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102945823B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10381330B2 (en) | 2017-03-28 | 2019-08-13 | Silicon Storage Technology, Inc. | Sacrificial alignment ring and self-soldering vias for wafer bonding |
| CN112310070A (en) * | 2020-10-27 | 2021-02-02 | 伟芯科技(绍兴)有限公司 | Multi-silicon-chip integrated circuit device and design method thereof |
| CN113743047B (en) * | 2021-08-19 | 2022-07-05 | 广芯微电子（广州）股份有限公司 | Chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200524096A (en) * | 2003-11-28 | 2005-07-16 | Renesas Tech Corp | Semiconductor integrated circuit device |
| CN101510772A (en) * | 2009-03-19 | 2009-08-19 | 智原科技股份有限公司 | Output/input circuit with small area |
| CN102684681A (en) * | 2011-03-11 | 2012-09-19 | 阿尔特拉公司 | Systems including an i/o stack and methods for fabricating such systems |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001185676A (en) * | 1999-12-24 | 2001-07-06 | Sharp Corp | Semiconductor device |
-
2012
- 2012-10-24 CN CN201210410947.0A patent/CN102945823B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200524096A (en) * | 2003-11-28 | 2005-07-16 | Renesas Tech Corp | Semiconductor integrated circuit device |
| CN101510772A (en) * | 2009-03-19 | 2009-08-19 | 智原科技股份有限公司 | Output/input circuit with small area |
| CN102684681A (en) * | 2011-03-11 | 2012-09-19 | 阿尔特拉公司 | Systems including an i/o stack and methods for fabricating such systems |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102945823A (en) | 2013-02-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10114775B2 (en) | Stacked semiconductor device assembly in computer system | |
| CN103219718B (en) | ESD protection circuit | |
| US8890607B2 (en) | Stacked chip system | |
| US9385527B2 (en) | Enhanced charge device model clamp | |
| US8830640B2 (en) | Electrostatic discharge protection circuit | |
| CN102959704A (en) | Electro-static discharge protection for die of multi-chip module | |
| US9929139B2 (en) | Modular electrostatic discharge (ESD) protection | |
| CN102945823B (en) | Method for reducing area of interconnected input-output pins on stacked chips | |
| US20130228867A1 (en) | Semiconductor device protected from electrostatic discharge | |
| CN103247621A (en) | ESD protection circuit | |
| KR20140116425A (en) | Driver circuit and method of generating an output signal | |
| US20200413531A1 (en) | Spark gap electrostatic discharge (esd) protection for memory cards | |
| JP2017037949A (en) | Semiconductor device | |
| TWI731663B (en) | Buffer system, buffer circuit and operating method thereof | |
| US8373953B2 (en) | Distribution of electrostatic discharge (ESD) circuitry within an integrated circuit | |
| CN102693979B (en) | Whole-chip electrostatic discharge (ESD) protection circuit | |
| CN210838938U (en) | High-voltage integrated chip, intelligent power module and air conditioner | |
| US20080310059A1 (en) | Esd protection design method and related circuit thereof | |
| CN102891114B (en) | Manufacturing method of chips of up-and-down stacked system-on-chip | |
| US7417883B2 (en) | I/O data interconnect reuse as repeater | |
| CN215266279U (en) | Power supply structure of chip and chip | |
| CN210403720U (en) | Integrated circuit chip and integrated circuit | |
| US20080116572A1 (en) | Semiconductor memory modules, methods of arranging terminals therein, and methods of using thereof | |
| CN212725296U (en) | Chip expansion circuit | |
| US7326973B2 (en) | Method and an apparatus for a hard-coded bit value changeable in any layer of metal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |