CN112310070A - Multi-silicon-chip integrated circuit device and design method thereof - Google Patents
Multi-silicon-chip integrated circuit device and design method thereof Download PDFInfo
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- CN112310070A CN112310070A CN202011168191.4A CN202011168191A CN112310070A CN 112310070 A CN112310070 A CN 112310070A CN 202011168191 A CN202011168191 A CN 202011168191A CN 112310070 A CN112310070 A CN 112310070A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Abstract
The application provides a many silicon chips integrated circuit device, wherein, including two above silicon chips, include at least a kind of target input/output module on the silicon chip more than two, wherein target input/output module is the same input/output module on the silicon chip more than two, the same kind on the different silicon chips in the silicon chip more than two target input/output module shorts out together and is connected to an ESD protection circuit that corresponds with this kind of target input/output module. According to the embodiment of the application, the target input and output modules with the same functions are connected to the corresponding ESD protection circuit, the area of a multi-silicon-chip integrated circuit device occupied by the ESD protection circuit can be greatly reduced, the manufacturing cost is reduced, the target input and output modules with the same functions are connected to the ESD protection circuit, the ESD protection circuit connected with the target input and output modules is prevented from being connected in parallel, the parasitic capacitance of the target input and output modules can be greatly reduced, and the working speed of the target input and output modules is improved.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a multi-silicon-chip integrated circuit device and a design method thereof.
Background
With the increasing requirements for the functions of integrated circuits, the integration level of integrated circuit devices is also increasing, and the use of multi-chip packaging technology is becoming more and more widespread. The multi-chip packaging technology is to package silicon chips of a plurality of independent chips in a tube shell in a centralized manner to form a powerful highly integrated circuit device. According to the functional requirements, the silicon chip packaged in one tube shell can realize chips with different functions, can be a chip with the same functional part, and can also be a chip with the same function.
In the prior art, each silicon chip in the integrated circuit device needs to carry out ESD protection circuit design on each input/output module on the silicon chip, for each silicon chip, the area of the ESD protection circuit on one silicon chip can account for 1% -50% of the area of the silicon chip according to the number of the input/output modules, for the whole integrated circuit device, the ESD protection circuit occupies a large amount of area resources, and the manufacturing cost of the integrated circuit device is improved. In addition, when the ESD protection circuit occupies a large area resource, the parasitic capacitance of the ESD protection circuit is also large, and especially when different silicon chips have input/output modules with the same function, the ESD protection circuits connected to the input/output modules with the same function are connected in parallel, which results in that the total parasitic capacitance on the input/output modules is increased by times, and the huge parasitic capacitance will sharply decrease the working speed of the input/output modules.
Disclosure of Invention
In view of this, an object of the embodiments of the present application is to provide a multi-silicon-chip integrated circuit device and a design method thereof, which can reduce an occupied area of an ESD protection circuit in the multi-silicon-chip integrated circuit device, reduce a manufacturing cost of the multi-silicon-chip integrated circuit device, reduce a parasitic capacitance of an input/output module, and improve a working speed of the input/output module.
According to an aspect of the present application, there is provided a multi-silicon-chip integrated circuit device, including two or more silicon chips, where the two or more silicon chips include at least one type of target input/output module, where the target input/output module is an input/output module with the same function on the two or more silicon chips, and the target input/output module of the same type on different silicon chips in the two or more silicon chips is shorted together and connected to an ESD protection circuit corresponding to the type of target input/output module.
In one possible embodiment, the ESD protection circuit is disposed on one of the two or more silicon chips.
In one possible embodiment, the ESD protection circuit is disposed on a separate silicon chip other than the two or more silicon chips.
In one possible implementation manner, for each type of target input/output module, the ESD protection circuit connected to the type of target input/output module is disposed on the independent silicon chip corresponding to the type of target input/output module.
In a possible implementation manner, the ESD protection circuit connected to each type of target input/output module is disposed on the same independent silicon chip.
In one possible embodiment, the ESD protection circuit may employ a diode structure, a Metal Oxide Semiconductor (MOS) pin, or a thyristor (SCR) structure.
In a second aspect, the present application further provides a method for designing a multi-silicon-chip integrated circuit device, including:
determining at least one type of target input/output module on more than two silicon chips, wherein the more than two silicon chips are contained in the multi-silicon chip integrated circuit device, and the target input/output module is an input/output module with the same function on the more than two silicon chips;
for each type of target input and output module, the type of target input and output modules on different silicon chips are in short circuit connection;
and connecting the target input and output module to the ESD protection circuit corresponding to the target input module.
In one possible embodiment, the ESD protection circuit is disposed on one of the two or more silicon chips.
In one possible embodiment, the ESD protection circuit is disposed on a separate silicon chip other than the two or more silicon chips.
In one possible embodiment, the ESD protection circuit may employ a diode structure, a Metal Oxide Semiconductor (MOS) pin, or a thyristor (SCR) structure.
Based on any one of the above aspects, the target input/output modules with the same function on different silicon chips are short-circuited together and connected to one ESD protection circuit corresponding to the target input/output module, and compared with the prior art in which each input/output module is provided with one ESD protection circuit, the target input/output modules with the same function are connected to one corresponding ESD protection circuit, so that the area of a multi-silicon-chip integrated circuit device occupied by the ESD protection circuit can be greatly reduced, the manufacturing cost is reduced, and the target input/output modules with the same function are connected to one ESD protection circuit, thereby preventing the parallel connection of the ESD protection circuits connected to the target input/output modules, greatly reducing the parasitic capacitance of the target input/output modules, and improving the working speed of the target input/output modules.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
FIG. 1 is a block diagram of a prior art multi-silicon integrated circuit device;
FIG. 2 is a block diagram of a multi-silicon integrated circuit device according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of another multi-silicon integrated circuit device provided by an embodiment of the present application;
FIG. 4 is a block diagram of yet another multi-silicon integrated circuit device provided by an embodiment of the present application;
FIG. 5 is a block diagram of yet another multi-silicon integrated circuit device provided by an embodiment of the present application;
fig. 6 shows a flow chart of a design method of a multi-silicon-chip integrated circuit device according to an embodiment of the present application.
Detailed Description
In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for illustrative and descriptive purposes only and are not used to limit the scope of protection of the present application. Additionally, it should be understood that the schematic drawings are not necessarily drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be performed out of order, and steps without logical context may be performed in reverse order or simultaneously. One skilled in the art, under the guidance of this application, may add one or more other operations to, or remove one or more operations from, the flowchart.
In addition, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that in the embodiments of the present application, the term "comprising" is used to indicate the presence of the features stated hereinafter, but does not exclude the addition of further features.
In the design of an integrated circuit, a user design is prepared on a wafer by using a photoetching technology, the wafer is cut to form an independent silicon wafer, finally the silicon wafer is packaged in a proper tube shell, and an input/output module on the silicon wafer is connected to a pin to form an integrated circuit chip. With the increasing requirements for the functions of integrated circuits, the integration level of integrated circuit devices is also increasing, and the use of multi-chip packaging technology is becoming more and more widespread. The multi-chip packaging technology is to package silicon chips of a plurality of independent chips in a tube shell in a centralized manner to form a powerful highly integrated circuit device. According to the functional requirements, the silicon chip packaged in one tube shell can realize chips with different functions, can be a chip with the same functional part, and can also be a chip with the same function.
In the prior art, each silicon chip in the integrated circuit device needs to perform an ESD protection circuit design for each input/output module on the silicon chip. As shown in fig. 1, the multi-silicon integrated circuit device 100 includes three silicon chips 101, 102 and 103, each of which has at least one input/output module 111, in the prior art, each input/output module 111 needs to be designed for ESD protection, that is, each input/output module 111 is connected to one ESD protection circuit 112. The ESD protection circuit 112 may be disposed on one, two, three, four, or inside of the silicon dies 101, 102, and 103. For each silicon chip, the area of the ESD protection circuit on one silicon chip can occupy 1% -50% of the area of the silicon chip according to the number of the input/output modules, and for the whole integrated circuit device, the ESD protection circuit occupies a large amount of area resources, so that the manufacturing cost of the integrated circuit device is increased. In addition, when the ESD protection circuit occupies a large area resource, the parasitic capacitance of the ESD protection circuit is also large, and especially when different silicon chips have input/output modules with the same function, the ESD protection circuits connected to the input/output modules with the same function are connected in parallel, which results in that the total parasitic capacitance on the input/output modules is increased by times, and the huge parasitic capacitance will sharply decrease the working speed of the input/output modules. When a multi-silicon-chip integrated circuit device comprises a plurality of silicon chips, especially a plurality of silicon chips for realizing the same function, the problems of area resource consumption and parasitic capacitance caused by the ESD protection circuit are particularly serious.
In view of this, the present application provides a multi-silicon-chip integrated circuit device and a design method thereof, wherein target input/output modules with the same function on different silicon chips are shorted together and connected to an ESD protection circuit corresponding to the target input/output module, and compared to the prior art in which each input/output module is provided with an ESD protection circuit, the present application connects the target input/output modules with the same function to a corresponding ESD protection circuit, which can greatly reduce the area of the multi-silicon-chip integrated circuit device occupied by the ESD protection circuit and reduce the manufacturing cost, and the target input/output modules with the same function are connected to an ESD protection circuit, thereby preventing the ESD protection circuits connected to the target input/output modules from being connected in parallel, greatly reducing the parasitic capacitance of the target input/output modules, and improving the working speed of the target input/output modules.
As shown in fig. 2, the present application provides a multi-silicon-chip integrated circuit device 200, which includes two or more silicon chips 201, wherein at least one type of target input/output module 211 is included on the two or more silicon chips 201, the target input/output module 211 is an input/output module with the same function on the two or more silicon chips 201, and the target input/output modules 211 on different silicon chips 201 are shorted together and connected to an ESD protection circuit 212 corresponding to the target input/output module.
Fig. 2 shows one type of target input/output module on the two or more silicon chips 201, and when there are two or more types of target input/output modules on the two or more silicon chips 201, for each type of target input/output module, the type of target input/output module is shorted together and connected to the ESD protection circuit 212 corresponding to the type of target input/output module, as shown in fig. 2.
In some embodiments, as shown in FIG. 2, the ESD protection circuit 212 is disposed on one of the two or more dies 201. The ESD protection circuit 212 may be disposed on any silicon chip on which the target input output module 211 is located. In a possible implementation, the ESD protection circuit 212 may also be disposed on a silicon chip without the target input/output module 211 in the two or more silicon chips 201.
In this embodiment, the ESD protection circuit 212 may be fabricated using an integrated device process.
In some embodiments, as shown in fig. 3, the multi-die integrated circuit device 300 includes two or more dies 301, and the target input-output module 311 is shorted together and connected to the ESD protection circuit 312, in which embodiment the ESD protection circuit 312 is disposed on a separate die 302 than the two or more dies 301. Here, the individual silicon wafer 302 is a silicon wafer different from the two or more silicon wafers 301.
In specific implementation, the following two possible implementation manners of embodiment a and embodiment B may be adopted to implement this embodiment:
example A: in one possible implementation, as shown in fig. 4, the multi-silicon integrated circuit device 400 includes more than two silicon chips 401, the ESD protection circuits 412 connected to the same type of target input/output module 411 are disposed on a separate silicon chip 421, and the ESD protection circuits 414 connected to another type of target input/output module 413 are disposed on another separate silicon chip 422. And aiming at each type of target input and output module, the ESD protection circuit connected with the type of input and output module is arranged on an independent silicon chip corresponding to the type of target input and output module.
The target input/output module 411 and the ESD protection circuit 412 on the independent silicon chip 421 may be connected through pad pins on the silicon chip or through metal interconnection lines. Similarly, the target input/output module 413 and the ESD protection circuit 414 on the separate silicon chip 422 may be connected through pad pins on the silicon chip or through metal interconnection lines.
In this embodiment a, the separate silicon chips 421 and 422 provided with the ESD protection circuits 412 and 414 can be prepared by using a discrete device process. When the ESD protection circuit is realized by adopting a discrete device process or an independently processed ESD discrete device or TVS device, the manufacturing cost of the ESD protection circuit part can be further reduced, and due to the difference of the processing processes, smaller parasitic capacitance can be realized, and the working speed of the target input/output module is further improved.
Example B: in another possible implementation, as shown in fig. 5, the multi-silicon integrated circuit device 500 includes more than two silicon chips 501, and the ESD protection circuits 512 connected to the same type of target input/output module 511 and the ESD protection circuits 514 connected to another type of target input/output module 513 are disposed on the same independent silicon chip 521. The ESD protection circuit connected with each type of target input/output module is arranged on the same independent silicon chip.
In this embodiment B, an integrated device process may be used to fabricate the separate silicon wafer 521 on which the ESD protection circuits 512, 514 are disposed.
In one possible embodiment, the target input/ output module 511, 513 and the ESD protection circuit 512, 514 on the independent silicon chip 521 can be connected through metal interconnection lines.
In one possible implementation, the ESD protection circuits 212, 312, 412, 414, 512, and 514 may be ESD circuits or transient suppression (TVS) circuits. In one possible embodiment, the ESD protection circuits 212, 312, 412, 414, 512, and 514 may employ a diode structure, a Metal Oxide Semiconductor (MOS) pin, or a thyristor (SCR) structure.
By using the technical scheme of the embodiment of the invention, when the target input/output module is in short circuit and is connected to a corresponding ESD protection circuit, the ESD protection circuit is only required to be designed on one of at least one silicon chip of the multi-silicon-chip integrated circuit device, or the ESD protection circuit is independently designed on one ESD silicon chip independent of the at least one silicon chip. The embodiment of the invention can save the area occupied by the ESD protection circuit on each silicon chip in the multi-silicon chip integrated circuit device, greatly reduce the area consumption and save the manufacturing cost of the multi-silicon chip integrated circuit. Taking a multi-silicon-chip integrated circuit device integrally packaged with 10 silicon chips as an example, if the ESD area of each silicon chip in the prior art is 30%, the total area cost can be reduced by 27% at most by using the technology of the present invention.
In addition, the embodiment of the invention can also greatly reduce the increase of parasitic capacitance caused by the parallel connection of the ESD protection circuits on a plurality of silicon chips and improve the working speed of the target input/output module. Taking a multi-silicon-chip integrated circuit integrally packaged with 10 silicon chips as an example, if the parasitic capacitance of an ESD circuit of one silicon chip is 2pF, the total parasitic capacitance generated by parallel connection of ESD protection circuits in the existing design is 20pF, and after the technical scheme provided by the embodiment of the invention is adopted, the total parasitic capacitance of the target input/output module is reduced to 2pF, which is reduced by 90%, and the working speed of the target input/output module can be improved by 9 times without considering other factors.
Fig. 6 shows a design method of a multi-silicon-chip integrated circuit device provided by the present application, including:
s601: determining at least one type of target input/output module on more than two silicon chips, wherein the more than two silicon chips are contained in the multi-silicon chip integrated circuit device, and the target input/output module is an input/output module with the same function on the more than two silicon chips;
s602: for each type of target input and output module, the type of target input and output modules on different silicon chips are in short circuit connection;
s603: and connecting the target input and output module to the ESD protection circuit corresponding to the target input module.
In one possible embodiment, the ESD protection circuit is disposed on one of the two or more silicon chips.
In one possible embodiment, the ESD protection circuit is disposed on a separate silicon chip other than the two or more silicon chips.
In one possible embodiment, the ESD protection circuit is provided as a discrete device outside the multi-silicon-chip integrated circuit device, and the discrete device is connected to the target input/output module of the multi-silicon-chip integrated circuit device through a pin of the multi-silicon-chip integrated circuit device.
The design method of the multi-silicon-chip integrated circuit device provided by the embodiment of the application is characterized in that each input/output module is provided with one ESD protection circuit, the target input/output modules with the same functions are connected to one corresponding ESD protection circuit, the area of the multi-silicon-chip integrated circuit device occupied by the ESD protection circuits can be greatly reduced, the manufacturing cost is reduced, the target input/output modules with the same functions are connected to one ESD protection circuit, the ESD protection circuits connected with the target input/output modules are prevented from being connected in parallel, the parasitic capacitance of the target input/output modules can be greatly reduced, and the working speed of the target input/output modules is improved.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system and the apparatus described above may refer to corresponding processes in the method embodiments, and are not described in detail in this application. In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. The above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical division, and there may be other divisions in actual implementation, and for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or modules through some communication interfaces, and may be in an electrical, mechanical or other form.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A multi-silicon-chip integrated circuit device, comprising: the target input/output module has the same function on the two or more silicon chips, and the target input/output modules of the same type on different silicon chips in the two or more silicon chips are shorted together and connected to an ESD protection circuit corresponding to the target input/output module.
2. The multi-die integrated circuit device of claim 1, wherein the ESD protection circuit is disposed on one of the two or more dies.
3. The multi-die integrated circuit device of claim 1, wherein the ESD protection circuit is disposed on a separate die than the two or more dies.
4. The multi-silicon-chip integrated circuit device according to claim 3, wherein, for each type of target input/output module, the ESD protection circuit connected to the type of target input/output module is disposed on the independent silicon chip corresponding to the type of target input/output module.
5. The multi-silicon integrated circuit device according to claim 3, wherein the ESD protection circuits connected to each type of target input/output module are disposed on the same independent silicon chip.
6. The multi-silicon-chip integrated circuit device according to any one of claims 1 to 5, wherein the ESD protection circuit can adopt a diode structure, a Metal Oxide Semiconductor (MOS) pin or a thyristor (SCR) structure.
7. A method for designing a multi-silicon-chip integrated circuit device, comprising:
determining at least one type of target input/output module on more than two silicon chips, wherein the more than two silicon chips are contained in the multi-silicon chip integrated circuit device, and the target input/output module is an input/output module with the same function on the more than two silicon chips;
for each type of target input and output module, the type of target input and output modules on different silicon chips are in short circuit connection;
and connecting the target input and output module to the ESD protection circuit corresponding to the target input module.
8. The method of claim 7, wherein the ESD protection circuit is disposed on one of the two or more silicon dies.
9. The method of claim 7, wherein the ESD protection circuit is disposed on a separate silicon die than the two or more silicon dies.
10. The method of any of claims 7-9, wherein the ESD protection circuit is in a diode configuration, a Metal Oxide Semiconductor (MOS) pin, or a thyristor (SCR) configuration.
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