TW200644426A - Configurable logic and memory block, and programmable pass gate based configurable logic device - Google Patents
Configurable logic and memory block, and programmable pass gate based configurable logic deviceInfo
- Publication number
- TW200644426A TW200644426A TW095115248A TW95115248A TW200644426A TW 200644426 A TW200644426 A TW 200644426A TW 095115248 A TW095115248 A TW 095115248A TW 95115248 A TW95115248 A TW 95115248A TW 200644426 A TW200644426 A TW 200644426A
- Authority
- TW
- Taiwan
- Prior art keywords
- configurable logic
- logic device
- clmb
- sram
- memory block
- Prior art date
Links
- 230000003068 static effect Effects 0.000 abstract 1
Landscapes
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A configurable logic and memory block (CLMB) and a configurable logic device are disclosed. The CLMB includes one or more static random access memory (SRAM) cells, a first output module for generating a first output by reading at least one SRAM cell when the CLMB functions as an SRAM, a second output module for generating a second output by reading at least one SRAM cell when the CLMB functions as a program logic device (PLD), wherein data on one or more bitlines coupled to the SRAM cells are controllably feeding into the first and second output modules. The configurable logic device can provide various Boolean logic functions using pass gates.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/119,086 US7401302B2 (en) | 2004-04-29 | 2005-04-29 | System on chip development with reconfigurable multi-project wafer technology |
| US11/180,936 US7350177B2 (en) | 2004-04-29 | 2005-07-13 | Configurable logic and memory devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200644426A true TW200644426A (en) | 2006-12-16 |
| TWI315610B TWI315610B (en) | 2009-10-01 |
Family
ID=37195497
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW095115249A TWI321841B (en) | 2005-04-29 | 2006-04-28 | System on chip development with reconfigurable multi-project wafer technology |
| TW095115248A TWI315610B (en) | 2005-04-29 | 2006-04-28 | Configurable logic and memory block, and programmable pass gate based configurable logic device |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW095115249A TWI321841B (en) | 2005-04-29 | 2006-04-28 | System on chip development with reconfigurable multi-project wafer technology |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP4730192B2 (en) |
| CN (3) | CN101359908B (en) |
| TW (2) | TWI321841B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130191572A1 (en) * | 2012-01-23 | 2013-07-25 | Qualcomm Incorporated | Transaction ordering to avoid bus deadlocks |
| US10176855B2 (en) * | 2013-11-21 | 2019-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional (3-D) write assist scheme for memory cells |
| US9275180B1 (en) * | 2014-07-14 | 2016-03-01 | Xilinx, Inc. | Programmable integrated circuit having different types of configuration memory |
| KR102201566B1 (en) * | 2017-08-18 | 2021-01-11 | 주식회사 엘지화학 | Customized bms module and method for designing thereof |
| TWI661676B (en) * | 2018-08-01 | 2019-06-01 | 新唐科技股份有限公司 | Programmable array logic |
| CN110364203B (en) * | 2019-06-20 | 2021-01-05 | 中山大学 | Storage system supporting internal calculation of storage and calculation method |
| US11088693B2 (en) * | 2019-07-08 | 2021-08-10 | Hossein Asadi | Configurable logic block for implementing a Boolean function |
| CN112106139A (en) * | 2020-08-13 | 2020-12-18 | 长江存储科技有限责任公司 | Flash memory device |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0695569B2 (en) * | 1984-11-20 | 1994-11-24 | 富士通株式会社 | Gate array LSI device |
| US5200907A (en) * | 1990-04-16 | 1993-04-06 | Tran Dzung J | Transmission gate logic design method |
| JPH04240768A (en) * | 1991-01-25 | 1992-08-28 | Matsushita Electron Corp | Read-only semiconductor memory device |
| JPH06224300A (en) * | 1993-01-26 | 1994-08-12 | Hitachi Ltd | Designing method for semiconductor integrated circuit and semiconductor integrated circuit for evaluation |
| JP3407975B2 (en) * | 1994-05-20 | 2003-05-19 | 株式会社半導体エネルギー研究所 | Thin film semiconductor integrated circuit |
| US6237132B1 (en) * | 1998-08-18 | 2001-05-22 | International Business Machines Corporation | Toggle based application specific core methodology |
| JP2002289817A (en) * | 2001-03-27 | 2002-10-04 | Toshiba Corp | Semiconductor integrated circuit device and its manufacturing method |
| US7170315B2 (en) * | 2003-07-31 | 2007-01-30 | Actel Corporation | Programmable system on a chip |
| US7032191B2 (en) * | 2004-02-27 | 2006-04-18 | Rapid Bridge Llc | Method and architecture for integrated circuit design and manufacture |
-
2006
- 2006-04-28 CN CN200810145354XA patent/CN101359908B/en not_active Expired - Fee Related
- 2006-04-28 TW TW095115249A patent/TWI321841B/en active
- 2006-04-28 CN CNB200610077245XA patent/CN100538881C/en not_active Expired - Fee Related
- 2006-04-28 TW TW095115248A patent/TWI315610B/en not_active IP Right Cessation
- 2006-04-29 CN CNB200610078986XA patent/CN100508190C/en active Active
- 2006-05-01 JP JP2006127703A patent/JP4730192B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TWI315610B (en) | 2009-10-01 |
| CN100538881C (en) | 2009-09-09 |
| CN101359908A (en) | 2009-02-04 |
| TWI321841B (en) | 2010-03-11 |
| CN100508190C (en) | 2009-07-01 |
| JP4730192B2 (en) | 2011-07-20 |
| CN1917082A (en) | 2007-02-21 |
| JP2006310869A (en) | 2006-11-09 |
| CN101359908B (en) | 2010-08-18 |
| CN1855485A (en) | 2006-11-01 |
| TW200723501A (en) | 2007-06-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |