JP4708563B2 - 薄くドープされたドレイントランジスタの有効なチャネル長さを減じる方法およびトランジスタを形成する方法 - Google Patents
薄くドープされたドレイントランジスタの有効なチャネル長さを減じる方法およびトランジスタを形成する方法 Download PDFInfo
- Publication number
- JP4708563B2 JP4708563B2 JP2000541729A JP2000541729A JP4708563B2 JP 4708563 B2 JP4708563 B2 JP 4708563B2 JP 2000541729 A JP2000541729 A JP 2000541729A JP 2000541729 A JP2000541729 A JP 2000541729A JP 4708563 B2 JP4708563 B2 JP 4708563B2
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- Prior art keywords
- region
- drain
- substrate
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- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/605—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having significant overlap between the lightly-doped extensions and the gate electrode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/225—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/050,730 | 1998-03-30 | ||
| US09/050,730 US5970353A (en) | 1998-03-30 | 1998-03-30 | Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion |
| PCT/US1998/024907 WO1999050900A1 (en) | 1998-03-30 | 1998-11-24 | Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002510861A JP2002510861A (ja) | 2002-04-09 |
| JP2002510861A5 JP2002510861A5 (https=) | 2006-01-05 |
| JP4708563B2 true JP4708563B2 (ja) | 2011-06-22 |
Family
ID=21967049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000541729A Expired - Fee Related JP4708563B2 (ja) | 1998-03-30 | 1998-11-24 | 薄くドープされたドレイントランジスタの有効なチャネル長さを減じる方法およびトランジスタを形成する方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5970353A (https=) |
| EP (1) | EP1068637A1 (https=) |
| JP (1) | JP4708563B2 (https=) |
| KR (1) | KR100615657B1 (https=) |
| WO (1) | WO1999050900A1 (https=) |
Families Citing this family (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5645440A (en) | 1995-10-16 | 1997-07-08 | Masimo Corporation | Patient cable connector |
| US6541756B2 (en) | 1991-03-21 | 2003-04-01 | Masimo Corporation | Shielded optical probe having an electrical connector |
| JPH11168069A (ja) * | 1997-12-03 | 1999-06-22 | Nec Corp | 半導体装置の製造方法 |
| US6048784A (en) * | 1997-12-17 | 2000-04-11 | Texas Instruments Incorporated | Transistor having an improved salicided gate and method of construction |
| US6153455A (en) | 1998-10-13 | 2000-11-28 | Advanced Micro Devices | Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer |
| US6174778B1 (en) * | 1998-12-15 | 2001-01-16 | United Microelectronics Corp. | Method of fabricating metal oxide semiconductor |
| KR100289810B1 (ko) * | 1999-05-10 | 2001-05-15 | 김영환 | 반도체 소자 제조를 위한 할로 이온 주입 방법 |
| US6194293B1 (en) * | 1999-05-25 | 2001-02-27 | Advanced Micro Devices, Inc. | Channel formation after source and drain regions are formed |
| FR2794898B1 (fr) * | 1999-06-11 | 2001-09-14 | France Telecom | Dispositif semi-conducteur a tension de seuil compensee et procede de fabrication |
| US6194278B1 (en) * | 1999-06-21 | 2001-02-27 | Infineon Technologies North America Corp. | Device performance by employing an improved method for forming halo implants |
| US7091093B1 (en) * | 1999-09-17 | 2006-08-15 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating a semiconductor device having a pocket dopant diffused layer |
| US6319798B1 (en) * | 1999-09-23 | 2001-11-20 | Advanced Micro Devices, Inc. | Method for reducing lateral dopant gradient in source/drain extension of MOSFET |
| US7192836B1 (en) * | 1999-11-29 | 2007-03-20 | Advanced Micro Devices, Inc. | Method and system for providing halo implant to a semiconductor device with minimal impact to the junction capacitance |
| US6255175B1 (en) * | 2000-01-07 | 2001-07-03 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with minimized parasitic Miller capacitance |
| US20020061309A1 (en) * | 2000-03-08 | 2002-05-23 | Garger Stephen J. | Production of peptides in plants as N-terminal viral coat protein fusions |
| US6500739B1 (en) * | 2001-06-14 | 2002-12-31 | Taiwan Semiconductor Manufacturing Company | Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect |
| US6475885B1 (en) * | 2001-06-29 | 2002-11-05 | Advanced Micro Devices, Inc. | Source/drain formation with sub-amorphizing implantation |
| US6489223B1 (en) | 2001-07-03 | 2002-12-03 | International Business Machines Corporation | Angled implant process |
| US6649460B2 (en) | 2001-10-25 | 2003-11-18 | International Business Machines Corporation | Fabricating a substantially self-aligned MOSFET |
| US6509221B1 (en) | 2001-11-15 | 2003-01-21 | International Business Machines Corporation | Method for forming high performance CMOS devices with elevated sidewall spacers |
| KR100422326B1 (ko) * | 2002-06-25 | 2004-03-11 | 동부전자 주식회사 | 반도체 소자의 제조방법 |
| DE10261374B4 (de) * | 2002-12-30 | 2010-01-21 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung von als Feldeffekttransistor ausgebildeten Halbleiterelementen mit verbesserten Dotierprofilen |
| US20040124458A1 (en) * | 2002-12-31 | 2004-07-01 | Chandrasekharan Kothandaraman | Programmable fuse device |
| US6927414B2 (en) * | 2003-06-17 | 2005-08-09 | International Business Machines Corporation | High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof |
| EP1678750A1 (en) * | 2003-10-17 | 2006-07-12 | Koninklijke Philips Electronics N.V. | Semiconductor device and method of manufacturing such a semiconductor device |
| US7118979B2 (en) * | 2003-11-05 | 2006-10-10 | Texas Instruments Incorporated | Method of manufacturing transistor having germanium implant region on the sidewalls of the polysilicon gate electrode |
| US7429771B2 (en) * | 2004-05-07 | 2008-09-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having halo implanting regions |
| KR100698069B1 (ko) * | 2004-07-01 | 2007-03-23 | 동부일렉트로닉스 주식회사 | 씨모스 이미지 센서의 제조방법 |
| US7122435B2 (en) * | 2004-08-02 | 2006-10-17 | Texas Instruments Incorporated | Methods, systems and structures for forming improved transistors |
| DE102004042156B4 (de) * | 2004-08-31 | 2010-10-28 | Advanced Micro Devices, Inc., Sunnyvale | Transistor mit asymmetrischem Source/Drain- und Halo- Implantationsgebiet und Verfahren zum Herstellen desselben |
| US10188348B2 (en) | 2006-06-05 | 2019-01-29 | Masimo Corporation | Parameter upgrade system |
| US7880626B2 (en) | 2006-10-12 | 2011-02-01 | Masimo Corporation | System and method for monitoring the life of a physiological sensor |
| JP2008198763A (ja) * | 2007-02-13 | 2008-08-28 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| JP2008085355A (ja) * | 2007-10-22 | 2008-04-10 | Toshiba Corp | イオン注入方法 |
| DE102008026213B3 (de) * | 2008-05-30 | 2009-09-24 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Durchlassstromerhöhung in Transistoren durch asymmetrische Amorphisierungsimplantation |
| US8124506B2 (en) * | 2008-08-14 | 2012-02-28 | Varian Semiconductor Equipment Associates, Inc. | USJ techniques with helium-treated substrates |
| US8372735B2 (en) * | 2008-08-14 | 2013-02-12 | Varian Semiconductor Equipment Associates, Inc. | USJ techniques with helium-treated substrates |
| US8571619B2 (en) | 2009-05-20 | 2013-10-29 | Masimo Corporation | Hemoglobin display and patient treatment |
| JP6723775B2 (ja) * | 2016-03-16 | 2020-07-15 | エイブリック株式会社 | 半導体装置および半導体装置の製造方法 |
| US10916652B2 (en) | 2016-12-28 | 2021-02-09 | Intel Corporation | Asymmetric transistors and related devices and methods |
| CN115084238A (zh) * | 2021-03-10 | 2022-09-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| PL141094B1 (en) * | 1983-12-09 | 1987-06-30 | Polska Akad Nauk Centrum | Microwave balun transformer,especially for mixers and modulators |
| US4746964A (en) * | 1986-08-28 | 1988-05-24 | Fairchild Semiconductor Corporation | Modification of properties of p-type dopants with other p-type dopants |
| US4861729A (en) * | 1987-08-24 | 1989-08-29 | Matsushita Electric Industrial Co., Ltd. | Method of doping impurities into sidewall of trench by use of plasma source |
| JP3104265B2 (ja) * | 1990-05-30 | 2000-10-30 | 松下電器産業株式会社 | イオン注入方法 |
| US5091763A (en) * | 1990-12-19 | 1992-02-25 | Intel Corporation | Self-aligned overlap MOSFET and method of fabrication |
| US5362982A (en) * | 1992-04-03 | 1994-11-08 | Matsushita Electric Industrial Co., Ltd. | Insulated gate FET with a particular LDD structure |
| JPH0629527A (ja) * | 1992-07-10 | 1994-02-04 | Asahi Kasei Micro Syst Kk | 半導体装置およびその製造方法 |
| JPH06267974A (ja) * | 1993-03-12 | 1994-09-22 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
| US5500379A (en) * | 1993-06-25 | 1996-03-19 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing semiconductor device |
| US5308780A (en) * | 1993-07-22 | 1994-05-03 | United Microelectronics Corporation | Surface counter-doped N-LDD for high hot carrier reliability |
| US5360749A (en) * | 1993-12-10 | 1994-11-01 | Advanced Micro Devices, Inc. | Method of making semiconductor structure with germanium implant for reducing short channel effects and subthreshold current near the substrate surface |
| US5470794A (en) * | 1994-02-23 | 1995-11-28 | Advanced Micro Devices | Method for forming a silicide using ion beam mixing |
| JPH07263682A (ja) * | 1994-03-24 | 1995-10-13 | Oki Electric Ind Co Ltd | サリサイド構造を有するmosfetの製造方法 |
| US5574685A (en) * | 1994-09-01 | 1996-11-12 | Advanced Micro Devices, Inc. | Self-aligned buried channel/junction stacked gate flash memory cell |
| US5593907A (en) * | 1995-03-08 | 1997-01-14 | Advanced Micro Devices | Large tilt angle boron implant methodology for reducing subthreshold current in NMOS integrated circuit devices |
| JPH08250728A (ja) * | 1995-03-10 | 1996-09-27 | Sony Corp | 電界効果型半導体装置及びその製造方法 |
| US5585286A (en) * | 1995-08-31 | 1996-12-17 | Lsi Logic Corporation | Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device |
| JP2848439B2 (ja) * | 1995-11-10 | 1999-01-20 | 日本電気株式会社 | 半導体装置の製造方法 |
| US5719425A (en) * | 1996-01-31 | 1998-02-17 | Micron Technology, Inc. | Multiple implant lightly doped drain (MILDD) field effect transistor |
| US5627087A (en) * | 1996-03-11 | 1997-05-06 | United Microelectronics Corporation | Process for fabricating metal-oxide semiconductor (MOS) transistors based on lightly doped drain (LDD) structure |
| EP0806794A3 (en) * | 1996-04-29 | 1998-09-02 | Texas Instruments Incorporated | Method of forming shallow doped regions in a semiconductor substrate, using preamorphization and ion implantation |
| DE69730019T2 (de) * | 1996-05-08 | 2004-12-30 | Advanced Micro Devices, Inc., Sunnyvale | Kontrolle der p-n-übergangstiefe und kanallänge durch erzeugung von die dotierstoffdiffusion hemmenden zwischengitterstellen-gradienten |
| US5654215A (en) * | 1996-09-13 | 1997-08-05 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor |
| US5747373A (en) * | 1996-09-24 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Nitride-oxide sidewall spacer for salicide formation |
| US5847428A (en) * | 1996-12-06 | 1998-12-08 | Advanced Micro Devices, Inc. | Integrated circuit gate conductor which uses layered spacers to produce a graded junction |
| US6124610A (en) * | 1998-06-26 | 2000-09-26 | Advanced Micro Devices, Inc. | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
| US6268640B1 (en) * | 1999-08-12 | 2001-07-31 | International Business Machines Corporation | Forming steep lateral doping distribution at source/drain junctions |
-
1998
- 1998-03-30 US US09/050,730 patent/US5970353A/en not_active Expired - Lifetime
- 1998-11-24 JP JP2000541729A patent/JP4708563B2/ja not_active Expired - Fee Related
- 1998-11-24 KR KR1020007010869A patent/KR100615657B1/ko not_active Expired - Fee Related
- 1998-11-24 EP EP98960360A patent/EP1068637A1/en not_active Withdrawn
- 1998-11-24 WO PCT/US1998/024907 patent/WO1999050900A1/en not_active Ceased
-
1999
- 1999-09-20 US US09/400,524 patent/US6593623B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| WO1999050900A1 (en) | 1999-10-07 |
| KR100615657B1 (ko) | 2006-08-25 |
| US6593623B1 (en) | 2003-07-15 |
| KR20010042320A (ko) | 2001-05-25 |
| EP1068637A1 (en) | 2001-01-17 |
| US5970353A (en) | 1999-10-19 |
| JP2002510861A (ja) | 2002-04-09 |
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| LAPS | Cancellation because of no payment of annual fees |