JP4698722B2 - 素子搭載用基板、半導体モジュールおよびその製造方法、ならびに携帯機器 - Google Patents

素子搭載用基板、半導体モジュールおよびその製造方法、ならびに携帯機器 Download PDF

Info

Publication number
JP4698722B2
JP4698722B2 JP2008273591A JP2008273591A JP4698722B2 JP 4698722 B2 JP4698722 B2 JP 4698722B2 JP 2008273591 A JP2008273591 A JP 2008273591A JP 2008273591 A JP2008273591 A JP 2008273591A JP 4698722 B2 JP4698722 B2 JP 4698722B2
Authority
JP
Japan
Prior art keywords
electrode
wiring layer
protruding electrode
layer
covering portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008273591A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009135458A (ja
JP2009135458A5 (enrdf_load_stackoverflow
Inventor
哲也 山本
芳央 岡山
康行 柳瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2008273591A priority Critical patent/JP4698722B2/ja
Priority to US12/266,907 priority patent/US8129846B2/en
Priority to CN2008102463746A priority patent/CN101488487B/zh
Publication of JP2009135458A publication Critical patent/JP2009135458A/ja
Publication of JP2009135458A5 publication Critical patent/JP2009135458A5/ja
Application granted granted Critical
Publication of JP4698722B2 publication Critical patent/JP4698722B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Wire Bonding (AREA)
JP2008273591A 2007-11-08 2008-10-23 素子搭載用基板、半導体モジュールおよびその製造方法、ならびに携帯機器 Expired - Fee Related JP4698722B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008273591A JP4698722B2 (ja) 2007-11-08 2008-10-23 素子搭載用基板、半導体モジュールおよびその製造方法、ならびに携帯機器
US12/266,907 US8129846B2 (en) 2007-11-08 2008-11-07 Board adapted to mount an electronic device, semiconductor module and manufacturing method therefor, and portable device
CN2008102463746A CN101488487B (zh) 2007-11-08 2008-11-10 元件搭载用基板、半导体组件及其制造方法及便携式设备

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007291342 2007-11-08
JP2007291342 2007-11-08
JP2008273591A JP4698722B2 (ja) 2007-11-08 2008-10-23 素子搭載用基板、半導体モジュールおよびその製造方法、ならびに携帯機器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010271794A Division JP5295211B2 (ja) 2007-11-08 2010-12-06 半導体モジュールの製造方法

Publications (3)

Publication Number Publication Date
JP2009135458A JP2009135458A (ja) 2009-06-18
JP2009135458A5 JP2009135458A5 (enrdf_load_stackoverflow) 2010-05-13
JP4698722B2 true JP4698722B2 (ja) 2011-06-08

Family

ID=40867002

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2008273591A Expired - Fee Related JP4698722B2 (ja) 2007-11-08 2008-10-23 素子搭載用基板、半導体モジュールおよびその製造方法、ならびに携帯機器
JP2010271794A Active JP5295211B2 (ja) 2007-11-08 2010-12-06 半導体モジュールの製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2010271794A Active JP5295211B2 (ja) 2007-11-08 2010-12-06 半導体モジュールの製造方法

Country Status (1)

Country Link
JP (2) JP4698722B2 (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5002633B2 (ja) * 2009-09-30 2012-08-15 三洋電機株式会社 半導体モジュールおよび携帯機器
US9455162B2 (en) 2013-03-14 2016-09-27 Invensas Corporation Low cost interposer and method of fabrication
JP6102398B2 (ja) * 2013-03-26 2017-03-29 セイコーエプソン株式会社 半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5823943B2 (ja) * 1975-07-16 1983-05-18 松下電器産業株式会社 絶縁体の貫通電極形成方法
JP3474936B2 (ja) * 1994-10-07 2003-12-08 株式会社東芝 実装用印刷配線板およびその製造方法
JP2001326459A (ja) * 2000-05-16 2001-11-22 North:Kk 配線回路基板とその製造方法
JP4568215B2 (ja) * 2005-11-30 2010-10-27 三洋電機株式会社 回路装置および回路装置の製造方法

Also Published As

Publication number Publication date
JP2009135458A (ja) 2009-06-18
JP5295211B2 (ja) 2013-09-18
JP2011049606A (ja) 2011-03-10

Similar Documents

Publication Publication Date Title
US8309864B2 (en) Device mounting board and manufacturing method therefor, and semiconductor module
JP5091600B2 (ja) 半導体モジュール、半導体モジュールの製造方法および携帯機器
WO2010067610A1 (ja) 半導体モジュール、半導体モジュールの製造方法および携帯機器
JP5135246B2 (ja) 半導体モジュールおよびその製造方法、ならびに携帯機器
US20100078813A1 (en) Semiconductor module and method for manufacturing the semiconductor module
JP2010262992A (ja) 半導体モジュールおよび携帯機器
US7492045B2 (en) Semiconductor module, method for manufacturing semiconductor modules and mobile device
JP2009182272A (ja) 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器
JP4588046B2 (ja) 回路装置およびその製造方法
JP4753960B2 (ja) 半導体モジュール、半導体モジュールの製造方法
JP2009224581A (ja) 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、電極構造、携帯機器
US8129846B2 (en) Board adapted to mount an electronic device, semiconductor module and manufacturing method therefor, and portable device
JP2013165087A (ja) 半導体モジュールおよび半導体モジュールの製造方法
JP5134899B2 (ja) 半導体モジュール、半導体モジュールの製造方法および携帯機器
JP2009158830A (ja) 素子搭載用基板およびその製造方法、半導体モジュールおよびその製造方法、ならびに携帯機器
JP5295211B2 (ja) 半導体モジュールの製造方法
US8237258B2 (en) Semiconductor module including a semiconductor device, a device mounting board, and a protecting layer therebetween
JP2011054670A (ja) 半導体モジュールおよびその製造方法、ならびに携帯機器
JP5028291B2 (ja) 素子搭載用基板、素子搭載用基板の製造方法、半導体モジュールおよび半導体モジュールの製造方法
US20100140797A1 (en) Device mounting board and method of manufacturing the board, semiconductor module and method of manufacturing the module
JP2010040721A (ja) 半導体モジュール、半導体装置、携帯機器、半導体モジュールの製造方法および半導体装置の製造方法
JP5061010B2 (ja) 半導体モジュール
JP5022963B2 (ja) 突起電極の構造、素子搭載用基板およびその製造方法、半導体モジュール、ならびに携帯機器
JP5121875B2 (ja) 回路装置
JP5306443B2 (ja) 素子搭載用基板、素子搭載用基板の製造方法、半導体モジュールおよび半導体モジュールの製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100330

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100330

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20100331

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20100414

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100922

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101005

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101206

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110201

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110301

R151 Written notification of patent or utility model registration

Ref document number: 4698722

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

LAPS Cancellation because of no payment of annual fees