JP4671600B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

Info

Publication number
JP4671600B2
JP4671600B2 JP2003431911A JP2003431911A JP4671600B2 JP 4671600 B2 JP4671600 B2 JP 4671600B2 JP 2003431911 A JP2003431911 A JP 2003431911A JP 2003431911 A JP2003431911 A JP 2003431911A JP 4671600 B2 JP4671600 B2 JP 4671600B2
Authority
JP
Japan
Prior art keywords
film
layer
substrate
oxide film
tungsten
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003431911A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004221570A5 (enrdf_load_stackoverflow
JP2004221570A (ja
Inventor
舜平 山崎
徹 高山
純矢 丸山
由美子 大野
裕吾 後藤
秀明 桑原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2003431911A priority Critical patent/JP4671600B2/ja
Publication of JP2004221570A publication Critical patent/JP2004221570A/ja
Publication of JP2004221570A5 publication Critical patent/JP2004221570A5/ja
Application granted granted Critical
Publication of JP4671600B2 publication Critical patent/JP4671600B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor

Landscapes

  • Ceramic Capacitors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
JP2003431911A 2002-12-27 2003-12-26 半導体装置の作製方法 Expired - Fee Related JP4671600B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003431911A JP4671600B2 (ja) 2002-12-27 2003-12-26 半導体装置の作製方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002380726 2002-12-27
JP2003431911A JP4671600B2 (ja) 2002-12-27 2003-12-26 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2004221570A JP2004221570A (ja) 2004-08-05
JP2004221570A5 JP2004221570A5 (enrdf_load_stackoverflow) 2007-02-15
JP4671600B2 true JP4671600B2 (ja) 2011-04-20

Family

ID=32911287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003431911A Expired - Fee Related JP4671600B2 (ja) 2002-12-27 2003-12-26 半導体装置の作製方法

Country Status (1)

Country Link
JP (1) JP4671600B2 (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013179358A (ja) * 2007-03-13 2013-09-09 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100970194B1 (ko) 2004-06-02 2010-07-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치 제조방법
US7591863B2 (en) 2004-07-16 2009-09-22 Semiconductor Energy Laboratory Co., Ltd. Laminating system, IC sheet, roll of IC sheet, and method for manufacturing IC chip
JP5352040B2 (ja) * 2004-08-23 2013-11-27 株式会社半導体エネルギー研究所 半導体装置の作製方法
CN100530549C (zh) 2004-08-23 2009-08-19 株式会社半导体能源研究所 激光照射设备、照射方法和制备半导体器件的方法
US8288773B2 (en) 2004-08-23 2012-10-16 Semiconductor Energy Laboratory Co., Ltd. Wireless chip and manufacturing method thereof
CN101010706B (zh) 2004-09-03 2012-07-11 株式会社半导体能源研究所 健康数据收集系统及半导体器件
JP5008289B2 (ja) * 2004-09-24 2012-08-22 株式会社半導体エネルギー研究所 半導体装置の作製方法、剥離方法
JP4749102B2 (ja) * 2004-09-24 2011-08-17 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7781758B2 (en) * 2004-10-22 2010-08-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2006165535A (ja) * 2004-11-11 2006-06-22 Semiconductor Energy Lab Co Ltd 半導体装置
EP1810334B1 (en) 2004-11-11 2011-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for Manufacturing a Semiconductor Device
US8030643B2 (en) 2005-03-28 2011-10-04 Semiconductor Energy Laboratory Co., Ltd. Memory device and manufacturing method the same
US7687327B2 (en) 2005-07-08 2010-03-30 Kovio, Inc, Methods for manufacturing RFID tags and structures formed therefrom
JP4619900B2 (ja) * 2005-08-22 2011-01-26 京セラ株式会社 有機ｅｌディスプレイ及び有機ｅｌディスプレイの製造方法
US7548407B2 (en) * 2005-09-12 2009-06-16 Qualcomm Incorporated Capacitor structure
CN101449362B (zh) * 2006-05-18 2012-03-28 Nxp股份有限公司 提高半导体器件中电感器的品质因子的方法
JP2008135639A (ja) * 2006-11-29 2008-06-12 Kyocera Corp 積層セラミック電子部品の製造方法及び製造装置
EP2515337B1 (en) 2008-12-24 2016-02-24 Semiconductor Energy Laboratory Co., Ltd. Driver circuit and semiconductor device
JP6087046B2 (ja) * 2011-03-01 2017-03-01 太陽誘電株式会社 薄膜素子の転写方法及び回路基板の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745786A (ja) * 1993-08-02 1995-02-14 Tdk Corp 複合集積回路部品
JPH1126733A (ja) * 1997-07-03 1999-01-29 Seiko Epson Corp 薄膜デバイスの転写方法、薄膜デバイス、薄膜集積回路装置，アクティブマトリクス基板、液晶表示装置および電子機器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013179358A (ja) * 2007-03-13 2013-09-09 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法

Also Published As

Publication number Publication date
JP2004221570A (ja) 2004-08-05

Similar Documents

Publication Publication Date Title
US8441102B2 (en) Semiconductor device having a capacitor
JP4671600B2 (ja) 半導体装置の作製方法
US6331722B1 (en) Hybrid circuit and electronic device using same
CN1832169B (zh) 无线芯片以及具有该无线芯片的电子设备
CN101142715B (zh) 半导体器件以及具有该半导体器件的电子器件
CN100530576C (zh) 半导体器件以及其制作方法
JP4974541B2 (ja) 無線チップの作製方法
CN102646681B (zh) 半导体器件
JP5707470B2 (ja) 半導体装置
KR101443176B1 (ko) 반도체 장치 및 그것의 제작 방법
TW200417033A (en) Semiconductor chip and method for manufacturing the same
TW200947664A (en) Semiconductor device and manufacturing method of the same
JP2005277579A (ja) 高周波モジュールおよびそれを用いた通信機器
TW201110454A (en) Semiconductor device and method of forming directional RF coupler with IPD for additional RF signal processing
WO1996027905A1 (en) High-frequency amplifier circuit
JP3868567B2 (ja) 複合化回路の作製方法
CN118475213A (zh) 复合衬底、射频集成式器件、制备方法及装置
JP4884807B2 (ja) 無線チップの作製方法
WO2024174730A1 (zh) 一种滤波器封装结构、封装方法及通信装置
JP2005277940A (ja) 高周波モジュールおよびそれを用いた通信機器
JP2006013614A (ja) 薄膜圧電共振装置
JPH10209466A (ja) 複合化回路及び複合化回路を内蔵した電子装置
JP2009224796A (ja) 複合化回路及び複合化回路を有する電子装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061225

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061225

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101116

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101118

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101214

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110111

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110118

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4671600

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140128

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees