JP4630906B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4630906B2 JP4630906B2 JP2008051240A JP2008051240A JP4630906B2 JP 4630906 B2 JP4630906 B2 JP 4630906B2 JP 2008051240 A JP2008051240 A JP 2008051240A JP 2008051240 A JP2008051240 A JP 2008051240A JP 4630906 B2 JP4630906 B2 JP 4630906B2
- Authority
- JP
- Japan
- Prior art keywords
- core material
- film
- pattern
- semiconductor device
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/60—Wet etching
- H10P50/64—Wet etching of semiconductor materials
- H10P50/642—Chemical etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4088—Processes for improving the resolution of the masks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/947—Subphotolithographic processing
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008051240A JP4630906B2 (ja) | 2008-02-29 | 2008-02-29 | 半導体装置の製造方法 |
| US12/395,094 US8088689B2 (en) | 2008-02-29 | 2009-02-27 | Method of fabricating semiconductor device |
| KR1020090016754A KR101087311B1 (ko) | 2008-02-29 | 2009-02-27 | 반도체 장치를 제조하는 방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008051240A JP4630906B2 (ja) | 2008-02-29 | 2008-02-29 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009212163A JP2009212163A (ja) | 2009-09-17 |
| JP2009212163A5 JP2009212163A5 (https=) | 2010-04-08 |
| JP4630906B2 true JP4630906B2 (ja) | 2011-02-09 |
Family
ID=41013514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008051240A Expired - Fee Related JP4630906B2 (ja) | 2008-02-29 | 2008-02-29 | 半導体装置の製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8088689B2 (https=) |
| JP (1) | JP4630906B2 (https=) |
| KR (1) | KR101087311B1 (https=) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5160302B2 (ja) * | 2008-05-19 | 2013-03-13 | 株式会社東芝 | 半導体装置の製造方法 |
| JP5606388B2 (ja) | 2011-05-13 | 2014-10-15 | 株式会社東芝 | パターン形成方法 |
| JP2013197266A (ja) | 2012-03-19 | 2013-09-30 | Toshiba Corp | 半導体装置およびその製造方法 |
| US9564361B2 (en) * | 2013-09-13 | 2017-02-07 | Qualcomm Incorporated | Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device |
| US9847339B2 (en) * | 2016-04-12 | 2017-12-19 | Macronix International Co., Ltd. | Self-aligned multiple patterning semiconductor device fabrication |
| JP6981945B2 (ja) | 2018-09-13 | 2021-12-17 | 信越化学工業株式会社 | パターン形成方法 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6435916A (en) * | 1987-07-31 | 1989-02-07 | Hitachi Ltd | Formation of fine pattern |
| JPH01119028A (ja) * | 1987-10-30 | 1989-05-11 | Nec Corp | 半導体装置の製造方法 |
| US4838991A (en) | 1987-10-30 | 1989-06-13 | International Business Machines Corporation | Process for defining organic sidewall structures |
| US5328810A (en) * | 1990-05-07 | 1994-07-12 | Micron Technology, Inc. | Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process |
| US6924191B2 (en) | 2002-06-20 | 2005-08-02 | Applied Materials, Inc. | Method for fabricating a gate structure of a field effect transistor |
| JP2006032648A (ja) * | 2004-07-16 | 2006-02-02 | Toshiba Corp | パターン形成方法を含む半導体装置の製造方法 |
| US7253118B2 (en) | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
| JP4921723B2 (ja) | 2005-04-18 | 2012-04-25 | 株式会社東芝 | 半導体装置の製造方法 |
| JP4271243B2 (ja) * | 2006-04-11 | 2009-06-03 | 株式会社東芝 | 集積回路パターンの形成方法 |
-
2008
- 2008-02-29 JP JP2008051240A patent/JP4630906B2/ja not_active Expired - Fee Related
-
2009
- 2009-02-27 US US12/395,094 patent/US8088689B2/en not_active Expired - Fee Related
- 2009-02-27 KR KR1020090016754A patent/KR101087311B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20090221147A1 (en) | 2009-09-03 |
| JP2009212163A (ja) | 2009-09-17 |
| US8088689B2 (en) | 2012-01-03 |
| KR101087311B1 (ko) | 2011-11-25 |
| KR20090093869A (ko) | 2009-09-02 |
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