JP4621718B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4621718B2
JP4621718B2 JP2007233908A JP2007233908A JP4621718B2 JP 4621718 B2 JP4621718 B2 JP 4621718B2 JP 2007233908 A JP2007233908 A JP 2007233908A JP 2007233908 A JP2007233908 A JP 2007233908A JP 4621718 B2 JP4621718 B2 JP 4621718B2
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JP
Japan
Prior art keywords
film
line
pattern
resist
space
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007233908A
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English (en)
Japanese (ja)
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JP2009065093A (ja
JP2009065093A5 (https=
Inventor
光広 大村
和幸 東
卓司 国谷
真 和田
明広 梶田
勝朗 石川
英樹 小熊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2007233908A priority Critical patent/JP4621718B2/ja
Priority to US12/208,010 priority patent/US20090191712A1/en
Publication of JP2009065093A publication Critical patent/JP2009065093A/ja
Publication of JP2009065093A5 publication Critical patent/JP2009065093A5/ja
Application granted granted Critical
Publication of JP4621718B2 publication Critical patent/JP4621718B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP2007233908A 2007-09-10 2007-09-10 半導体装置の製造方法 Expired - Fee Related JP4621718B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007233908A JP4621718B2 (ja) 2007-09-10 2007-09-10 半導体装置の製造方法
US12/208,010 US20090191712A1 (en) 2007-09-10 2008-09-10 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007233908A JP4621718B2 (ja) 2007-09-10 2007-09-10 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2009065093A JP2009065093A (ja) 2009-03-26
JP2009065093A5 JP2009065093A5 (https=) 2009-10-22
JP4621718B2 true JP4621718B2 (ja) 2011-01-26

Family

ID=40559382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007233908A Expired - Fee Related JP4621718B2 (ja) 2007-09-10 2007-09-10 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US20090191712A1 (https=)
JP (1) JP4621718B2 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4901898B2 (ja) 2009-03-30 2012-03-21 株式会社東芝 半導体装置の製造方法
US9337197B1 (en) * 2014-10-28 2016-05-10 Globalfoundries Inc. Semiconductor structure having FinFET ultra thin body and methods of fabrication thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0472622A (ja) * 1990-07-13 1992-03-06 Hitachi Ltd 半導体装置およびその製造方法
JPH08306698A (ja) * 1995-05-10 1996-11-22 Casio Comput Co Ltd パターン形成方法
JP2002280388A (ja) * 2001-03-15 2002-09-27 Toshiba Corp 半導体装置の製造方法
DE10142590A1 (de) * 2001-08-31 2003-04-03 Infineon Technologies Ag Verfahren zur Seitenwandverstärkung von Resiststrukturen und zur Herstellung von Strukturen mit reduzierter Strukturgröße
JP2004014652A (ja) * 2002-06-04 2004-01-15 Ricoh Co Ltd 微細パターンの形成方法
US6867116B1 (en) * 2003-11-10 2005-03-15 Macronix International Co., Ltd. Fabrication method of sub-resolution pitch for integrated circuits
US7183205B2 (en) * 2004-06-08 2007-02-27 Macronix International Co., Ltd. Method of pitch dimension shrinkage
US7465525B2 (en) * 2005-05-10 2008-12-16 Lam Research Corporation Reticle alignment and overlay for multiple reticle process
JP4652140B2 (ja) * 2005-06-21 2011-03-16 東京エレクトロン株式会社 プラズマエッチング方法、制御プログラム、コンピュータ記憶媒体

Also Published As

Publication number Publication date
JP2009065093A (ja) 2009-03-26
US20090191712A1 (en) 2009-07-30

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