JP4574302B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP4574302B2
JP4574302B2 JP2004267800A JP2004267800A JP4574302B2 JP 4574302 B2 JP4574302 B2 JP 4574302B2 JP 2004267800 A JP2004267800 A JP 2004267800A JP 2004267800 A JP2004267800 A JP 2004267800A JP 4574302 B2 JP4574302 B2 JP 4574302B2
Authority
JP
Japan
Prior art keywords
probe
wafer
cleaning
semiconductor device
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004267800A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006086244A5 (zh
JP2006086244A (ja
Inventor
淳逸 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2004267800A priority Critical patent/JP4574302B2/ja
Publication of JP2006086244A publication Critical patent/JP2006086244A/ja
Publication of JP2006086244A5 publication Critical patent/JP2006086244A5/ja
Application granted granted Critical
Publication of JP4574302B2 publication Critical patent/JP4574302B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2004267800A 2004-09-15 2004-09-15 半導体装置の製造方法 Expired - Fee Related JP4574302B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004267800A JP4574302B2 (ja) 2004-09-15 2004-09-15 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004267800A JP4574302B2 (ja) 2004-09-15 2004-09-15 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2006086244A JP2006086244A (ja) 2006-03-30
JP2006086244A5 JP2006086244A5 (zh) 2007-10-25
JP4574302B2 true JP4574302B2 (ja) 2010-11-04

Family

ID=36164508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004267800A Expired - Fee Related JP4574302B2 (ja) 2004-09-15 2004-09-15 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP4574302B2 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009115720A (ja) * 2007-11-08 2009-05-28 Japan Electronic Materials Corp プローブのクリーニング方法およびプローブのクリーニング装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004228314A (ja) * 2003-01-22 2004-08-12 Renesas Technology Corp パッドを有する半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840836A (ja) * 1981-09-03 1983-03-09 Seiko Epson Corp 半導体装置の製造方法
JPH0442944A (ja) * 1990-06-06 1992-02-13 Matsushita Electron Corp 半導体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004228314A (ja) * 2003-01-22 2004-08-12 Renesas Technology Corp パッドを有する半導体装置

Also Published As

Publication number Publication date
JP2006086244A (ja) 2006-03-30

Similar Documents

Publication Publication Date Title
US7168163B2 (en) Full wafer silicon probe card for burn-in and testing and test system including same
US7219422B2 (en) Fabrication method of semiconductor integrated circuit device
Mann et al. The leading edge of production wafer probe test technology
US7223616B2 (en) Test structures in unused areas of semiconductor integrated circuits and methods for designing the same
JP5065674B2 (ja) 半導体集積回路装置の製造方法
JP4372785B2 (ja) 半導体集積回路装置の製造方法
JP2005277338A (ja) 半導体装置及びその検査方法
CN101996911B (zh) 对栅氧化层进行失效分析的方法
JP2001091544A (ja) 半導体検査装置の製造方法
JP2005136302A (ja) 半導体集積回路装置の製造方法
JP2005136246A (ja) 半導体集積回路装置の製造方法
JP2008205042A (ja) 半導体集積回路装置の製造方法
JP7299952B2 (ja) 半導体ユニットのテスト方法
JP4830772B2 (ja) 半導体チップの検査方法
JP4574302B2 (ja) 半導体装置の製造方法
US6972202B2 (en) Method of manufacturing and testing a semiconductor device
JP2007003252A (ja) プローブカードおよび半導体集積回路の試験方法
JP2010267689A (ja) 半導体集積回路装置の製造方法
JP4052966B2 (ja) ウェハ検査装置およびその検査方法
JP4852943B2 (ja) 半導体デバイスチップの選別方法
JP2010098046A (ja) プローブカードおよび半導体装置の製造方法
JP2006196711A (ja) 半導体集積回路、プローブカードおよび半導体集積回路の試験方法
JP2002141474A (ja) プレーナ型半導体チップとそのテスト方法並びに半導体ウエハ
JP2007121152A (ja) 半導体集積回路装置の製造方法およびプローブカードの製造方法
JP2003332399A (ja) 絶縁膜の評価方法及び評価装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070910

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070910

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100218

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100528

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100803

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100818

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130827

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees