JP4562919B2 - ダイナミック・ディスプレイ・メモリを実装するための方法および装置 - Google Patents

ダイナミック・ディスプレイ・メモリを実装するための方法および装置 Download PDF

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JP4562919B2
JP4562919B2 JP2000594101A JP2000594101A JP4562919B2 JP 4562919 B2 JP4562919 B2 JP 4562919B2 JP 2000594101 A JP2000594101 A JP 2000594101A JP 2000594101 A JP2000594101 A JP 2000594101A JP 4562919 B2 JP4562919 B2 JP 4562919B2
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memory
graphics
operand
control component
address
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Japanese (ja)
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JP2002535763A5 (enExample
JP2002535763A (ja
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ドイル，ピーター
スリニバス，アジャ
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/122—Tiling

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)
JP2000594101A 1999-01-15 2000-01-12 ダイナミック・ディスプレイ・メモリを実装するための方法および装置 Expired - Fee Related JP4562919B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/231,609 1999-01-15
US09/231,609 US6362826B1 (en) 1999-01-15 1999-01-15 Method and apparatus for implementing dynamic display memory
PCT/US2000/000776 WO2000042594A1 (en) 1999-01-15 2000-01-12 Method and apparatus for implementing dynamic display memory

Publications (3)

Publication Number Publication Date
JP2002535763A JP2002535763A (ja) 2002-10-22
JP2002535763A5 JP2002535763A5 (enExample) 2006-03-09
JP4562919B2 true JP4562919B2 (ja) 2010-10-13

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JP2000594101A Expired - Fee Related JP4562919B2 (ja) 1999-01-15 2000-01-12 ダイナミック・ディスプレイ・メモリを実装するための方法および装置

Country Status (9)

Country Link
US (2) US6362826B1 (enExample)
EP (1) EP1141930B1 (enExample)
JP (1) JP4562919B2 (enExample)
KR (1) KR100433499B1 (enExample)
CN (1) CN1135477C (enExample)
AU (1) AU3470700A (enExample)
DE (1) DE60038871D1 (enExample)
TW (1) TWI250482B (enExample)
WO (1) WO2000042594A1 (enExample)

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US7710425B1 (en) * 2000-06-09 2010-05-04 3Dlabs Inc. Ltd. Graphic memory management with invisible hardware-managed page faulting
US6704021B1 (en) * 2000-11-20 2004-03-09 Ati International Srl Method and apparatus for efficiently processing vertex information in a video graphics system
US6828977B2 (en) * 2001-02-15 2004-12-07 Sony Corporation Dynamic buffer pages
US6803917B2 (en) 2001-02-15 2004-10-12 Sony Corporation Checkerboard buffer using memory bank alternation
US7379069B2 (en) 2001-02-15 2008-05-27 Sony Corporation Checkerboard buffer using two-dimensional buffer pages
US7205993B2 (en) * 2001-02-15 2007-04-17 Sony Corporation Checkerboard buffer using two-dimensional buffer pages and using memory bank alternation
US7038691B2 (en) * 2001-02-15 2006-05-02 Sony Corporation Two-dimensional buffer pages using memory bank alternation
US6795079B2 (en) * 2001-02-15 2004-09-21 Sony Corporation Two-dimensional buffer pages
US20030058368A1 (en) * 2001-09-24 2003-03-27 Mark Champion Image warping using pixel pages
US9058292B2 (en) 2004-12-29 2015-06-16 Intel Corporation System and method for one step address translation of graphics addresses in virtualization
US7444583B2 (en) * 2005-05-27 2008-10-28 Microsoft Corporation Standard graphics specification and data binding
US7512752B2 (en) 2005-05-31 2009-03-31 Broadcom Corporation Systems, methods, and apparatus for pixel fetch request interface
US7831780B2 (en) * 2005-06-24 2010-11-09 Nvidia Corporation Operating system supplemental disk caching system and method
US7616218B1 (en) * 2005-12-05 2009-11-10 Nvidia Corporation Apparatus, system, and method for clipping graphics primitives
US8593474B2 (en) * 2005-12-30 2013-11-26 Intel Corporation Method and system for symmetric allocation for a shared L2 mapping cache
US8347064B1 (en) 2006-09-19 2013-01-01 Nvidia Corporation Memory access techniques in an aperture mapped memory space
US8601223B1 (en) * 2006-09-19 2013-12-03 Nvidia Corporation Techniques for servicing fetch requests utilizing coalesing page table entries
US8352709B1 (en) 2006-09-19 2013-01-08 Nvidia Corporation Direct memory access techniques that include caching segmentation data
US8543792B1 (en) 2006-09-19 2013-09-24 Nvidia Corporation Memory access techniques including coalesing page table entries
US7840732B2 (en) * 2006-09-25 2010-11-23 Honeywell International Inc. Stacked card address assignment
US8707011B1 (en) 2006-10-24 2014-04-22 Nvidia Corporation Memory access techniques utilizing a set-associative translation lookaside buffer
US8700883B1 (en) 2006-10-24 2014-04-15 Nvidia Corporation Memory access techniques providing for override of a page table
US8347065B1 (en) * 2006-11-01 2013-01-01 Glasco David B System and method for concurrently managing memory access requests
US8533425B1 (en) 2006-11-01 2013-09-10 Nvidia Corporation Age based miss replay system and method
US8706975B1 (en) 2006-11-01 2014-04-22 Nvidia Corporation Memory access management block bind system and method
US8504794B1 (en) 2006-11-01 2013-08-06 Nvidia Corporation Override system and method for memory access management
US8607008B1 (en) 2006-11-01 2013-12-10 Nvidia Corporation System and method for independent invalidation on a per engine basis
US8700865B1 (en) 2006-11-02 2014-04-15 Nvidia Corporation Compressed data access system and method
US20080276067A1 (en) * 2007-05-01 2008-11-06 Via Technologies, Inc. Method and Apparatus for Page Table Pre-Fetching in Zero Frame Display Channel
US8719547B2 (en) * 2009-09-18 2014-05-06 Intel Corporation Providing hardware support for shared virtual memory between local and remote physical memory
US10146545B2 (en) 2012-03-13 2018-12-04 Nvidia Corporation Translation address cache for a microprocessor
US9880846B2 (en) 2012-04-11 2018-01-30 Nvidia Corporation Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries
US10241810B2 (en) 2012-05-18 2019-03-26 Nvidia Corporation Instruction-optimizing processor with branch-count table in hardware
US20140189310A1 (en) 2012-12-27 2014-07-03 Nvidia Corporation Fault detection in instruction translations
US10108424B2 (en) 2013-03-14 2018-10-23 Nvidia Corporation Profiling code portions to generate translations
US20140365930A1 (en) * 2013-06-10 2014-12-11 Hewlett-Packard Development Company, L.P. Remote display of content elements
GB2535823B (en) * 2014-12-24 2021-08-04 Intel Corp Hybrid on-demand graphics translation table shadowing

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Also Published As

Publication number Publication date
EP1141930A1 (en) 2001-10-10
US6362826B1 (en) 2002-03-26
KR20020013832A (ko) 2002-02-21
HK1038091A1 (en) 2002-03-01
AU3470700A (en) 2000-08-01
JP2002535763A (ja) 2002-10-22
WO2000042594A9 (en) 2002-03-28
CN1347545A (zh) 2002-05-01
US6650332B2 (en) 2003-11-18
EP1141930B1 (en) 2008-05-14
DE60038871D1 (de) 2008-06-26
WO2000042594A1 (en) 2000-07-20
KR100433499B1 (ko) 2004-05-31
US20020075271A1 (en) 2002-06-20
TWI250482B (en) 2006-03-01
CN1135477C (zh) 2004-01-21

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