JP4533855B2 - シリコンオンナッシング金属酸化物半導体電界效果トランジスタ及びその製造方法 - Google Patents
シリコンオンナッシング金属酸化物半導体電界效果トランジスタ及びその製造方法 Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims description 186
- 239000010703 silicon Substances 0.000 title claims description 186
- 238000004519 manufacturing process Methods 0.000 title claims description 49
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 230000005669 field effect Effects 0.000 title claims description 20
- 229910044991 metal oxide Inorganic materials 0.000 title claims description 15
- 150000004706 metal oxides Chemical class 0.000 title claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 186
- 239000000758 substrate Substances 0.000 claims description 117
- 238000000034 method Methods 0.000 claims description 55
- 229910052734 helium Inorganic materials 0.000 claims description 49
- 239000001307 helium Substances 0.000 claims description 49
- -1 helium ions Chemical class 0.000 claims description 48
- 239000001257 hydrogen Substances 0.000 claims description 48
- 229910052739 hydrogen Inorganic materials 0.000 claims description 48
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 45
- 230000008569 process Effects 0.000 claims description 45
- 238000002955 isolation Methods 0.000 claims description 30
- 238000000137 annealing Methods 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 230000000903 blocking effect Effects 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 19
- 230000010354 integration Effects 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Description
Malgorzata Jurczak et. al.,"Silicon−On−Nothing (SON)− an innovative Process for Advanced CMOS", IEEE Transactions on Electron Devices,Vol.47,No.11,pp.2179−2187、(2000)
先ず、図5に示すように、素子分離絶縁膜110、ゲート電極130、ソース領域140及びドレイン領域141を覆うようにシリコン基板100の全面にシリコン窒化膜142を蒸着して形成する。シリコン窒化膜142は後続の工程で水素またはヘリウムイオン143を注入した後、水素またはヘリウムがシリコン基板100に形成されたブリスター150,151から外部に拡散してしまうことを阻む阻止層の役目をする。
模造ゲート203と犠牲絶縁膜202をとり除いてからは、図15に示すように、ゲート絶縁膜220とゲート物質231を順に積層して形成する。そして、図16に示すように、蒸着されたゲート物質231をパターニングしてゲート電極230を形成する。
11,101,201 シリコンチャンネル
20,140,240 ソース領域
21,141,241 ドレイン領域
30 基板絶縁膜
40,120,220 ゲート絶縁膜
50,130,230 ゲート電極
110 素子分離絶縁膜
210 スクリーン酸化膜
150,151,250 ブリスター
143,204 水素またはヘリウムイオン
Claims (15)
- シリコン基板の上部両側に形成された素子分離絶縁膜と、
前記素子分離絶縁膜の間のシリコン基板表面に順に形成されたゲート絶縁膜とゲート電極と、
前記ゲート絶縁膜と前記素子分離絶縁膜の間のシリコン基板上部に形成されたソース領域とドレイン領域と、
前記ゲート絶縁膜下部のシリコン基板内部に形成されたブリスターと、
前記ブリスターと前記ソース領域及びドレイン領域によって取り囲まれるシリコン基板内部のシリコンチャンネルであって、前記ブリスターによって張力ストレスが加えられるシリコンチャンネルとを含み、
前記ブリスターは水素またはヘリウムイオンで形成された
ことを特徴とするシリコンオンナッシング金属酸化物半導体電界效果トランジスタ。 - 前記ソース領域やドレイン領域下部のシリコン基板内部に形成されたブリスターを追加で含む請求項1に記載のシリコンオンナッシング金属酸化物半導体電界效果トランジスタ。
- シリコン基板の上部両側に形成されたソース領域とドレイン領域と、
前記ソース領域及びドレイン領域を覆うように形成されたスクリーン酸化膜と、
前記スクリーン酸化膜の間のシリコン基板内部に形成されたブリスターと、
前記ブリスターの上部に位置して、両側が前記ソース領域及びドレイン領域と接して形成され、前記ブリスターによって張力ストレスが加えられるシリコンチャンネルと、
前記シリコンチャンネルの上部に順に形成されたゲート絶縁膜とゲート電極とを含み、
前記ブリスターは水素またはヘリウムイオンで形成されたことを特徴とするシリコンオンナッシング金属酸化物半導体電界效果トランジスタ。 - 前記ブリスターは比誘電率が1である請求項1または3記載のシリコンオンナッシング金属酸化物半導体電界效果トランジスタ。
- (a)シリコン基板の上部両側に素子分離絶縁膜を形成する段階と、
(b)前記素子分離絶縁膜の間のシリコン基板表面に順にゲート絶縁膜とゲート電極を形成する段階と、
(c)前記ゲート絶縁膜と前記素子分離絶縁膜の間のシリコン基板上部にソース領域とドレイン領域を形成する段階と、
(d)前記ゲート絶縁膜下部のシリコン基板内部にブリスターを形成して、前記ブリスターと前記ソース領域及びドレイン領域によって取り囲まれるシリコン基板内部のシリコンチャンネルであって、前記ブリスターによって張力ストレスが加えられるシリコンチャンネルを形成する段階を含み、
前記ブリスターは水素またはヘリウムイオンで形成される
ことを特徴とするシリコンオンナッシング金属酸化物半導体電界效果トランジスタの製造方法。 - 前記(d)段階で、
前記ブリスターが、前記ゲート絶縁膜の下部に位置するシリコン基板内部に水素またはヘリウムイオンを注入した後アニーリングして形成される
請求項5記載のシリコンオンナッシング金属酸化物半導体電界效果トランジスタの製造方法。 - 前記(d)段階で、
前記ソース領域やドレイン領域下部に追加的にブリスターを形成する請求項5記載のシリコンオンナッシング金属酸化物半導体電界效果トランジスタの製造方法。 - 前記(c)段階で、
前記ソース領域及びドレイン領域を形成した後、前記素子分離絶縁膜と、前記ゲート電極、前記ソース領域及びドレイン領域を覆うようにシリコン窒化膜を形成して、前記(d)段階でシリコン基板内部に形成される前記ブリスターから気体が外部に拡散することを阻む阻止層となるようにして、
前記(d)段階で、
前記ブリスター及び前記シリコンチャンネルを形成した後、前記形成されたシリコン窒化膜をとり除く請求項5記載のシリコンオンナッシング金属酸化物半導体電界效果トランジスタの製造方法。 - (a)シリコン基板の上部両側にソース領域とドレイン領域を形成する段階と、
(b)前記ソース領域及びドレイン領域を覆うようにスクリーン酸化膜を形成する段階と、
(c)前記スクリーン酸化膜の間のシリコン基板内部にブリスターを形成して、前記ブリスターの上部に、両側が前記ソース領域及びドレイン領域と接し、前記ブリスターによって張力ストレスが加えられるシリコンチャンネルを形成する段階と、
(d)前記シリコンチャンネルの上部にゲート絶縁膜とゲート電極を順に形成する段階とを含み、
前記ブリスターは水素またはヘリウムイオンで形成されることを特徴とするシリコンオンナッシング金属酸化物半導体電界效果トランジスタの製造方法。 - 前記(c)段階で、
前記ブリスターが、前記スクリーン酸化膜の間のシリコン基板内部に水素またはヘリウムイオンを注入した後アニーリングして形成される請求項9記載のシリコンオンナッシング金属酸化物半導体電界效果トランジスタの製造方法。 - 前記(c)段階で、
前記ブリスターを形成する水素またはヘリウムイオンは前記スクリーン酸化膜と、前記スクリーン酸化膜の間のシリコン基板上部に形成された模造ゲートの間に生成された段差によって、水素またはヘリウムイオンを注入する深さが調節され、前記スクリーン酸化膜の間のシリコン基板内部にだけ選択的に水素またはヘリウムイオンが注入される請求項10記載のシリコンオンナッシング金属酸化物半導体電界效果トランジスタの製造方法。 - 前記(a)段階で、
前記ソース領域とドレイン領域の間のシリコン基板表面に順に犠牲絶縁膜と模造ゲートを形成して、前記模造ゲートをマスクにして前記ソース領域とドレイン領域を形成して、
前記(c)段階で、
前記ブリスター及び前記シリコンチャンネルを形成した後、前記模造ゲートと前記犠牲絶縁膜を順に蝕刻する請求項9記載のシリコンオンナッシング金属酸化物半導体電界效果トランジスタの製造方法。 - 前記素子分離絶縁膜やスクリーン酸化膜を酸化工程または化学気相成長工程で形成する請求項5または9記載のシリコンオンナッシング金属酸化物半導体電界效果トランジスタの製造方法。
- 注入エネルギーを調節して前記水素またはヘリウムイオンが前記シリコン基板内部に注入される位置や深さを決める請求項6または10記載のシリコンオンナッシング金属酸化物半導体電界效果トランジスタの製造方法。
- 前記シリコン基板内部に注入された水素またはヘリウムイオンが前記ブリスターを形成するようにアニーリングする温度は400℃以上800℃以下である請求項6または10記載のシリコンオンナッシング金属酸化物半導体電界效果トランジスタの製造方法。
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JP2007027232A (ja) * | 2005-07-13 | 2007-02-01 | Seiko Epson Corp | 半導体装置及びその製造方法 |
US20070128810A1 (en) * | 2005-12-07 | 2007-06-07 | Ching-Hung Kao | Ultra high voltage MOS transistor device and method of making the same |
US8138523B2 (en) | 2009-10-08 | 2012-03-20 | International Business Machines Corporation | Semiconductor device having silicon on stressed liner (SOL) |
CN101986435B (zh) * | 2010-06-25 | 2012-12-19 | 中国科学院上海微系统与信息技术研究所 | 防止浮体及自加热效应的mos器件结构的制造方法 |
US8610211B2 (en) | 2010-07-23 | 2013-12-17 | International Business Machines Corporation | Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure |
CN102856375B (zh) * | 2011-06-27 | 2015-05-20 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
US8779554B2 (en) | 2012-03-30 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOSFETs with channels on nothing and methods for forming the same |
CN103531471B (zh) * | 2012-07-03 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | 一种mosfet及其制备方法 |
US9136328B2 (en) | 2012-10-09 | 2015-09-15 | Infineon Technologies Dresden Gmbh | Silicon on nothing devices and methods of formation thereof |
CN105261587A (zh) * | 2014-07-16 | 2016-01-20 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US10516050B2 (en) * | 2016-07-29 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming stressor, semiconductor device having stressor, and method for forming the same |
DE102016119799B4 (de) * | 2016-10-18 | 2020-08-06 | Infineon Technologies Ag | Integrierte schaltung, die einen vergrabenen hohlraum enthält, und herstellungsverfahren |
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JP2000012858A (ja) * | 1998-04-24 | 2000-01-14 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2003332540A (ja) * | 2002-05-08 | 2003-11-21 | Nec Corp | 半導体基板の製造方法、半導体装置の製造方法、および半導体基板、半導体装置 |
JP2004349702A (ja) * | 2003-05-20 | 2004-12-09 | Sharp Corp | シリコン・オン・ナッシング製造プロセス |
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JP4405201B2 (ja) | 2003-07-29 | 2010-01-27 | 独立行政法人科学技術振興機構 | 二次元パターニング方法ならびにそれを用いた電子デバイスの作製方法 |
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JP2000012858A (ja) * | 1998-04-24 | 2000-01-14 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2003332540A (ja) * | 2002-05-08 | 2003-11-21 | Nec Corp | 半導体基板の製造方法、半導体装置の製造方法、および半導体基板、半導体装置 |
JP2004349702A (ja) * | 2003-05-20 | 2004-12-09 | Sharp Corp | シリコン・オン・ナッシング製造プロセス |
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