JP4509521B2 - 自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム - Google Patents

自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム Download PDF

Info

Publication number
JP4509521B2
JP4509521B2 JP2003343302A JP2003343302A JP4509521B2 JP 4509521 B2 JP4509521 B2 JP 4509521B2 JP 2003343302 A JP2003343302 A JP 2003343302A JP 2003343302 A JP2003343302 A JP 2003343302A JP 4509521 B2 JP4509521 B2 JP 4509521B2
Authority
JP
Japan
Prior art keywords
layer
lower layer
line pattern
priority direction
extending
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2003343302A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005109336A5 (https=
JP2005109336A (ja
Inventor
裕三 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2003343302A priority Critical patent/JP4509521B2/ja
Priority to TW093128682A priority patent/TWI253144B/zh
Priority to US10/951,858 priority patent/US7146597B2/en
Publication of JP2005109336A publication Critical patent/JP2005109336A/ja
Publication of JP2005109336A5 publication Critical patent/JP2005109336A5/ja
Application granted granted Critical
Publication of JP4509521B2 publication Critical patent/JP4509521B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
JP2003343302A 2003-10-01 2003-10-01 自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム Expired - Lifetime JP4509521B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003343302A JP4509521B2 (ja) 2003-10-01 2003-10-01 自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム
TW093128682A TWI253144B (en) 2003-10-01 2004-09-22 Automatic design method, automatic design device, reticule set, semiconductor integrated circuit and recording media
US10/951,858 US7146597B2 (en) 2003-10-01 2004-09-27 CAD method for arranging via-holes, a CAD tool, photomasks produced by the CAD method, a semiconductor integrated circuit manufactured with photomasks and a computer program product for executing the CAD method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003343302A JP4509521B2 (ja) 2003-10-01 2003-10-01 自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム

Publications (3)

Publication Number Publication Date
JP2005109336A JP2005109336A (ja) 2005-04-21
JP2005109336A5 JP2005109336A5 (https=) 2010-01-21
JP4509521B2 true JP4509521B2 (ja) 2010-07-21

Family

ID=34537317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003343302A Expired - Lifetime JP4509521B2 (ja) 2003-10-01 2003-10-01 自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム

Country Status (3)

Country Link
US (1) US7146597B2 (https=)
JP (1) JP4509521B2 (https=)
TW (1) TWI253144B (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4801333B2 (ja) * 2004-07-23 2011-10-26 パナソニック株式会社 電源配線構造および該電源配線構造を備えた半導体集積回路
JP4901302B2 (ja) * 2006-05-26 2012-03-21 株式会社東芝 半導体集積回路
JP2010003712A (ja) * 2007-08-09 2010-01-07 Renesas Technology Corp 半導体装置、半導体装置の配置配線方法、及びデータ処理システム
CN102622469A (zh) * 2012-02-20 2012-08-01 浙江工业大学 一种基于相似度的产品可拓分类知识挖掘方法
US8631375B2 (en) * 2012-04-10 2014-01-14 International Business Machines Corporation Via selection in integrated circuit design
CN103093051B (zh) * 2013-01-17 2015-10-07 浙江工业大学 一种产品性能传导知识挖掘方法
CN103136349A (zh) * 2013-02-22 2013-06-05 浙江工业大学 一种产品性能传导知识挖掘方法
CN105097800B (zh) * 2015-08-31 2018-09-07 京东方科技集团股份有限公司 一种显示基板、显示面板和显示装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61140149A (ja) * 1984-12-12 1986-06-27 Hitachi Comput Eng Corp Ltd 半導体集積回路装置
US5618744A (en) * 1992-09-22 1997-04-08 Fujitsu Ltd. Manufacturing method and apparatus of a semiconductor integrated circuit device
KR100273703B1 (ko) * 1997-12-12 2001-03-02 윤종용 콘택관련 결함 및 콘택저항을 감소하기 위한 반도체 장치의 콘택구조 및 그 제조 방법
US6349403B1 (en) * 1998-12-18 2002-02-19 Synopsys, Inc. Interative, gridless, cost-based layer assignment coarse router for computer controlled IC design
US6507941B1 (en) * 1999-04-28 2003-01-14 Magma Design Automation, Inc. Subgrid detailed routing
JP4008629B2 (ja) * 1999-09-10 2007-11-14 株式会社東芝 半導体装置、その設計方法、及びその設計プログラムを格納したコンピュータ読み取り可能な記録媒体
JP3822009B2 (ja) * 1999-11-17 2006-09-13 株式会社東芝 自動設計方法、露光用マスクセット、半導体集積回路装置、半導体集積回路装置の製造方法、および自動設計プログラムを記録した記録媒体
JP3390393B2 (ja) * 1999-12-21 2003-03-24 エヌイーシーマイクロシステム株式会社 自動配置配線システムの配線方法および自動配置配線システムの配線方法を記録した記録媒体
JP2001284455A (ja) * 2000-03-29 2001-10-12 Kawasaki Steel Corp 自動レイアウト方法及び装置ならびにそれらを用いた半導体集積回路
JP2001291844A (ja) * 2000-04-06 2001-10-19 Fujitsu Ltd 半導体装置及びその製造方法
US6900540B1 (en) * 2000-12-07 2005-05-31 Cadence Design Systems, Inc. Simulating diagonal wiring directions using Manhattan directional wires
US6858928B1 (en) * 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Multi-directional wiring on a single metal layer
JP2002329783A (ja) * 2001-04-27 2002-11-15 Toshiba Corp 配線パターンの自動レイアウト方法、レイアウトパターンの光学補正方法、自動レイアウト方法と光学補正方法に基づいて製造される半導体集積回路、および自動レイアウト光学補正プログラムを記録した記録媒体
JP2003031662A (ja) * 2001-07-16 2003-01-31 Mitsubishi Electric Corp 半導体集積回路の配線方法、半導体集積回路、及び配線方法をコンピュータに実行させるプログラム
JP2003218115A (ja) * 2002-01-23 2003-07-31 Hitachi Ltd ヴィアを有する配線構造

Also Published As

Publication number Publication date
TWI253144B (en) 2006-04-11
US7146597B2 (en) 2006-12-05
TW200519668A (en) 2005-06-16
US20050108673A1 (en) 2005-05-19
JP2005109336A (ja) 2005-04-21

Similar Documents

Publication Publication Date Title
CN101326635B (zh) 半导体器件及其制造方法
JP4307664B2 (ja) 半導体装置
US5449637A (en) Method of producing low and high voltage MOSFETs with reduced masking steps
US6949801B2 (en) Dual trench isolation using single critical lithographic patterning
TWI388005B (zh) 利用二次切割來消除多晶矽單向線端短縮
KR100281182B1 (ko) 반도체 장치의 자기 정렬 콘택 형성 방법
JP2010524247A (ja) 半導体デバイス構造
JP4509521B2 (ja) 自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム
US20020081799A1 (en) Contact fabrication method for semiconductor device
JP2010245173A (ja) 半導体装置の製造方法
US5916733A (en) Method of fabricating a semiconductor device
JP2000124332A (ja) 半導体装置の製造方法及び半導体装置
US6974999B2 (en) Semiconductor device and method of manufacturing the same
US6074923A (en) Method of fabricating metal-oxide-semiconductor transistor
JPH08148658A (ja) 半導体記憶装置およびその製造方法
CN100527381C (zh) 制造快闪存储器件的方法
JP2007149768A (ja) 半導体装置の製造方法
KR100470390B1 (ko) 에스램소자 제조시 다마신을 이용한 국부배선 스페이스최소화방법
JP2006040916A (ja) 半導体装置及びその製造方法
KR100863421B1 (ko) 반도체 메모리 장치의 워드라인 형성 방법
KR20020005389A (ko) 트렌치 분리를 갖는 반도체 장치의 제조 방법
CN120784211A (zh) 半导体结构及其制作方法
KR100258202B1 (ko) 반도체 장치의 제조 방법
JPH07288288A (ja) 集積回路装置の配線方法
KR20000007480A (ko) 반도체 소자 및 그 제조방법

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060315

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090529

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091201

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20091201

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20091214

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100105

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100305

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100406

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100428

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130514

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4509521

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130514

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140514

Year of fee payment: 4

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313115

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

EXPY Cancellation because of completion of term