JP2005109336A5 - - Google Patents

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Publication number
JP2005109336A5
JP2005109336A5 JP2003343302A JP2003343302A JP2005109336A5 JP 2005109336 A5 JP2005109336 A5 JP 2005109336A5 JP 2003343302 A JP2003343302 A JP 2003343302A JP 2003343302 A JP2003343302 A JP 2003343302A JP 2005109336 A5 JP2005109336 A5 JP 2005109336A5
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Japan
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layer
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JP2003343302A
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English (en)
Japanese (ja)
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JP4509521B2 (ja
JP2005109336A (ja
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Priority to JP2003343302A priority Critical patent/JP4509521B2/ja
Priority claimed from JP2003343302A external-priority patent/JP4509521B2/ja
Priority to TW093128682A priority patent/TWI253144B/zh
Priority to US10/951,858 priority patent/US7146597B2/en
Publication of JP2005109336A publication Critical patent/JP2005109336A/ja
Publication of JP2005109336A5 publication Critical patent/JP2005109336A5/ja
Application granted granted Critical
Publication of JP4509521B2 publication Critical patent/JP4509521B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2003343302A 2003-10-01 2003-10-01 自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム Expired - Lifetime JP4509521B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003343302A JP4509521B2 (ja) 2003-10-01 2003-10-01 自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム
TW093128682A TWI253144B (en) 2003-10-01 2004-09-22 Automatic design method, automatic design device, reticule set, semiconductor integrated circuit and recording media
US10/951,858 US7146597B2 (en) 2003-10-01 2004-09-27 CAD method for arranging via-holes, a CAD tool, photomasks produced by the CAD method, a semiconductor integrated circuit manufactured with photomasks and a computer program product for executing the CAD method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003343302A JP4509521B2 (ja) 2003-10-01 2003-10-01 自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム

Publications (3)

Publication Number Publication Date
JP2005109336A JP2005109336A (ja) 2005-04-21
JP2005109336A5 true JP2005109336A5 (https=) 2010-01-21
JP4509521B2 JP4509521B2 (ja) 2010-07-21

Family

ID=34537317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003343302A Expired - Lifetime JP4509521B2 (ja) 2003-10-01 2003-10-01 自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム

Country Status (3)

Country Link
US (1) US7146597B2 (https=)
JP (1) JP4509521B2 (https=)
TW (1) TWI253144B (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4801333B2 (ja) * 2004-07-23 2011-10-26 パナソニック株式会社 電源配線構造および該電源配線構造を備えた半導体集積回路
JP4901302B2 (ja) * 2006-05-26 2012-03-21 株式会社東芝 半導体集積回路
JP2010003712A (ja) * 2007-08-09 2010-01-07 Renesas Technology Corp 半導体装置、半導体装置の配置配線方法、及びデータ処理システム
CN102622469A (zh) * 2012-02-20 2012-08-01 浙江工业大学 一种基于相似度的产品可拓分类知识挖掘方法
US8631375B2 (en) * 2012-04-10 2014-01-14 International Business Machines Corporation Via selection in integrated circuit design
CN103093051B (zh) * 2013-01-17 2015-10-07 浙江工业大学 一种产品性能传导知识挖掘方法
CN103136349A (zh) * 2013-02-22 2013-06-05 浙江工业大学 一种产品性能传导知识挖掘方法
CN105097800B (zh) * 2015-08-31 2018-09-07 京东方科技集团股份有限公司 一种显示基板、显示面板和显示装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61140149A (ja) * 1984-12-12 1986-06-27 Hitachi Comput Eng Corp Ltd 半導体集積回路装置
US5618744A (en) * 1992-09-22 1997-04-08 Fujitsu Ltd. Manufacturing method and apparatus of a semiconductor integrated circuit device
KR100273703B1 (ko) * 1997-12-12 2001-03-02 윤종용 콘택관련 결함 및 콘택저항을 감소하기 위한 반도체 장치의 콘택구조 및 그 제조 방법
US6349403B1 (en) * 1998-12-18 2002-02-19 Synopsys, Inc. Interative, gridless, cost-based layer assignment coarse router for computer controlled IC design
US6507941B1 (en) * 1999-04-28 2003-01-14 Magma Design Automation, Inc. Subgrid detailed routing
JP4008629B2 (ja) * 1999-09-10 2007-11-14 株式会社東芝 半導体装置、その設計方法、及びその設計プログラムを格納したコンピュータ読み取り可能な記録媒体
JP3822009B2 (ja) * 1999-11-17 2006-09-13 株式会社東芝 自動設計方法、露光用マスクセット、半導体集積回路装置、半導体集積回路装置の製造方法、および自動設計プログラムを記録した記録媒体
JP3390393B2 (ja) * 1999-12-21 2003-03-24 エヌイーシーマイクロシステム株式会社 自動配置配線システムの配線方法および自動配置配線システムの配線方法を記録した記録媒体
JP2001284455A (ja) * 2000-03-29 2001-10-12 Kawasaki Steel Corp 自動レイアウト方法及び装置ならびにそれらを用いた半導体集積回路
JP2001291844A (ja) * 2000-04-06 2001-10-19 Fujitsu Ltd 半導体装置及びその製造方法
US6900540B1 (en) * 2000-12-07 2005-05-31 Cadence Design Systems, Inc. Simulating diagonal wiring directions using Manhattan directional wires
US6858928B1 (en) * 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Multi-directional wiring on a single metal layer
JP2002329783A (ja) * 2001-04-27 2002-11-15 Toshiba Corp 配線パターンの自動レイアウト方法、レイアウトパターンの光学補正方法、自動レイアウト方法と光学補正方法に基づいて製造される半導体集積回路、および自動レイアウト光学補正プログラムを記録した記録媒体
JP2003031662A (ja) * 2001-07-16 2003-01-31 Mitsubishi Electric Corp 半導体集積回路の配線方法、半導体集積回路、及び配線方法をコンピュータに実行させるプログラム
JP2003218115A (ja) * 2002-01-23 2003-07-31 Hitachi Ltd ヴィアを有する配線構造

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