JP4485119B2 - Display device - Google Patents

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Publication number
JP4485119B2
JP4485119B2 JP2002327498A JP2002327498A JP4485119B2 JP 4485119 B2 JP4485119 B2 JP 4485119B2 JP 2002327498 A JP2002327498 A JP 2002327498A JP 2002327498 A JP2002327498 A JP 2002327498A JP 4485119 B2 JP4485119 B2 JP 4485119B2
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Prior art keywords
electrode
transistor
gate
electrically connected
supply line
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JP2002327498A
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JP2003216110A5 (en
JP2003216110A (en
Inventor
肇 木村
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株式会社半導体エネルギー研究所
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Priority to JP2001-348032 priority
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Priority to JP2002327498A priority patent/JP4485119B2/en
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a structure of a semiconductor device having a transistor. The present invention also relates to a structure of an active matrix display device including a semiconductor device having a thin film transistor (hereinafter referred to as TFT) manufactured over an insulator such as glass or plastic. The present invention also relates to an electronic device using such a display device.
[0002]
[Prior art]
In recent years, development of display devices using light-emitting elements such as electroluminescence (EL) elements has been activated. The light-emitting element has high visibility because it emits light by itself, and is suitable for thinning because it does not require a backlight necessary for a liquid crystal display (LCD) or the like, and has almost no restriction on the viewing angle.
[0003]
Here, the EL element refers to an element having a light emitting layer from which luminescence generated by applying an electric field can be obtained. In this light emitting layer, there are light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. May be any of the light emitting forms described above.
[0004]
An EL element is configured such that a light emitting layer is sandwiched between a pair of electrodes (anode and cathode), and usually has a laminated structure. A typical example is a stacked structure of “anode / hole transport layer / light emitting layer / electron transport layer / cathode” proposed by Tang et al. Of Eastman Kodak Company. This structure has a very high luminous efficiency, and this structure is employed in many EL devices that are currently being studied.
[0005]
In addition to this, between the anode and the cathode, “hole injection layer / hole transport layer / light emitting layer / electron transport layer” or “hole injection layer / hole transport layer / light emitting layer / electron transport”. There is a structure of stacking in the order of “layer / electron injection layer”. As the structure of the EL element used in the light emitting device of the present invention, any of the above structures may be adopted. Further, a fluorescent pigment or the like may be doped into the light emitting layer.
[0006]
In this specification, in the EL element, all layers provided between the anode and the cathode are collectively referred to as an EL layer. Therefore, the above-described hole injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are all included in the EL element, and a light emitting element including an anode, an EL layer, and a cathode is referred to as an EL element. Call.
[0007]
2A and 2B illustrate a pixel structure in a general light-emitting device. Note that an EL display device is taken as an example of a typical light-emitting device. 2A and 2B include a source signal line 201, a gate signal line 202, a switching TFT 203, a driving TFT 204, a capacitor element (capacitor means) 205, a current supply line 206, an EL element 207, and a power source. It has a line 208. 2A, the driving TFT 204 is a P-channel type, and in FIG. 2B, the driving TFT 204 is an N-channel type. Since the switching TFT 203 is a TFT that functions as a switch when inputting a video signal to a pixel, the polarity thereof does not matter here.
[0008]
The connection relationship of each part will be described. Here, the TFT has three terminals of a gate, a source, and a drain. However, the source and drain cannot be clearly distinguished because of the structure of the TFT. Therefore, when describing connection between elements, one of a source and a drain is referred to as a first electrode, and the other is referred to as a second electrode. Regarding the ON / OFF of a TFT, when it is necessary to explain the potential of each terminal (the voltage between the gate and the source of a TFT), it is expressed as a source, a drain, or the like.
[0009]
In this specification, the TFT is ON means that the voltage between the gate and the source of the TFT exceeds the threshold value and a current flows between the source and the drain. If the TFT is OFF Is a state in which the gate-source voltage of the TFT is below its threshold value, and no current flows between the source and drain.
[0010]
The switching TFT 203 has a gate electrode connected to the gate signal line 202, a first electrode connected to the source signal line 201, and a second electrode connected to the gate electrode of the driving TFT 204. The first electrode of the driving TFT 204 is connected to the current supply line 206, and the second electrode is connected to the anode (Anode) of the EL element 207. A cathode of the EL element 207 is connected to the power supply line 208. The current supply line 206 and the power supply line 208 have a potential difference from each other. Further, in order to hold the gate-source voltage of the driving TFT 204, a capacitor element 205 may be provided between the gate electrode of the driving TFT 204 and a certain potential, for example, the current supply line 206.
[0011]
When a pulse is input to the gate signal line 202 and the switching TFT 203 is turned on, the video signal output to the source signal line 201 is input to the gate electrode of the driving TFT 204. The gate-source voltage of the driving TFT 204 is determined according to the potential of the input video signal, and the current flowing between the source and drain of the driving TFT 204 (hereinafter referred to as drain current) is determined. This current is supplied to the EL element 207 to emit light.
[0012]
In addition, a display device in which a TFT or the like is formed on a substrate and a pixel portion and a peripheral circuit are integrally formed is applied to mobile devices that are remarkably popular, taking advantage of small size and light weight. On the other hand, TFT fabrication is performed through many processes such as element formation by repeated film formation and etching, and addition of an impurity element for imparting conductivity to the semiconductor. Become.
[0013]
Therefore, if the pixel portion and the peripheral circuit are formed of a single polarity TFT, a part of the impurity element adding step can be omitted. As an example of a pixel configured using a single polarity TFT, one shown in FIG. 8 has been proposed (for example, see Non-Patent Document 1).
[0014]
[Non-Patent Document 1]
Kanicki, JH.Kim, JYNahm, Y.He, and R.Hattori "Amorphous Silicon Thin-Film Transistors Based Active-Matrix Organic Light-Emitting Displays" Asia Display / IDW (ASIA DISPLAY / IDW) 2001 p. 315-318
[0015]
The pixel shown in FIG. 8 includes a source signal line 801, a gate signal line 802, a switching TFT 803, a driving TFT 804, an active resistance TFT 805, a capacitor element 806, a current supply line 807, an EL element 808, and a power supply line 809. N-channel TFTs are used for the TFTs 803 to 805.
[0016]
The gate electrode of the switching TFT 803 is connected to the gate signal line 802, the first electrode is connected to the source signal line 801, and the second electrode is connected to the gate electrode of the driving TFT 804. The first electrode of the driving TFT 804 is connected to the anode of the EL element 808, and the second electrode is connected to the first electrode of the active resistance TFT 805. The gate electrode and the second electrode of the active resistance TFT 805 are connected to each other and connected to the current supply line 807. The cathode of the EL element 808 is connected to the power supply line 809 and has a potential difference from the current supply line 807. The capacitor 806 is provided between the gate electrode of the driving TFT 804 and the current supply line 807 and holds the potential of a signal applied to the gate electrode of the driving TFT 804.
[0017]
[Problems to be solved by the invention]
Here, consider the operation in the case where an N-channel TFT is used as the driving TFT as shown in FIGS. 2C illustrates only the components of the current supply line 206, the driving TFT 204, the EL element 207, and the power supply line 208 in the pixel shown in FIGS. 2A and 2B. Since the driving TFT 204 is an N-channel type, the side connected to the anode of the EL element 207 is the source, and the side connected to the current supply line is the drain.
[0018]
Now, the potential of the current supply line 206 is V DD The anode potential of the EL element 207 is V A Similarly, the cathode potential is V C The potential of the gate electrode of the driving TFT 204 is V Sig , The gate-source voltage V of the driving TFT 204 GS Is V GS = (V Sig -V A ) And the anode-cathode voltage V of the EL element 207 EL Is V EL = (V A -V C ).
[0019]
FIG. 2D shows voltage / current characteristics of the driving TFT 204 and the EL element 207. The intersection of the voltage / current curve of the driving TFT 204 and the voltage / current curve of the EL element 207 is the operating point. The value of the current flowing through the EL element 207 and the potential V of the anode of the EL element A Will be determined. Now, when the voltage / current curve of the EL element 207 is represented by 211 and the voltage / current curve of the TFT 204 is represented by 213, the operating point is 215, whereby the current value and V A = V A1 Will be determined. The gate-source voltage V of the driving TFT 204 at this time GS Is V GS = (V Sig -V A1 ).
[0020]
Consider a case where the EL element 207 is deteriorated. When the EL element 207 deteriorates, the lighting start voltage increases, and the curve shifts to the right and is indicated by 212. Here, if the driving TFT 204 is operating in the saturation region and the gate-source voltage does not change due to the deterioration of the EL element 207, the operating point shifts to 216. That is, V A = V A2 It becomes. In this case, even if the source-drain voltage of the driving TFT 204 changes, the current value does not change greatly, so the luminance does not change so much. However, since an N-channel TFT is used as the driving TFT 204 and the side connected to the anode of the EL element 207 is the source, the gate-source voltage V of the driving TFT 204 is GS Is V GS = (V Sig -V A2 ) And it gets smaller. Therefore, the voltage / current curve of the driving TFT 204 at this time is as indicated by 214. Therefore, the operating point is 217. In other words, due to the deterioration of the EL element 207, the source potential of the driving TFT 204 is increased and the gate-source voltage is decreased, so that the current value is greatly changed, leading to a decrease in luminance.
[0021]
Therefore, in the present invention, a semiconductor device is provided which is configured by using an N-channel TFT as a driving TFT for supplying current to an EL element, and which can solve the problems caused by the deterioration of the EL element as described above. The task is to do.
[0022]
[Means for Solving the Problems]
The main point of the above-described problem is that the anode potential of the EL element, that is, the source potential of the driving TFT increases due to the deterioration of the EL element, and the gate-source voltage of the driving TFT decreases accordingly. .
[0023]
To prevent the current value from changing even when the EL element deteriorates, even if the EL element deteriorates and the potential of the anode of the EL element rises, the gate-source voltage of the driving TFT changes. It is necessary to prevent it from occurring.
[0024]
Therefore, in the present invention, a configuration applying the bootstrap operation is applied to the pixel. A capacitive element (voltage holding means) is provided between the gate and source of the driving TFT, and the potential of the source is fixed to a certain value while the video signal is input to the gate electrode. Then, after inputting the video signal, the gate electrode is brought into a floating state. At this time, if the gate-source voltage of the driving TFT exceeds the threshold value, the driving TFT is turned on, and the capacitive element has the potential (V Sig ) And power line potential (V SS ) And the potential difference. Here, when the fixation of the source potential of the driving TFT is released, a current flows through the EL element (light emitting element), and the potential of the anode, that is, the source potential of the driving TFT increases. Then, the potential of the gate electrode of the driving TFT which is in a floating state is increased by the same amount due to the coupling by the capacitive element disposed between the gate and the source of the driving TFT. Therefore, even when the value of the increase in the potential of the anode varies due to the deterioration of the EL element, the increase can be directly added to the potential of the gate electrode, and the gate-source voltage of the driving TFT can be made constant. .
[0025]
The configuration of the present invention will be described below.
[0026]
The display device of the present invention includes:
A light emitting element;
Voltage holding means for holding a voltage based on the video signal;
A power supply line connected to the light emitting element and the voltage holding means via at least one switching element,
The voltage holding unit has a function of controlling a current supplied to the light emitting element, and the current is a potential difference between a potential of the video signal and a potential of the power supply line.
[0027]
The display device of the present invention includes:
A light emitting element;
Voltage holding means for holding a voltage based on the video signal;
A switching element connected to the voltage holding means;
A power line connected to the switching element;
A transistor connected to the light emitting element and the voltage holding means;
A current supply line connected to the transistor, comprising:
The voltage holding means holds a potential difference between the potential of the video signal and the potential of the power supply line, and controls the gate-source voltage of the transistor;
A current based on a gate-source voltage of the transistor is supplied to the light emitting element from the current supply line.
[0028]
The display device of the present invention includes:
A light emitting element;
Voltage holding means for holding a voltage based on the video signal;
A switching element connected between the voltage holding means and the power line;
A power line connected to the switching element;
A transistor connected to the light emitting element and the voltage holding means;
A current supply line connected to the transistor, comprising:
The voltage holding means holds a potential difference between the potential of the video signal and the potential of the power supply line, and controls the gate-source voltage of the transistor;
A current based on a gate-source voltage of the transistor is supplied to the light emitting element from the current supply line.
[0029]
The display device of the present invention includes:
A first switching element, a second switching element, a transistor, a capacitor, and a light emitting element;
A first electrode of the first switching element is electrically connected to a source signal line, and a second electrode is electrically connected to a gate electrode of the transistor;
The first electrode of the transistor is electrically connected to the first electrode of the second switching element and the first electrode of the light emitting element, and the second electrode is electrically connected to a current supply line.
A second electrode of the second switching element is electrically connected to the first power line;
A second electrode of the light emitting element is electrically connected to a second power supply line;
The capacitor element includes a pixel provided between a gate electrode and a first electrode of the transistor.
[0030]
The display device of the present invention includes:
A first switching element, a third switching element, a transistor, a capacitor, and a light emitting element;
A first electrode of the first switching element is electrically connected to a source signal line, and a second electrode is electrically connected to a gate electrode of the transistor;
The first electrode of the transistor is electrically connected to the first electrode of the second switching element and the first electrode of the light emitting element, and the second electrode is electrically connected to a current supply line.
A second electrode of the second switching element is electrically connected to the first power line;
A second electrode of the light emitting element is electrically connected to a second power supply line;
The capacitor element includes a pixel provided between a gate electrode and a first electrode of the transistor.
[0031]
The display device of the present invention includes:
A first switching element, a third switching element, a transistor, a capacitor, and a light emitting element;
A first electrode of the first switching element is electrically connected to a source signal line, and a second electrode is electrically connected to a gate electrode of the transistor;
The first electrode of the transistor is electrically connected to the first electrode of the second switching element and the first electrode of the light emitting element, and the second electrode is electrically connected to a current supply line.
A second electrode of the second switching element is electrically connected to the first power line;
A second electrode of the light emitting element is electrically connected to a second power supply line;
The capacitive element is provided between a gate electrode and a first electrode of the transistor,
The first electrode of the third switching element is the gate electrode of the transistor, the second electrode is the first electrode of the transistor, the first electrode of the second switching element, and the first electrode of the light emitting element. And a pixel electrically connected to each electrode.
[0032]
The display device of the present invention includes:
A first switching element, a third switching element, a transistor, a capacitor, and a light emitting element;
A first electrode of the first switching element is electrically connected to a source signal line, and a second electrode is electrically connected to a gate electrode of the transistor;
The first electrode of the transistor is electrically connected to the first electrode of the second switching element and the first electrode of the light emitting element, and the second electrode is electrically connected to a current supply line.
A second electrode of the second switching element is electrically connected to the first power line;
A second electrode of the light emitting element is electrically connected to a second power supply line;
The capacitive element is provided between a gate electrode and a first electrode of the transistor,
The first electrode of the third switching element includes a first electrode of the light emitting element, and the second electrode includes a pixel electrically connected to the first power supply line. .
[0033]
The display device of the present invention includes:
When the conductivity type of the transistor is an N-channel type, the current supply line V 1 , Voltage V of the first power line 2 , The second power line voltage V Three Is V 1 > V 2 And V 1 > V Three It may be. In addition, V 2 <V Three It may be.
[0034]
Moreover, the display device of the present invention includes:
When the conductivity type of the transistor is a P-channel type, the current supply line V 1 , The potential V of the first power supply line 2 , The potential V of the second power supply line Three Is V 1 <V 2 And V 1 <V Three It may be. In addition, V 2 > V Three It may be.
[0035]
The display device of the present invention includes:
A display device in which pixels having a source signal line, a gate signal line, a current supply line, first to third transistors, a capacitor, and a light emitting element are provided in a matrix,
The gate electrode of the first transistor is electrically connected to the first gate signal line, and the first electrode is electrically connected to the first electrode of the second transistor and the first electrode of the light emitting element. The second electrode is electrically connected to either the first power supply line or a gate signal line provided in a row not including the pixel,
A gate electrode of the second transistor is electrically connected to a first electrode of the third transistor; a second electrode is electrically connected to the current supply line;
A gate electrode of the third transistor is electrically connected to the second gate signal line; a second electrode is electrically connected to the source signal line;
A second electrode of the light emitting element is electrically connected to a second power line;
The capacitor element is provided between a gate electrode and a first electrode of the second transistor.
[0036]
The display device of the present invention includes:
A display device in which pixels having a source signal line, first and second gate signal lines, a current supply line, first to third transistors, a capacitor element, and a light emitting element are provided in a matrix. There,
The gate electrode of the first transistor is electrically connected to the first gate signal line, and the first electrode is electrically connected to the first electrode of the second transistor and the first electrode of the light emitting element. The second electrode is electrically connected to the first power supply line and either the first gate signal line or the second gate signal line provided in a row not including the pixel;
A gate electrode of the second transistor is electrically connected to a first electrode of the third transistor; a second electrode is electrically connected to the current supply line;
A gate electrode of the third transistor is electrically connected to the second gate signal line; a second electrode is electrically connected to the source signal line;
A second electrode of the light emitting element is electrically connected to a second power line;
The capacitor element is provided between a gate electrode and a first electrode of the second transistor.
[0037]
The display device of the present invention includes:
A display device in which pixels having a source signal line, first to third gate signal lines, a current supply line, first to fourth transistors, a capacitor, and a light-emitting element are provided in a matrix. There,
The gate electrode of the first transistor is electrically connected to the first gate signal line, and the first electrode includes the first electrode of the second transistor and the first electrode of the light emitting element. The second electrode is electrically connected to the first power supply line, the first to third gate signal lines provided in the row not including the pixel, and the first electrode provided in the row including the pixel. Electrically connected to either the second gate signal line or the third gate signal line;
A gate electrode of the second transistor is electrically connected to a first electrode of the third transistor; a second electrode is electrically connected to the current supply line;
A gate electrode of the third transistor is electrically connected to the second gate signal line; a second electrode is electrically connected to the source signal line;
A second electrode of the light emitting element is electrically connected to a second power line;
The capacitive element is provided between a gate electrode and a first electrode of the second transistor;
The gate electrode of the fourth transistor is electrically connected to the third gate signal line, the first electrode is electrically connected to the gate electrode of the second transistor, and the second electrode is The second transistor is electrically connected to any one of the first electrode, the first power supply line, and the second power supply line.
[0038]
The display device of the present invention includes:
A display device in which pixels having a source signal line, first and second gate signal lines, a current supply line, first to fourth transistors, a capacitor element, and a light emitting element are provided in a matrix. There,
The gate electrode of the first transistor is electrically connected to the first gate signal line, and the first electrode is electrically connected to the first electrode of the second transistor and the first electrode of the light emitting element. The second electrode is connected to the first power supply line, the first gate signal line or the second gate signal line provided in the row not including the pixel, and the second electrode provided in the row including the pixel. Electrically connected to one of the two gate signal lines,
A gate electrode of the second transistor is electrically connected to a first electrode of the third transistor; a second electrode is electrically connected to the current supply line;
A gate electrode of the third transistor is electrically connected to the first gate signal line; a second electrode is electrically connected to the source signal line;
A second electrode of the light emitting element is electrically connected to a second power supply line;
The capacitive element is provided between a gate electrode and a first electrode of the second transistor;
The gate electrode of the fourth transistor is electrically connected to the second gate signal line, the first electrode is electrically connected to the gate electrode of the second transistor, and the second electrode is The second transistor is electrically connected to any one of the first electrode, the first power supply line, and the second power supply line.
[0039]
The display device of the present invention includes:
A display device in which pixels having a source signal line, first to third gate signal lines, a current supply line, first to fourth transistors, a capacitor, and a light-emitting element are provided in a matrix. There,
The gate electrode of the first transistor is electrically connected to the first gate signal line, and the first electrode is electrically connected to the first electrode of the second transistor and the first electrode of the light emitting element. The second electrode is connected to the first power supply line, the first to third gate signal lines provided in the row not including the pixel, and the second gate provided in the row including the pixel. Electrically connected to either the signal line or the third gate signal line;
A gate electrode of the second transistor is electrically connected to a first electrode of the third transistor; a second electrode is electrically connected to the current supply line;
A gate electrode of the third transistor is electrically connected to the second gate signal line; a second electrode is electrically connected to the source signal line;
A second electrode of the light emitting element is electrically connected to a second power line;
The capacitive element is provided between a gate electrode and a first electrode of the second transistor;
The gate electrode of the fourth transistor is electrically connected to the third gate signal line, the first electrode is electrically connected to the first electrode of the light emitting element, and the second electrode is connected to the first electrode. It is electrically connected to one power line.
[0040]
The display device of the present invention includes:
A display device in which pixels having a source signal line, first and second gate signal lines, a current supply line, first to fourth transistors, a capacitor element, and a light emitting element are provided in a matrix. There,
The gate electrode of the first transistor is electrically connected to the first gate signal line, and the first electrode is electrically connected to the first electrode of the second transistor and the first electrode of the light emitting element. The second electrode is connected to the first power source line, the first to third gate signal lines provided in a row not including the pixel, and the second gate signal provided in the row including the pixel. Electrically connected to either the line or the third gate signal line,
A gate electrode of the second transistor is electrically connected to a first electrode of the third transistor; a second electrode is electrically connected to the current supply line;
A gate electrode of the third transistor is electrically connected to the first gate signal line; a second electrode is electrically connected to the source signal line;
A second electrode of the light emitting element is electrically connected to a second power source having a potential difference from the current supply line;
The capacitive element is provided between a gate electrode and a first electrode of the second transistor;
The gate electrode of the fourth transistor is electrically connected to the second gate signal line, the first electrode is electrically connected to the first electrode of the light emitting element, and the second electrode is connected to the first electrode. It is electrically connected to one power line.
[0041]
The display device of the present invention includes:
A display device in which pixels having a source signal line, first to third gate signal lines, a current supply line, first to fourth transistors, a capacitor, and a light-emitting element are provided in a matrix. There,
The gate electrode of the first transistor is electrically connected to the first gate signal line, and the first electrode is electrically connected to the first electrode of the second transistor and the first electrode of the light emitting element. The second electrode is connected to the first power source line, the first to third gate signal lines provided in a row not including the pixel, and the second gate signal provided in the row including the pixel. Electrically connected to either the line or the third gate signal line,
A gate electrode of the second transistor is electrically connected to a first electrode of the third transistor; a second electrode is electrically connected to the current supply line;
A gate electrode of the third transistor is electrically connected to the second gate signal line; a second electrode is electrically connected to the source signal line;
A second electrode of the light emitting element is electrically connected to a second power line;
The capacitive element is provided between a gate electrode and a first electrode of the second transistor, and holds a voltage between the gate electrode and the first electrode of the second transistor;
The fourth transistor is between the second electrode of the second transistor and the current supply line, or between the first electrode of the second transistor and the first electrode of the light emitting element. And the gate electrode of the fourth transistor is electrically connected to the third gate signal line.
[0042]
The display device of the present invention includes:
A display device in which pixels having a source signal line, first and second gate signal lines, a current supply line, first to fourth transistors, a capacitor element, and a light emitting element are provided in a matrix. There,
The gate electrode of the first transistor is electrically connected to the first gate signal line, and the first electrode is electrically connected to the first electrode of the second transistor and the first electrode of the light emitting element. The second electrode is connected to the first power supply line, the first gate signal line or the second gate signal line provided in the row not including the pixel, and the second electrode provided in the row including the pixel. Electrically connected to one of the two gate signal lines,
A gate electrode of the second transistor is electrically connected to a first electrode of the third transistor; a second electrode is electrically connected to the current supply line;
A gate electrode of the third transistor is electrically connected to the first gate signal line; a second electrode is electrically connected to the source signal line;
A second electrode of the light emitting element is electrically connected to a second power line;
The capacitive element is provided between a gate electrode and a first electrode of the second transistor, and holds a voltage between the gate electrode and the first electrode of the second transistor;
The fourth transistor is between the second electrode of the second transistor and the current supply line, or between the first electrode of the second transistor and the first electrode of the light emitting element. And the gate electrode of the fourth transistor is electrically connected to the third gate signal line.
[0043]
In the display device of the present invention,
The first and third transistors may be of the same conductivity type.
[0044]
In the display device of the present invention,
The transistors included in the pixel may be of the same conductivity type.
[0045]
In the display device of the present invention,
When the conductivity type of the second transistor is an N-channel type, the potential V of the current supply line 1 , The potential V of the first power supply line 2 , The potential V of the second power supply line Three Is V 1 > V 2 And V 1 > V Three It may be. In addition, V 2 > V Three It may be.
[0046]
The display device of the present invention includes:
When the conductivity type of the second transistor is a P-channel type, the potential V of the current supply line 1 , The potential V of the first power supply line 2 , The potential V of the second power supply line Three Is V 1 <V 2 And V 1 <V Three It may be. In addition, V 2 <V Three It may be.
[0047]
The display device driving method of the present invention includes:
A first switching element, a second switching element, a transistor, a capacitor, and a light emitting element;
A first electrode of the first switching element is electrically connected to a source signal line; a second electrode is electrically connected to a gate electrode of the transistor;
A first electrode of the transistor is electrically connected to a first electrode of the second switching element and a first electrode of the light-emitting element; the second electrode is electrically connected to a current supply line;
A second electrode of the second switching element is electrically connected to a first power line;
A second electrode of the light emitting element is electrically connected to a second power line;
The capacitive element is a driving method of a display device having a pixel provided between a gate electrode and a first electrode of the transistor,
Conducting the first and second switching elements, inputting a video signal from the source signal line to the transistor, and fixing the potential of the first electrode of the transistor;
The first and second switching elements are non-conductive, the gate electrode of the transistor is in a floating state,
A current corresponding to the potential applied to the gate electrode of the transistor is supplied to the light-emitting element, the voltage between the gate and the source of the transistor is held by the capacitor, and the potential change amount of the first electrode of the transistor And the potential change amount of the gate electrode of the transistor is made equal.
[0048]
The display device driving method of the present invention includes:
A first switching element, a third switching element, a transistor, a capacitor, and a light emitting element;
A first electrode of the first switching element is electrically connected to a source signal line; a second electrode is electrically connected to a gate electrode of the transistor;
A first electrode of the transistor is electrically connected to a first electrode of the second switching element and a first electrode of the light-emitting element; the second electrode is electrically connected to a current supply line;
A second electrode of the second switching element is electrically connected to a first power line;
A second electrode of the light emitting element is electrically connected to a second power line;
The capacitive element is provided between a gate electrode and a first electrode of the transistor,
The first electrode of the third switching element is electrically connected to the gate electrode of the transistor, and the second electrode is the first electrode of the transistor, the first power supply line, and the second power supply. A driving method of a display device having a pixel electrically connected to any of lines,
Conducting the first and second switching elements, inputting a video signal from the source signal line to the transistor, and fixing the potential of the first electrode of the transistor;
The first and second switching elements are non-conductive, the gate electrode of the transistor is in a floating state,
A current corresponding to the potential applied to the gate electrode of the transistor is supplied to the light-emitting element, the voltage between the gate and the source of the transistor is held by the capacitor, and the potential change amount of the first electrode of the transistor And the potential change amount of the gate electrode of the transistor are equalized,
The third switching element is turned on, the gate-source voltage of the transistor is made equal to or lower than the absolute value of the threshold voltage, and supply of current to the light emitting element is stopped.
[0049]
The display device driving method of the present invention includes:
A first switching element, a third switching element, a transistor, a capacitor, and a light emitting element;
A first electrode of the first switching element is electrically connected to a source signal line; a second electrode is electrically connected to a gate electrode of the transistor;
A first electrode of the transistor is electrically connected to a first electrode of the second switching element and a first electrode of the light-emitting element; the second electrode is electrically connected to a current supply line;
A second electrode of the second switching element is electrically connected to the first power line;
A second electrode of the light emitting element is electrically connected to a second power supply line;
The capacitive element is provided between a gate electrode and a first electrode of the transistor,
The first electrode of the third switching element has a pixel electrically connected to the first electrode of the light emitting element, and the second electrode has a pixel electrically connected to the first power supply line. A driving method of a display device,
Conducting the first and second switching elements, inputting the video signal from the source signal line to the transistor, and fixing the potential of the first electrode of the transistor;
The first and second switching elements are made non-conductive, the gate electrode of the transistor is in a floating state,
A current corresponding to the potential applied to the gate electrode of the transistor is supplied to the light-emitting element, the voltage between the gate and the source of the transistor is held by the capacitor, and the potential change amount of the first electrode of the transistor And the potential change amount of the gate electrode of the transistor are equalized,
The third switching element is turned on, the gate-source voltage of the transistor is made equal to or lower than the absolute value of the threshold voltage, and supply of current to the light emitting element is stopped.
[0050]
The display device driving method of the present invention includes:
A first switching element, a third switching element, a transistor, a capacitor, and a light emitting element;
A first electrode of the first switching element is electrically connected to a source signal line; a second electrode is electrically connected to a gate electrode of the transistor;
The first electrode of the transistor is electrically connected to the first electrode of the second switching element and the first electrode of the light emitting element, and the second electrode is connected to the first switching element via the third switching element. Electrically connected to the current supply line,
A second electrode of the second switching element is electrically connected to the first power line;
A second electrode of the light emitting element is electrically connected to a second power line;
The capacitive element is a driving method of a display device having a pixel provided between a gate electrode and a first electrode of the transistor,
Conducting the first and second switching elements, inputting a video signal from the source signal line to the transistor, and fixing the potential of the first electrode of the transistor;
The first and second switching elements are non-conductive, the gate electrode of the transistor is in a floating state,
Conducting the third switching element, supplying a current corresponding to the potential applied to the gate electrode of the transistor to the light emitting element, and holding the gate-source voltage of the transistor by the capacitive element, The potential change amount of the first electrode of the transistor is equal to the potential change amount of the gate electrode of the transistor,
The third switching element is made non-conductive, and supply of current to the light emitting element is stopped.
[0051]
In the present invention, a transistor can be used as the switching element. The transistor of the present invention can be a thin film transistor (TFT) or a transistor formed using SOI technology. A transistor using an organic material for the active layer, a transistor using a polycrystalline semiconductor, or a transistor using an amorphous semiconductor may be used. For example, a TFT using polysilicon or a TFT using amorphous silicon can be used.
[0052]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
FIG. 1A shows an embodiment of the present invention. The pixel of the invention includes a source signal line 101, a gate signal line 102, first to third TFTs 103 to 105, a capacitor element 106, a current supply line 107, an EL element 108, power supply lines 109 and 110 (first power supply line). , Second power supply line). The gate electrode of the TFT 103 is connected to the gate signal line 102, the first electrode is connected to the source signal line 101, and the second electrode is connected to the gate electrode of the TFT 104. The first electrode of the TFT 104 is connected to the current supply line 107, and the second electrode is connected to the first electrode of the TFT 105 and the first electrode of the EL element. The gate electrode of the TFT 105 is connected to the gate signal line 102, and the second electrode is connected to the power supply line 110. A second electrode of the EL element 108 is connected to the power supply line 109. The capacitor element 106 is provided between the gate electrode and the second electrode of the TFT 104 and holds the gate-source voltage of the TFT.
[0053]
Now, all of the TFTs 103 to 105 are N-channel TFTs, and are turned on when the gate-source voltage exceeds the threshold value. In the EL element 108, the first electrode is an anode, the second electrode is a cathode, and the potential of the anode is V. A , The potential of the cathode, that is, the potential of the power line 109 is V C And Further, the potential of the current supply line 107 is set to V DD And the potential of the power supply line 110 is V SS And The potential of the video signal is V Sig And
[0054]
The operation of the circuit will be described with reference to FIGS. Here, the gate (G), source (S), and drain (D) of the TFT 104 are defined as shown in FIG.
[0055]
In a certain row, the gate signal line 102 is selected and the TFTs 103 and 105 are turned on. A video signal is input from the source signal line 101 to the gate electrode of the TFT 104 as shown in FIG. Sig It becomes. On the other hand, since TFT 105 is ON, V A = V SS It becomes. At this time, V SS ≦ V C In other words, no current flows through the EL element 108 when the video signal is written. However, V SS > V C Thus, a current may flow through the EL element 108. What is important here is V A Is fixed at a constant potential. By this operation, the voltage between both electrodes of the capacitor 106 becomes (V Sig -V SS ). Eventually, when the selection period of the gate signal line 102 is completed and the TFTs 103 and 105 are turned off, the charge transfer path stored in the capacitor element 106 disappears, and the gate-source voltage (V Sig -V SS ) Is held (FIG. 3B).
[0056]
Where (V Sig -V SS ) Exceeds the threshold value of the TFT 104, the TFT 104 is turned on, current starts to flow from the current supply line 107 to the EL element, light emission starts (FIG. 3C), and the source potential of the TFT 104 rises. At this time, since the gate electrode of the TFT 104 is in a floating state and the gate-source voltage of the TFT 104 is held by the capacitor 106, the potential of the gate electrode also increases as the source potential increases. At this time, in the TFTs 104 and 105, a capacitance component exists between the gate electrode and the semiconductor layer (source region or drain region). By making it dominant, the increase range of the source potential of the TFT 104 and the increase range of the gate potential of the TFT 104 can be made substantially equal.
[0057]
Based on these operations, an operation based on the presence or absence of deterioration of the EL element will be considered with reference to FIG. In FIG. 1B, 151 is the potential of the gate signal line 102, and 152 and 153 are the potential V of the gate electrode of the TFT 104. G 154, 155 are anodes V of the EL element 108 A That is, the source potential of the TFT 104, 156 is the gate-source voltage V of the TFT 104. GS Are respectively schematically represented.
[0058]
Now, in the section indicated by (i) in FIG. 1B, the gate signal line 102 is selected and becomes H level. Therefore, in this section, the video signal is written and the gate potential V of the TFT 104 is G Rises. Further, since the TFT 105 is ON, the potential V of the anode of the EL element 108 A That is, the source potential of the TFT 104 is V SS Is equal to Therefore, the gate-source voltage V of the TFT 104 GS Becomes larger. In this section, V A = V SS <V C If the video signal V Sig The EL element 108 does not emit light regardless of the value of.
[0059]
At the timing shown in (ii), the selection of the gate signal line 102 is completed and becomes L level, and the TFTs 103 and 105 are turned off. V at this time GS = (V Sig -V A ) Is held in the capacitor 106.
[0060]
Subsequently, the section shown in (iii) is entered and light emission starts. At this time, the gate-source voltage V of the TFT 104 GS Exceeds the threshold value, the TFT 104 is turned on, a drain current flows, and the EL element 108 emits light. At the same time, the source potential of the TFT 104 also rises. Here, as described above, the gate electrode of the TFT 104 is in a floating state and rises in the same manner as the source potential of the TFT 104 rises.
[0061]
Here, a case where the EL element 108 is deteriorated is considered. When the EL element deteriorates, the voltage between the anode and the cathode increases when an electric current of a certain value flows through the EL element 108 as described above. A Rises. However, in the case of the present invention, V A As much as V G As a result, V GS It can be seen that there is no change.
[0062]
On the other hand, as shown in FIG. 7, in the case of the conventional configuration as shown in FIG. Sig Then the gate potential V of the TFT 204 G Does not change. Therefore, the EL element 207 deteriorates and V A Increases, the gate-source voltage of the TFT 204 becomes smaller than that before deterioration (FIGS. 7G and 7H). In such a case, even if the TFT 204 is operated in the saturation region, the current value at the operating point changes. Therefore, when the EL element 207 is deteriorated and the voltage / current characteristics are changed, the current flowing through the EL element 207 is reduced and the luminance is lowered.
[0063]
As described above, in the present invention, it is possible to eliminate the influence of the deterioration of the EL element by preventing the current value from being changed even when the EL element is deteriorated.
[0064]
Also, the potential V of the power line SS , V C Can be set arbitrarily, so V SS <V C Therefore, it is easy to apply a reverse bias to the EL element.
[0065]
Note that the TFTs 103 and 105 only need to function as switching elements, and their polarities are not limited. That is, normal operation is possible even if all TFTs constituting a pixel are unipolar. In FIG. 1, the TFTs 103 and 105 have the same polarity and are controlled only by the gate signal line 102. However, different TFTs may be controlled by using different first and second gate signal lines. . In this case, the TFTs 103 and 105 may have different polarities. However, considering the aperture ratio of the pixels, it is desirable that the number of wirings be as small as possible.
[0066]
[Embodiment 2]
According to the configuration shown in FIG. 1, the wiring routed to the pixel portion is a source signal line, a gate signal line, a current supply line (V DD ), Power line (V C ), Power line (V SS ) Was required. In the present embodiment, a configuration in which the number of wirings per pixel is reduced by sharing wirings and a high aperture ratio can be obtained will be described.
[0067]
FIG. 9 shows the configuration of this embodiment. The difference from Embodiment 1 is that the second electrode of the TFT 906 is connected to the power supply line (V SS In the present embodiment, only the point connected to the gate signal line of the next row is connected. Assuming that the pixel indicated by the dotted line frame 900 is the i-th row, the second electrode of the TFT 906 is connected to the i + 1-th gate signal line.
[0068]
As a pulse condition for selecting the gate signal line, when the gate signal line is at the H level, the gate-source voltage of the TFT 904 may sufficiently exceed the threshold value. That is, the video signal V Sig Any potential that is higher than the maximum value by a threshold value is sufficient. On the other hand, when it is at the L level, any potential may be used as long as the TFT 904 is reliably turned off. Therefore, the L-level potential is V in the gate signal line. SS To be equal to
[0069]
When the gate signal line in the i-th row is selected and becomes the H level and the TFTs 904 and 906 are turned on, the gate signal line in the i + 1-th row is not yet selected. That is, it is at L level and its potential is V SS It is. Therefore, the potential V of the anode of the EL element is passed through the TFT 906. A Is V as in the embodiment. SS Is equal to Therefore, even when the wiring is shared according to the present embodiment, the same operation as that of the first embodiment can be obtained.
[0070]
Note that the i-th gate signal line is selected and becomes H level, and the constant potential V is maintained during the period in which the TFT 906 is ON. SS The connection destination of the second electrode of the TFT 906 is not limited to the (i + 1) th gate signal line, and may be, for example, the (i-1) th gate signal line. It may be other than that. In the case where signal lines in adjacent rows are shared, it is desirable that pulses of the signal lines do not overlap each other.
[0071]
Further, as described in the first embodiment, since the TFTs 904 and 906 only need to function as switching elements, their polarities are not limited and are controlled by a single gate signal line 902 as shown in FIG. There is no limitation.
[0072]
[Embodiment 3]
A method in which display is performed by controlling the gate-source voltage of the driving TFT and controlling the current value flowing through the EL element with an analog amount is called an analog gradation method. On the other hand, there has been proposed a digital gradation method in which the EL element is driven only in two states of luminance 100% and 0%. This method can express only two gradations of white and black, but has an advantage that it is not easily affected by variations in TFT characteristics. In order to increase the number of gradations by the digital gradation method, a driving method combined with the time gradation method is used. The time gray scale method is a method for expressing a gray scale according to the length of time during which an element emits light.
[0073]
When the digital gradation method and the time gradation method are combined, one frame period is divided into a plurality of subframe periods as shown in FIG. Each subframe period has an address (write) period, a sustain (light emission) period, and an erase period, as shown in FIG. The number of subframe periods corresponding to the number of display bits is provided, and the length of the sustain (light emission) period in each subframe period is set to 2 (n-1) : 2 (n-2) : ...: 2: 1, and EL element light emission or non-light emission is selected in each sustain (light emission) period, and gradation is calculated using the difference in length of the total period during which the EL element emits light. Make an expression. If the light emission period is long, the luminance is high, and if it is short, the luminance is low. Note that FIG. 10 shows an example of 4-bit gradation, and one frame period is divided into four subframe periods, and 2 frames are obtained by combining the sustain (light emission) periods. Four = 16 gradations can be expressed. Note that gradation expression is possible even if the ratio of the length of the sustain period is not particularly a power-of-two ratio. Further, a certain subframe period may be further divided.
[0074]
When multi-gradation is attempted using the time gray scale method, the length of the sustain (light emission) period of the lower bits becomes shorter, so an attempt is made to start the next address period immediately after the end of the sustain (light emission) period. Then, a period in which address (write) periods in different subframe periods overlap is generated. In that case, since a video signal input to a certain pixel is also input to different pixels at the same time, normal display cannot be performed. The erasing period is provided to solve such a problem. As shown in FIG. 10B, two different address (writing) periods do not overlap after Ts3 and after Ts4. Is provided. Therefore, the erase period is not provided in SF1 and SF2 in which the sustain (light emission) period is sufficiently long and there is no concern that two different address (write) periods overlap.
[0075]
Thus, in order to drive by a method combining the digital gray scale method and the time gray scale method, it may be necessary to add an operation of forcibly stopping the light emission of the EL element and providing an erasing period.
[0076]
FIG. 4A corresponds to a driving method in which a second gate signal line 403 and an erasing TFT 407 are added to the pixel having the structure shown in Embodiment Mode 1 and a digital gray scale method and a time gray scale method are combined. This is an example. The gate electrode of the erasing TFT 407 is connected to the second gate signal line 403, the first electrode is connected to the gate electrode of the TFT 405 and the first electrode of the capacitor 408, and the second electrode is connected to the TFT 405. The second electrode and the second electrode of the capacitor 408 are connected.
[0077]
The operation in which the first gate signal line 402 is selected and the video signal is input is the same as that described in Embodiment Mode 1 and is therefore omitted here. Note that during the period in which the video signal is input, the second gate signal line is at the L level, and the erasing TFT 407 is OFF. At this time, V Sig Takes either of the potential for reliably turning on the TFT 405 or the potential for turning off the TFT 405.
[0078]
Here, the operation from the sustain (light emission) period to the erase period will be described with reference to FIGS. 11A is similar to that shown in FIG. 10A, and one frame period has four subframe periods as shown in FIG. 11B. The subframe periods SF3 and SF4 having a short sustain (light emission) period have erase periods Te3 and Te4, respectively. Here, the operation in SF3 will be described as an example.
[0079]
After the input of the video signal is finished, as shown in FIG. 10B, the gate-source voltage V of the TFT 405 GS A current corresponding to the current flows through the EL element 410 to emit light. After that, when the end timing of the sustain (light emission) period is reached, a pulse is input to the second gate signal line 403 and becomes H level, the erasing TFT 407 is turned on, and as shown in FIG. TFT-907 gate-source voltage V GS Is set to 0. Accordingly, the TFT 405 is turned off, the current to the EL element 410 is cut off, and the EL element 410 is forcibly turned off.
[0080]
These operations are shown in FIG. 11C as a timing chart. After the sustain (light emission) period Ts3, after a pulse is input to the third gate signal line 403 and the EL element 410 does not emit light, the pulse is input to the first gate signal line 402 again, and the next A period until the video signal starts to be input is an erasing period Te3.
[0081]
In the structure shown in FIG. 4A, the second electrode of the TFT 406 is connected to the power supply line 412, and this power supply line 412 is connected to the gate of the adjacent row as shown in the second embodiment. A signal line can be used instead. In this embodiment, since the second gate signal line 403 is provided to control the erasing TFT 407, the second electrode of the TFT 406 may be connected to the second gate signal line 403. good.
[0082]
Although the TFTs 404 and 406 are controlled by the same gate signal line 402, a single gate signal line may be added and the TFTs 404 and 406 may be controlled by different gate signal lines.
[0083]
[Embodiment 4]
FIG. 5A shows an example in which an erasing TFT is provided at a position different from that in the third embodiment. In this embodiment, the erasing TFT 507 is provided between the gate electrode of the TFT 505, the first electrode of the capacitor 508, and the power supply line 512.
[0084]
In the driving method, the input to light emission of the video signal may be a method combining the digital gray scale method and the time gray scale method as in the third embodiment. Therefore, the description is omitted here and the operation in the erasing period is performed. Will be described.
[0085]
When the timing for ending the sustain (light emission) period is reached, a pulse is input to the second gate signal line 503 to become H level, the erasing TFT 507 is turned on, and the gate of the TFT 505 is turned on as shown in FIG. The potential of the electrode is V SS It becomes. That is, in the erase period, the gate-source voltage V of the TFT 505 GS However, it is sufficient to make it below the threshold value.
[0086]
The source potential of the TFT 505 is at least V SS Is at a potential equal to or greater than. Therefore, the gate-source voltage V of the TFT 505 is caused by the operation of the erasing TFT 507 described above. GS Is V GS ≦ 0 and the TFT 505 is turned off. Therefore, the period until the EL element 510 does not emit light, a pulse is input to the first gate signal line 502 again, and the next video signal starts to be input is an erasing period.
[0087]
In the structure shown in FIG. 5A, the second electrode of the TFT 506 is connected to the power supply line 512. The power supply line 512 is connected to the gate of the adjacent row as shown in the second embodiment. A signal line can be used instead. In the present embodiment, since the second gate signal line 503 is provided to control the erasing TFT 507, the second electrode of the TFT 506 is connected to the second gate signal line 503. good.
[0088]
[Embodiment 5]
FIG. 6A shows an example in which an erasing TFT is provided at a position different from those in the third and fourth embodiments. In this embodiment, the erasing TFT 607 is provided between the first electrode of the TFT 605 and the current supply line.
[0089]
The operation of the circuit will be described. The first gate signal line 602 is selected and becomes H level, the TFT 604 is turned on, and a video signal is input to the pixel from the source signal line 601. On the other hand, the TFT 606 is also turned on, and the potential V of the anode of the EL element 610. A V SS Equal to At this time, V SS ≦ V C In other words, since no current flows through the EL element 610 when the video signal is written, the TFT 607 may be turned on or off.
[0090]
When the input of the video signal is completed and the first gate signal line 602 is deselected, the gate electrode of the TFT 605 is in a floating state, and in the capacitor 608, the stored charge transfer path is blocked. Source-to-source voltage V GS Is held in the capacitor 608.
[0091]
Subsequently, when the second gate signal line 603 is selected and becomes H level and the TFT 607 is turned on, a current flows as shown in FIG. 6D, and the potential V of the anode of the EL element 610 is obtained. A Rises and the cathode potential V C A potential difference is generated, and current flows to emit light. Note that the TFT 607 may be turned on from the stage of inputting the video signal. In this case, at the moment when the first gate signal line 602 is not selected, current is supplied to the EL element 610 through the TFTs 607 and 605, and the potential V of the anode of the EL element 610 is supplied. A Rises and the cathode potential V C A potential difference is generated, and current flows to emit light.
[0092]
When the timing for ending the sustain (light emission) period is reached, the second gate signal line 603 is not selected and becomes L level, the TFT 607 is turned OFF, and the current path from the current supply line 609 to the EL element 610 is cut off. . As a result, no current flows through the EL element 610 and no light is emitted. After that, the period from when a pulse is input to the first gate signal line 602 again until the next video signal starts to be input is an erasing period.
[0093]
Note that the TFT 607 may be disposed between the first electrode of the TFT 605 and the anode of the EL element 610. In other words, it may be arranged between the current path from the current supply line 609 to the EL element 610 so that the current supply to the EL element 610 can be cut during the erasing period.
[0094]
[Embodiment 6]
In the third to fifth embodiments, the example in which the TFT is added to provide the erasing period has been described, but in this embodiment, an example in which the same operation is performed without adding the erasing TFT will be described.
[0095]
FIG. 21A shows the configuration. The configuration is almost the same as that shown in the first embodiment except that the TFTs 2104 and 2106 are controlled by different gate signal lines 2102 and 2103, respectively.
[0096]
In the sustain (light emission) period, as shown in FIG. 21B, the gate-source voltage of the TFT 2105 is fixed by the capacitor 2107, and the accompanying current flows to the EL element 2109 to emit light.
[0097]
Subsequently, in the erasing period, a pulse is input to the second gate signal line 2103 and the TFT 2106 is turned on. At this time, the potential of the power supply line 2111 to which the second electrode of the TFT 2106 is connected is lower than the potential of the cathode of the EL element 2109, that is, the potential of the power supply line 2110, so that the EL element 2109 has a current. No longer flows. Therefore, the current at this time flows as shown in FIG.
[0098]
Note that as described in other embodiments, the power supply line 2111 may be a gate signal line in an adjacent row.
[0099]
[Embodiment 7]
Although an N-channel TFT has been used as a TFT for supplying current to the EL element, the present invention can also be implemented using a P-channel TFT as a driving TFT. FIG. 12A shows a configuration example.
[0100]
The circuit configuration is the same as that using the N-channel TFT shown in FIG. 1A, but the configuration of the EL element 1208 is reversed, and the side connected to the second electrode of the TFT 1204 is the cathode. The point where the side connected to the power supply line 1209 is the anode and the potential of the current supply line 1207 is V SS The potential of the power line 1209 is V A , The potential of the power supply line 1210 is V DD Is different. Where V SS <V DD And V A <V DD It is.
[0101]
The operation of the circuit will be described with reference to FIGS. Here, the polarity of the TFT is a P-channel type, and it is assumed that the L level is input to the gate electrode to be turned ON, and the H level is input to be OFF.
[0102]
In a certain row, the gate signal line 1202 is selected and becomes L level, and the TFTs 1203 and 1205 are turned ON. A video signal is input from the source signal line 1201 to the gate electrode of the TFT 1204 as shown in FIG. Sig It becomes. On the other hand, since the TFT 1205 is ON, the potential V of the cathode of the EL element 1208 C Is V C = V DD It becomes. At this time, V A ≦ V DD In other words, no current flows through the EL element 1208 when the video signal is written. By this operation, the voltage between both electrodes of the capacitor element 1206, that is, the gate-source voltage of the TFT 1204 is (V Sig -V DD ). Eventually, when the selection period of the gate signal line 1202 ends and becomes H level, and the TFTs 1203 and 1205 are turned OFF, there is no transfer path of the charge stored in the capacitor 1206, and the gate-source voltage (V Sig -V DD ) Is held (FIG. 12C).
[0103]
Where (V Sig -V DD ) Is lower than the threshold value of the TFT 1204, the TFT 1204 is turned on, a current flows between the power supply line 1209 to the EL element 1208 to the current supply line 1207 (FIG. 12D), and the TFT 1204. The source potential of At this time, the gate electrode of the TFT 1204 is in a floating state, and the voltage between the gate and the source of the TFT 1204 is held by the capacitor element 1206. Therefore, the potential of the gate electrode also decreases as the source potential decreases.
[0104]
In FIG. 12A, P-channel TFTs are used for all of the TFTs constituting the pixel. However, as described in other embodiments, the TFTs 1203 and 1205 only need to function as switching elements. The polarity does not matter. Further, the TFTs 1203 and 1205 do not need to be driven only by the gate signal line 1202, and each TFT may be controlled by another gate signal line.
[0105]
【Example】
Examples of the present invention will be described below.
[0106]
[Example 1]
In this embodiment, a configuration of a light-emitting device that performs display using an analog video signal as a video signal will be described. FIG. 16A illustrates a configuration example of a light-emitting device. A pixel portion 1602 in which a plurality of pixels are arranged in a matrix is provided over a substrate 1601. A source signal line driver circuit 1603 and first and second gate signal line driver circuits 1604 and 1605 are provided around the pixel portion. have. In FIG. 16A, two sets of gate signal line driver circuits are used. However, when there is one gate signal line as in the pixel shown in FIG. 1, the gate signal lines are simultaneously connected from both sides. Control. In the case of having two gate signal lines as in the pixels shown in FIGS. 4 and 5, each gate signal line driving circuit controls each gate signal line.
[0107]
Signals input to the source signal line driver circuit 1603 and the first and second gate signal line driver circuits 1604 and 1605 are supplied from the outside through a flexible printed circuit (FPC) 1606.
[0108]
FIG. 16B illustrates a configuration example of the source signal line driver circuit. This is a source signal line driver circuit for performing display using an analog video signal as a video signal, and includes a shift register 1611, a buffer 1612, and a sampling circuit 1613. Although not particularly shown, a level shifter or the like may be added as necessary.
[0109]
The operation of the source signal line driver circuit will be described. FIG. 17A shows a more detailed configuration, and reference is made thereto.
[0110]
The shift register 1701 includes a plurality of stages of flip-flop circuits (FF) 1702 and the like, and receives a clock signal (S-CLK), a clock inversion signal (S-CLKb), and a start pulse (S-SP). Sampling pulses are sequentially output according to the timing of these signals.
[0111]
The sampling pulse output from the shift register 1701 is amplified through the buffer 1703 and the like and then input to the sampling circuit. The sampling circuit 1704 uses a plurality of stages of sampling switches (SW) 1705, and samples a video signal in a certain column according to the timing at which sampling pulses are input. Specifically, when a sampling pulse is input to the sampling switch, the sampling switch 1705 is turned on, and the potential of the video signal at that time is output to each source signal line via the sampling switch.
[0112]
Next, the operation of the gate signal line driving circuit will be described. An example of a detailed configuration of the first and second gate signal line driver circuits 1604 and 1605 shown in FIG. 16C is shown in FIG. The first gate signal line driver circuit includes a shift register circuit 1711 and a buffer 1712 and is driven according to a clock signal (G-CLK1), a clock inversion signal (G-CLKb1), and a start pulse (G-SP1). The second gate signal line driver circuit 1605 may have the same configuration.
[0113]
The operation of the shift register to buffer is the same as that of the source signal line driver circuit. The selection pulse amplified by the buffer selects each gate signal line. By the first gate signal line driving circuit, the first gate signal line G 11 , G twenty one ... G m1 Are sequentially selected, and the second gate signal line G is selected by the second gate signal line driving circuit. 12 , G twenty two ... G m2 Are selected sequentially. Although not shown, the third gate signal line drive circuit is the same as the first and second gate signal line drive circuits, and the third gate signal line G 13 , G twenty three ... G m3 Are selected sequentially. In the selected row, a video signal is written in the pixel and emits light according to the procedure described in the embodiment.
[0114]
Although an example of a shift register using a plurality of stages of D-flip flops is shown here as an example of the shift register, a configuration in which a signal line can be selected by a decoder or the like may be used.
[0115]
[Example 2]
In this embodiment, a configuration of a light-emitting device that performs display using a digital video signal as a video signal will be described. FIG. 18A illustrates a configuration example of a light-emitting device. A pixel portion 1802 in which a plurality of pixels are arranged in a matrix is provided over a substrate 1801, and a source signal line driver circuit 1803 and first and second gate signal line driver circuits 1804 and 1805 are provided around the pixel portion. have. In FIG. 18A, two sets of gate signal line driver circuits are used. However, when there is one gate signal line as in the pixel shown in FIG. 1, the gate signal lines are simultaneously connected from both sides. Control. In the case of having two gate signal lines as in the pixels shown in FIGS. 4 and 5, each gate signal line driving circuit controls each gate signal line.
[0116]
Signals input to the source signal line driver circuit 1803 and the first and fourth gate signal line driver circuits 1804 and 1805 are supplied from the outside via a flexible printed circuit (FPC) 1806.
[0117]
FIG. 18B illustrates a configuration example of the source signal line driver circuit. This is a source signal line driver circuit for performing display using a digital video signal as a video signal, and includes a shift register 1811, a first latch circuit 1812, a second latch circuit 1813, and a D / A converter circuit 1814. Have. Although not particularly shown, a level shifter or the like may be added as necessary.
[0118]
Since the first and second gate signal line driving circuits 1804 and 1805 may be the same as those shown in the first embodiment, their illustration and description are omitted here.
[0119]
The operation of the source signal line driver circuit will be described. FIG. 19 (A) shows a more detailed configuration, so reference is made to it.
[0120]
The shift register 1901 includes a plurality of stages of flip-flop circuits (FF) 1910 and the like, and receives a clock signal (S-CLK), a clock inversion signal (S-CLKb), and a start pulse (S-SP). Sampling pulses are sequentially output according to the timing of these signals.
[0121]
The sampling pulse output from the shift register 1901 is input to the first latch circuit 1902. A digital video signal is input to the first latch circuit 1902, and the digital video signal is held in each stage in accordance with the timing at which the sampling pulse is input. Here, the digital video signal is inputted with 3 bits, and the video signal of each bit is held in each first latch circuit. Here, three first latch circuits operate in parallel by one sampling pulse.
[0122]
When the first latch circuit 1902 completes holding the digital video signal up to the final stage, a latch pulse (Latch Pulse) is input to the second latch circuit 1903 during the horizontal blanking period, and the first latch circuit 1902 The digital video signals held in are transferred to the second latch circuit 1903 all at once. After that, the digital video signal held in the second latch circuit 1903 is input to the D / A conversion circuit 1904 for one row at the same time.
[0123]
While the digital video signal held in the second latch circuit 1903 is being input to the D / A conversion circuit 1904, the sampling pulse is output again in the shift register 1901. Thereafter, this operation is repeated to process a video signal for one frame.
[0124]
The D / A conversion circuit 1904 performs digital-analog conversion on the input digital video signal and outputs it to the source signal line as a video signal having an analog voltage.
[0125]
The above operation is performed simultaneously over all stages within one horizontal period. Therefore, video signals are output to all source signal lines.
[0126]
As described in the first embodiment, the signal line may be selected using a decoder or the like instead of the shift register.
[0127]
[Example 3]
In the second embodiment, the digital video signal undergoes digital-analog conversion by a D / A conversion circuit and is written to a pixel. However, the semiconductor device of the present invention can also express gradation by a time gradation method. In this case, as shown in FIG. 19B, the D / A conversion circuit is not required, and the gradation expression is controlled by the length of the light emission time of the EL element. Since there is no need for processing, the first and second latch circuits may be one bit. At this time, each bit of the digital video signal is input in series, sequentially held in the latch circuit, and written to the pixel. Of course, latch circuits corresponding to the required number of bits may be arranged in parallel.
[0128]
[Example 4]
In this specification, a substrate in which a driver circuit and a pixel portion having a switching TFT and a driving TFT are formed over the same substrate is referred to as an active matrix substrate for convenience. In this embodiment, a process of manufacturing the active matrix substrate using a unipolar TFT will be described with reference to FIGS.
[0129]
As the substrate 5000, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed is used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature in this manufacturing process may be used. In this embodiment, a substrate 5000 made of glass such as barium borosilicate glass or alumino borosilicate glass was used.
[0130]
Next, a base film 5001 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 5000. Although the base film 5001 in this embodiment is formed with a two-layer structure, a single-layer structure of the insulating film or a structure in which two or more insulating films are stacked may be used.
[0131]
In this embodiment, as the first layer of the base film 5001, a plasma CVD method is used to form SiH. Four , NH Three And N 2 A silicon nitride oxide film 5001a formed using O as a reactive gas is formed to a thickness of 10 to 200 [nm] (preferably 50 to 100 [nm]). In this embodiment, the silicon nitride oxide film 5001a is formed to a thickness of 50 [nm]. Next, as a second layer of the base film 5001, a plasma CVD method is used to form SiH. Four And N 2 A silicon oxynitride film 5001b formed using O as a reaction gas is formed to a thickness of 50 to 200 [nm] (preferably 100 to 150 [nm]). In this embodiment, the silicon oxynitride film 5001b is formed to a thickness of 100 [nm].
[0132]
Subsequently, semiconductor layers 5002 to 5005 are formed over the base film 5001. The semiconductor layers 5002 to 5005 are formed by a known means (sputtering method, LPCVD method, plasma CVD method, etc.) with a thickness of 25 to 80 [nm] (preferably 30 to 60 [nm]). Next, the semiconductor film is crystallized by using a known crystallization method (a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like). Then, the obtained crystalline semiconductor film is patterned into a desired shape to form semiconductor layers 5002 to 5005. Note that as the semiconductor film, an amorphous semiconductor film, a microcrystalline semiconductor film, a crystalline semiconductor film, a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film, or the like may be used.
[0133]
In this embodiment, an amorphous silicon film having a film thickness of 55 [nm] is formed by plasma CVD. Then, a solution containing nickel is held on the amorphous silicon film, and the amorphous silicon film is dehydrogenated (500 [° C.], 1 hour), and then thermally crystallized (550 [° C.], 4 hours) to form a crystalline silicon film. After that, semiconductor layers 5002 to 5005 were formed by a patterning process using a photolithography method.
[0134]
Note that in the case of manufacturing a crystalline semiconductor film by a laser crystallization method, a continuous wave or pulsed gas laser or solid laser may be used. As the former gas laser, excimer laser, YAG laser, YVO Four Laser, YLF laser, YAlO Three A laser, a glass laser, a ruby laser, a Ti: sapphire laser, or the like can be used. The latter solid-state laser includes YAG, YVO doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm. Four , YLF, YAlO Three A laser using a crystal such as can be used. The fundamental wave of the laser differs depending on the material to be doped, and a laser beam having a fundamental wave around 1 [μm] can be obtained. The harmonic with respect to the fundamental wave can be obtained by using a nonlinear optical element. In order to obtain a crystal with a large grain size when crystallizing the amorphous semiconductor film, it is preferable to use a solid-state laser capable of continuous oscillation and apply the second to fourth harmonics of the fundamental wave. . Typically, Nd: YVO Four A second harmonic (532 [nm]) or a third harmonic (355 [nm]) of a laser (fundamental wave 1064 [nm]) is applied.
[0135]
Also, continuous oscillation YVO with an output of 10 [W] Four Laser light emitted from the laser is converted into a harmonic by a non-linear optical element. In addition, YVO in the resonator Four There is also a method of emitting harmonics by inserting a crystal and a nonlinear optical element. Preferably, the laser beam is shaped into a rectangular or elliptical shape on the irradiation surface by an optical system, and the object to be processed is irradiated. The energy density at this time is 0.01 to 100 [MW / cm. 2 ] Grade (preferably 0.1-10 [MW / cm 2 ])is required. Then, irradiation is performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 [cm / s].
[0136]
In the case of using the above laser, the laser beam emitted from the laser oscillator may be condensed linearly by an optical system and irradiated on the semiconductor film. The conditions for crystallization are appropriately set. When an excimer laser is used, the pulse oscillation frequency is 300 [Hz] and the laser energy density is 100 to 700 [mJ / cm. 2 ] (Typically 200-300 [mJ / cm 2 ]) When a YAG laser is used, the second harmonic is used to set a pulse oscillation frequency of 1 to 300 [Hz] and a laser energy density of 300 to 1000 [mJ / cm. 2 ] (Typically 350-500 [mJ / cm 2 ]) Then, a laser beam condensed in a linear shape with a width of 100 to 1000 [μm] (preferably a width of 400 [μm]) is irradiated over the entire surface of the substrate, and the linear beam superposition ratio (overlap ratio) at this time May be set as 50 to 98 [%].
[0137]
However, in this embodiment, since the amorphous silicon film is crystallized using a metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, an amorphous silicon film having a thickness of 50 to 100 [nm] is formed on the crystalline silicon film and subjected to heat treatment (RTA method, thermal annealing using a furnace annealing furnace, etc.), and the amorphous silicon film The metal element is diffused therein, and the amorphous silicon film is removed by etching after heat treatment. As a result, the content of the metal element in the crystalline silicon film can be reduced or removed.
[0138]
Note that after the semiconductor layers 5002 to 5005 are formed, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.
[0139]
Next, a gate insulating film 5006 is formed to cover the semiconductor layers 5002 to 5005. The gate insulating film 5006 is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm] by plasma CVD or sputtering. In this embodiment, a silicon oxynitride film having a thickness of 115 [nm] is formed as the gate insulating film 5006 by a plasma CVD method. Needless to say, the gate insulating film 5006 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0140]
Note that in the case where a silicon oxide film is used as the gate insulating film 5006, TEOS (Tetraethyl Orthosilicate) and O 2 And a reaction pressure of 40 [Pa], a substrate temperature of 300 to 400 [° C.], a high frequency (13.56 [MHz]) power density of 0.5 to 0.8 [W / cm]. 2 ] May be formed by discharging. The silicon oxide film manufactured by the above process can obtain favorable characteristics as the gate insulating film 5006 by subsequent thermal annealing at 400 to 500 [° C.].
[0141]
Next, a first conductive film 5007 with a thickness of 20 to 100 [nm] and a second conductive film 5008 with a thickness of 100 to 400 [n] m are stacked over the gate insulating film 5006. In this example, a first conductive film 5007 made of a TaN film with a thickness of 30 [nm] and a second conductive film 5008 made of a W film with a thickness of 370 [nm] were stacked.
[0142]
In this embodiment, the TaN film which is the first conductive film 5007 is formed by a sputtering method, and is formed by a sputtering method in an atmosphere containing nitrogen using a Ta target. The W film as the second conductive film 5008 was formed by sputtering using a W target. In addition, tungsten hexafluoride (WF 6 It is also possible to form it by a thermal CVD method using). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 [μΩcm] or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in the W film, the crystallization is hindered and the resistance is increased. Therefore, in this embodiment, the sputtering method using a high-purity W (purity 99.9999 [%]) target is used, and W is sufficiently considered so that impurities are not mixed in from the vapor phase during film formation. By forming the film, a resistivity of 9 to 20 [μΩcm] could be realized.
[0143]
Note that in this embodiment, the first conductive film 5007 is a TaN film, and the second conductive film 5008 is a W film; however, materials for forming the first conductive film 5007 and the second conductive film 5008 are not particularly limited. . The first conductive film 5007 and the second conductive film 5008 are an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. It may be formed. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus or an AgPdCu alloy may be used.
[0144]
Next, a resist mask 5009 is formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. (Figure 13 (B))
[0145]
In this embodiment, ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, and CF is used as an etching gas. Four And Cl 2 And O 2 The gas flow ratio is 25:25:10 [sccm], and 500 [W] RF (13.56 [MHz]) power is applied to the coil-type electrode at a pressure of 1.0 [Pa]. The plasma was generated to perform etching. 150 [W] RF (13.56 [MHz]) power was also applied to the substrate side (sample stage), and a substantially negative self-bias voltage was applied. Then, the W film was etched under the first etching conditions so that the end portion of the first conductive layer 5007 was tapered.
[0146]
Subsequently, the mask 5009 made of resist is changed to the second etching condition without being removed, and the etching gas is changed to CF. Four And Cl 2 The gas flow ratio is 30:30 [sccm], and 500 [W] RF (13.56 [MHz]) power is applied to the coil-type electrode at a pressure of 1.0 [Pa]. Then, plasma was generated and etching was performed for about 15 seconds. 20 [W] RF (13.56 [MHz]) power was also applied to the substrate side (sample stage), and a substantially negative self-bias voltage was applied. Under the second etching condition, the first conductive layer 5007 and the second conductive layer 5008 were etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film 5006, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0147]
In the first etching process described above, the shape of the resist mask is made suitable, so that the end portions of the first conductive layer 5007 and the second conductive layer 5008 can be obtained by the effect of the bias voltage applied to the substrate side. Becomes a tapered shape. In this manner, the first shape conductive layers 5010 to 5014 including the first conductive layer 5007 and the second conductive layer 5008 were formed by the first etching treatment. In the gate insulating film 5006, a region not covered with the first shape conductive layers 5010 to 5014 was etched by about 20 to 50 nm, so that a region with a thin film thickness was formed.
[0148]
Next, a second etching process is performed without removing the resist mask 5009. (FIG. 13C) In the second etching process, SF is used as the etching gas. 6 And Cl 2 And O 2 Each gas flow ratio is 24:12:24 (sccm), 700 W RF (13.56 MHz) power is applied to the coil side power at a pressure of 1.3 Pa, and plasma is generated for about 25 seconds. Etching was performed. 10 W of RF (13.56 MHz) power was also applied to the substrate side (sample stage), and a substantially negative self-bias voltage was applied. Thus, the W film was selectively etched to form second shape conductive layers 5015 to 5019. At this time, the first conductive layers 5015a to 5018a are hardly etched.
[0149]
Then, a first doping process is performed without removing the mask 5009 made of resist, and an impurity element imparting n-type conductivity is added to the semiconductor layers 5002 to 5005 at a low concentration. The first doping process may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 13 ~ 5x10 14 [atoms / cm 2 The acceleration voltage is 40 to 80 [keV]. In this embodiment, the dose amount is 5.0 × 10. 13 [atoms / cm 2 The acceleration voltage was 50 [keV]. As an impurity element imparting N-type, an element belonging to Group 15 may be used. Typically, phosphorus (P) or arsenic (As) is used, but phosphorus (P) is used in this embodiment. In this case, the first shape conductive regions 5015 to 5019 serve as masks for the impurity element imparting N-type, and first impurity regions (N−− regions) 5020 to 5023 are formed in a self-aligning manner. In the first impurity regions 5020 to 5023, 1 × 10 18 ~ 1x10 20 [atoms / cm Three In the concentration range, an impurity element imparting N-type was added.
[0150]
Subsequently, after removing the resist mask 5009, a resist mask 5024 is newly formed, and a second doping process is performed at an acceleration voltage higher than that of the first doping process. The condition of the ion doping method is a dose of 1 × 10 13 ~ 3x10 15 [atoms / cm 2 The acceleration voltage is 60 to 120 [keV]. In this embodiment, the dose amount is 3.0 × 10. 15 [atoms / cm 2 The acceleration voltage was 65 [keV]. In the second doping treatment, the second conductive layers 5015b to 5018b are used as masks against the impurity elements, and doping is performed so that the impurity elements are added to the semiconductor layers below the tapered portions of the first conductive layers 5015a to 5018a. .
[0151]
As a result of performing the second doping process, the second impurity regions (N− region, Lov region) 5026 and 5029 overlapping with the first conductive layer have 1 × 10 18 ~ 5x10 19 [atoms / cm Three An impurity element imparting N-type was added in the concentration range. The third impurity regions (N + regions) 5025, 5028, 5031, 5034 have 1 × 10 19 ~ 5x10 twenty one [atoms / cm Three An impurity element imparting N-type was added in the concentration range. In addition, after the first and second doping treatments, regions where no impurity element was added or regions where a small amount of impurity element was added were formed in the semiconductor layers 5002 to 5005. In this embodiment, a region to which no impurity element is added or a region to which a small amount of impurity element is added is referred to as channel regions 5027, 5030, 5033, and 5036. Further, among the first impurity regions (N−− regions) 5020 to 5023 formed by the first doping process, there is a region covered with the resist 5024 in the second doping process. Then, the first impurity regions (N− region, LDD region) 5032 and 5035 will be referred to.
[0152]
In this embodiment, the second impurity regions (N− regions) 5026 and 5029 and the third impurity regions (N + regions) 5025, 5028, 5031 and 5034 are formed only by the second doping process. It is not limited to. It may be formed by a plurality of doping processes by appropriately changing the conditions for performing the doping process.
[0153]
Next, as shown in FIG. 14A, the resist mask 5024 is removed, and a first interlayer insulating film 5037 is formed. The first interlayer insulating film 5037 is formed of an insulating film containing silicon with a thickness of 100 to 200 [nm] by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 100 [nm] is formed by plasma CVD. Needless to say, the first interlayer insulating film 5037 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0154]
Next, heat treatment (heat treatment) is performed to recover the crystallinity of the semiconductor layer and to activate the impurity element added to the semiconductor layer. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 [° C.] in a nitrogen atmosphere with an oxygen concentration of 1 [ppm] or less, preferably 0.1 [ppm] or less. In this embodiment, 410 [° C.], 1 Activation treatment was performed by heat treatment for a period of time. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0155]
Further, heat treatment may be performed before the first interlayer insulating film 5037 is formed. However, when the material forming the first conductive layers 5015a to 5019a and the second conductive layers 5015b to 5019b is weak against heat, the first interlayer insulating film is used to protect the wiring and the like as in this embodiment. Heat treatment is preferably performed after forming 5037 (an insulating film containing silicon as a main component, for example, a silicon nitride film).
[0156]
As described above, after the first interlayer insulating film 5037 (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed, the semiconductor layer is hydrogenated simultaneously with the activation process by heat treatment. Can do. In the hydrogenation step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 5037.
[0157]
Note that heat treatment for hydrogenation may be performed separately from heat treatment for activation treatment.
[0158]
Here, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film 5037. As other means for hydrogenation, means using hydrogen excited by plasma (plasma hydrogenation) or in an atmosphere containing 3 to 100% hydrogen at 300 to 450 [° C.] for 1 to 12 hours A means for performing heat treatment may be used.
[0159]
Next, a second interlayer insulating film 5038 is formed over the first interlayer insulating film 5037. As the second interlayer insulating film 5038, an inorganic insulating film can be used. For example, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. An organic insulating film can be used as the second interlayer insulating film 5038. For example, a film made of polyimide, polyamide, BCB (benzocyclobutene), acrylic, or the like can be used. Alternatively, a stacked structure of an acrylic film and a silicon oxynitride film may be used.
[0160]
In this embodiment, an acrylic film having a thickness of 1.6 [μm] is formed. With the second interlayer insulating film 5038, unevenness due to the TFT formed on the substrate 5000 can be reduced and planarized. In particular, since the second interlayer insulating film 5038 has a strong meaning of flattening, a film having excellent flatness is preferable.
[0161]
Next, by using dry etching or wet etching, the second interlayer insulating film 5038, the first interlayer insulating film 5037, and the gate insulating film 5006 are etched to form contact holes that reach the impurity regions 5025, 5028, 5031, and 5034. To do.
[0162]
Next, a pixel electrode 5039 made of a transparent conductive film is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (Indium Tin Oxide: ITO), a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, indium oxide, or the like can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode corresponds to the anode of the EL element.
[0163]
In this embodiment, ITO is formed to a thickness of 110 nm, and then patterned to form a pixel electrode 5039.
[0164]
Next, wirings 5040 to 5046 that are electrically connected to the respective impurity regions are formed. In this embodiment, the wirings 5040 to 5046 are formed by sputtering a laminated film of a Ti film having a thickness of 100 [nm], an Al film having a thickness of 350 [nm], and a Ti film having a thickness of 100 [nm]. Are continuously formed and patterned into a desired shape.
[0165]
Of course, it is not limited to a three-layer structure, and may be a single-layer structure or a two-layer structure, or may be a laminated structure of four or more layers. The wiring material is not limited to Al and Ti, and other conductive films may be used. For example, a wiring may be formed by patterning a laminated film in which Al or Cu is formed on a TaN film and a Ti film is further formed.
[0166]
Here, part of the pixel electrode 5039 and part of the wiring 5045 are formed so as to overlap each other, whereby the wiring 5045 and the pixel electrode 5039 are electrically connected to each other (FIG. 14B).
[0167]
Through the above steps, as illustrated in FIG. 14B, a driver circuit portion including an N-channel TFT and a pixel portion including a switching TFT and a driving TFT can be formed over the same substrate.
[0168]
The N-channel TFT in the driver circuit portion includes a low-concentration impurity region 5026 (Lov region) that overlaps with the first conductive layer 5015a that forms part of the gate electrode, and a high-concentration impurity region 5025 that functions as a source region or a drain region. have.
[0169]
In the pixel portion, the N-channel switching TFT has a low concentration impurity region 5032 (Loff region) formed outside the gate electrode and a high concentration impurity region 5031 functioning as a source region or a drain region. .
[0170]
Next, a third interlayer insulating film 5047 is formed. As the third interlayer insulating film 5047, an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, a silicon nitride oxide film formed by a sputtering method, or the like can be used. . An acrylic resin film or the like can be used as the organic insulating film.
[0171]
Examples of combinations of the second interlayer insulating film 5038 and the third interlayer insulating film 5047 are given below.
[0172]
As the second interlayer insulating film 5038, a combination of using a laminated film of acrylic and a silicon nitride oxide film formed by a sputtering method and using a silicon nitride oxide film formed by a sputtering method as the third interlayer insulating film 5047. is there. Further, there is a combination in which a silicon oxide film formed by an SOG method is used as the second interlayer insulating film 5038 and a silicon oxide film formed by the SOG method is used as the third interlayer insulating film 5047. Further, a stacked film of a silicon oxide film formed by an SOG method and a silicon oxide film formed by a plasma CVD method is used as the second interlayer insulating film 5038, and an oxide formed by a plasma CVD method is used as the third interlayer insulating film 5047. There is a combination using a silicon film. Further, there is a combination in which acrylic is used for the second interlayer insulating film 5038 and acrylic is also used for the third interlayer insulating film 5047. Further, there is a combination in which a laminated film of acrylic and a silicon oxide film formed by a plasma CVD method is used as the second interlayer insulating film 5038, and a silicon oxide film formed by a plasma CVD method is used as the third interlayer insulating film 5047. . Further, there is a combination in which a silicon oxide film formed by a plasma CVD method is used as the second interlayer insulating film 5038 and acrylic is used as the third interlayer insulating film 5047.
[0173]
An opening is formed at a position corresponding to the pixel electrode 5039 of the third interlayer insulating film 5047. The third interlayer insulating film functions as a bank. When the opening is formed, a tapered sidewall can be easily formed by using a wet etching method. Care must be taken because the deterioration of the EL layer due to the step becomes a significant problem unless the side wall of the opening is sufficiently gentle.
[0174]
Carbon particles or metal particles may be added to the third interlayer insulating film 5047 to reduce the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 6 ~ 1x10 12 [Ωm] (preferably 1 × 10 8 ~ 1x10 Ten The added amount of carbon particles or metal particles may be adjusted so that [Ωm]).
[0175]
Next, an EL layer 5048 is formed over the pixel electrode 5039 exposed in the opening of the third interlayer insulating film 5047.
[0176]
As the EL layer 5048, a known organic light emitting material or inorganic light emitting material can be used.
[0177]
As the organic light emitting material, a low molecular weight organic light emitting material, a high molecular weight organic light emitting material, and a medium molecular weight organic material can be freely used. In the present specification, the medium molecular organic light-emitting material is an organic light-emitting material that does not have sublimation and has a molecule number of 20 or less or a chain molecule length of 10 [μm] or less. Shall be shown.
[0178]
The EL layer 5048 usually has a stacked structure. A typical example is a “hole transport layer / light emitting layer / electron transport layer” stacked structure proposed by Tang et al. Of Kodak Eastman Company. In addition, the hole injection layer / hole transport layer / light emitting layer / electron transport layer, or hole injection layer / hole transport layer / light emitting layer / electron transport layer / electron injection layer are laminated in this order on the anode. Structure may be sufficient. You may dope a fluorescent pigment | dye etc. with respect to a light emitting layer.
[0179]
In this embodiment, the EL layer 5048 is formed by a vapor deposition method using a low molecular weight organic light emitting material. Specifically, a 20 [nm] thick copper phthalocyanine (CuPc) film is provided as a hole injection layer, and a 70 [nm] thick tris-8-quinolinolato aluminum complex (Alq) is formed thereon as a light emitting layer. Three ) A laminated structure provided with a film. Alq Three The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1.
[0180]
Although only one pixel is shown in FIG. 14C, an EL layer 5048 corresponding to each of a plurality of colors, for example, R (red), G (green), and B (blue) is separately formed. can do.
[0181]
As an example of using a polymer organic light emitting material, a 20 nm thick polythiophene (PEDOT) film is provided by a spin coating method as a hole injection layer, and a paraphenylene vinylene having a light emitting layer of about 100 nm is provided thereon. The EL layer 5048 may be formed by a stacked structure provided with a (PPV) film. If a PPV π-conjugated polymer is used, the emission wavelength can be selected from red to blue. It is also possible to use an inorganic material such as silicon carbide for the electron transport layer or the electron injection layer.
[0182]
Note that the EL layer 5048 is not limited to a layer in which a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and the like are clearly distinguished. That is, the EL layer 5048 may have a structure including a layer in which materials constituting a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and the like are mixed.
[0183]
For example, a mixed layer composed of a material that constitutes an electron transport layer (hereinafter referred to as an electron transport material) and a material that constitutes a light emitting layer (hereinafter referred to as a light emitting material) may be a light emitting layer that emits light from the electron transport layer. The EL layer 5048 may be provided between the layers.
[0184]
Next, a pixel electrode 5049 made of a conductive film is provided over the EL layer 5048. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (an alloy film of magnesium and silver) may be used. The pixel electrode 5049 corresponds to the cathode of the EL element. As the cathode material, a conductive film made of an element belonging to Group 1 or Group 2 of the periodic table or a conductive film added with these elements can be used freely.
[0185]
When the pixel electrode 5049 is formed, the EL element is completed. Note that an EL element refers to an element formed of a pixel electrode (anode) 5039, an EL layer 5048, and a pixel electrode (cathode) 5049.
[0186]
It is effective to provide the passivation film 5050 so as to completely cover the EL element. The passivation film 5050 is formed of an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film, and the insulating film can be used as a single layer or a combination of layers.
[0187]
A film with good coverage is preferably used as the passivation film 5050, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film or a CN film. Since the DLC film can be formed in a temperature range from room temperature to 100 [° C.] or less, it can be easily formed over the EL layer 5047 having low heat resistance. Further, the DLC film has a high blocking effect against oxygen and can suppress oxidation of the EL layer 5048.
[0188]
Note that after the formation of the third interlayer insulating film 5047, the steps from the formation of the passivation film 5050 to the formation of the passivation film 5050 are continuously performed by using a multi-chamber type (or inline type) film formation apparatus without being released into the atmosphere. It is effective.
[0189]
Actually, when the state shown in FIG. 14C is completed, a protective film (laminate film, ultraviolet curable resin film, etc.) or a light-transmitting material having high hermeticity and low degassing so as not to be exposed to the outside air. It is preferable to package (enclose) with a sealing material. At this time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the EL element is improved.
[0190]
In addition, if the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting the terminal drawn from the element or circuit formed on the substrate 5000 and the external signal terminal is attached. Completed as a product.
[0191]
Further, according to the steps shown in this embodiment, the number of photomasks necessary for manufacturing a light-emitting device can be suppressed. As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.
[0192]
[Example 5]
In this example, an example in which a light-emitting device is manufactured using the present invention will be described with reference to FIGS.
[0193]
15 is a top view of a light emitting device formed by sealing an element substrate on which a TFT is formed with a sealing material, and FIG. 15B is a cross-sectional view taken along line AA ′ of FIG. FIG. 15C is a cross-sectional view taken along the line BB ′ of FIG.
[0194]
A sealant 4009 is provided so as to surround the pixel portion 4002 provided over the substrate 4001, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004a and 4004b. In addition, a sealing material 4008 is provided over the pixel portion 4002, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004a and 4004b. Therefore, the pixel portion 4002, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004a and 4004b are sealed with the filler 4210 by the substrate 4001, the sealant 4009, and the sealant 4008. ing.
[0195]
In addition, the pixel portion 4002, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004a and 4004b provided over the substrate 4001 include a plurality of TFTs. In FIG. 15B, a TFT (note that an N-channel TFT and a P-channel TFT are illustrated here) 4201 and a pixel included in the source signal line driver circuit 4003 formed over the base film 4010 are typically shown. The TFT 4202 included in the portion 4002 is illustrated.
[0196]
An interlayer insulating film (planarization film) 4301 is formed on the TFTs 4201 and 4202, and a pixel electrode (anode) 4203 electrically connected to the drain of the TFT 4202 is formed thereon. As the pixel electrode 4203, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.
[0197]
An insulating film 4302 is formed over the pixel electrode 4203, and an opening is formed over the pixel electrode 4203 in the insulating film 4302. In this opening, an organic light emitting layer 4204 is formed on the pixel electrode 4203. A known organic light emitting material or inorganic light emitting material can be used for the organic light emitting layer 4204. The organic light emitting material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.
[0198]
As a method for forming the organic light emitting layer 4204, a known vapor deposition technique or coating technique may be used. The structure of the organic light emitting layer may be a laminated structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0199]
On the organic light emitting layer 4204, a cathode 4205 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper or silver as a main component or a laminated film of these with another conductive film) is formed. The In addition, it is desirable to remove moisture and oxygen present at the interface between the cathode 4205 and the organic light emitting layer 4204 as much as possible. Therefore, it is necessary to devise a method in which the organic light emitting layer 4204 is formed in a nitrogen or rare gas atmosphere and the cathode 4205 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation can be performed by using a multi-chamber type (cluster tool type) film formation apparatus. The cathode 4205 is given a predetermined voltage.
[0200]
As described above, the light emitting element 4303 including the pixel electrode (anode) 4203, the organic light emitting layer 4204, and the cathode 4205 is formed. A protective film 4303 is formed over the insulating film 4302 so as to cover the light emitting element 4303. The protective film 4303 is effective in preventing oxygen, moisture, and the like from entering the light emitting element 4303.
[0201]
Reference numeral 4005a denotes a lead wiring connected to the power supply line, which is connected to the first electrode of the TFT 4202. The lead wiring 4005 a passes between the sealant 4009 and the substrate 4001 and is electrically connected to the FPC wiring 4301 included in the FPC 4006 through the anisotropic conductive film 4300.
[0202]
As the sealing material 4008, a glass material, a metal material (typically a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. As the plastic material, an FRP (Fiberglass-Reinforced-Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.
[0203]
However, when the light emission direction from the light emitting element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.
[0204]
Further, as the filler 4210, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicon resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.
[0205]
In order to expose the filler 4210 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, a recess 4007 is provided on the surface of the sealing material 4008 on the substrate 4001 side to adsorb the hygroscopic substance or oxygen. A possible substance 4207 is arranged. In order to prevent the hygroscopic substance or the substance 4207 capable of adsorbing oxygen from scattering, the concave part cover material 4208 holds the hygroscopic substance or the substance 4207 capable of adsorbing oxygen in the concave part 4007. Note that the concave cover material 4208 has a fine mesh shape, and is configured to allow air and moisture to pass therethrough but not a hygroscopic substance or a substance 4207 capable of adsorbing oxygen. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the light-emitting element 4303 can be suppressed.
[0206]
As shown in FIG. 15C, a conductive film 4203a is formed so as to be in contact with the lead wiring 4005a at the same time as the pixel electrode 4203 is formed.
[0207]
The anisotropic conductive film 4300 has a conductive filler 4300a. By thermally pressing the substrate 4001 and the FPC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.
[0208]
[Example 6]
In the present invention, by using an organic light emitting material that can utilize phosphorescence from triplet excitons for light emission, the external light emission quantum efficiency can be dramatically improved. This makes it possible to reduce the power consumption, extend the life, and reduce the weight of the light emitting element.
[0209]
Here, a report of using triplet excitons to improve the external emission quantum efficiency is shown.
(T. Tsutsui, C. Adachi, S. Saito, Photochemical Processes in Organized Molecular Systems, ed. K. Honda, (Elsevier Sci. Pub., Tokyo, 1991) p.437.)
[0210]
The molecular formula of the organic light-emitting material (coumarin dye) reported by the above paper is shown below.
[0211]
[Chemical 1]
[0212]
(MABaldo, DFO'Brien, Y.You, A.Shoustikov, S.Sibley, METhompson, SRForrest, Nature 395 (1998) p.151.)
[0213]
The molecular formula of the organic light-emitting material (Pt complex) reported by the above paper is shown below.
[0214]
[Chemical formula 2]
[0215]
(MABaldo, S. Lamansky, PEBurrrows, METhompson, SRForrest, Appl.Phys.Lett., 75 (1999) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)
[0216]
The molecular formula of the organic light emitting material (Ir complex) reported by the above paper is shown below.
[0217]
[Chemical 3]
[0218]
As described above, if phosphorescence emission from triplet excitons can be used, in principle, it is possible to realize an external emission quantum efficiency that is 3 to 4 times higher than that in the case of using fluorescence emission from singlet excitons.
[0219]
[Example 7]
Since a light-emitting device using a light-emitting element is a self-luminous type, it has excellent visibility in a bright place and a wide viewing angle compared to a liquid crystal display. Therefore, it can be used for display portions of various electronic devices.
[0220]
As an electronic device using the light emitting device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device, A portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), an image playback device equipped with a recording medium (specifically, a recording medium such as a Digital Versatile Disc (DVD), etc.) A device provided with a display capable of displaying). In particular, it is desirable to use a light-emitting device for a portable information terminal that often has an opportunity to see a screen from an oblique direction because the wide viewing angle is important. Specific examples of these electronic devices are shown in FIGS.
[0221]
FIG. 20A illustrates a light-emitting element display device which includes a housing 3001, a support base 3002, a display portion 3003, a speaker portion 3004, a video input terminal 3005, and the like. The light emitting device of the present invention can be used for the display portion 3003. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. The light emitting element display device includes all information display devices such as a personal computer, a TV broadcast receiver, and an advertisement display.
[0222]
FIG. 20B illustrates a digital still camera, which includes a main body 3101, a display portion 3102, an image receiving portion 3103, operation keys 3104, an external connection port 3105, a shutter 3106, and the like. The light emitting device of the present invention can be used for the display portion 3102.
[0223]
FIG. 20C illustrates a laptop personal computer which includes a main body 3201, a housing 3202, a display portion 3203, a keyboard 3204, an external connection port 3205, a pointing mouse 3206, and the like. The light emitting device of the present invention can be used for the display portion 3203.
[0224]
FIG. 20D illustrates a mobile computer, which includes a main body 3301, a display portion 3302, a switch 3303, operation keys 3304, an infrared port 3305, and the like. The light-emitting device of the present invention can be used for the display portion 3302.
[0225]
FIG. 20E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 3401, a housing 3402, a display portion A3403, a display portion B3404, a recording medium (DVD or the like). A reading unit 3405, operation keys 3406, a speaker unit 3407, and the like are included. Although the display portion A 3403 mainly displays image information and the display portion B 3404 mainly displays character information, the light-emitting device of the present invention can be used for the display portions A, B 3403, and 3404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0226]
FIG. 20F illustrates a goggle type display (head mounted display), which includes a main body 3501, a display portion 3502, and an arm portion 3503. The light emitting device of the present invention can be used for the display portion 3502.
[0227]
FIG. 20G shows a video camera, which includes a main body 3601, a display portion 3602, a housing 3603, an external connection port 3604, a remote control receiving portion 3605, an image receiving portion 3606, a battery 3607, an audio input portion 3608, operation keys 3609, and the like. . The light-emitting device of the present invention can be used for the display portion 3602.
[0228]
FIG. 20H illustrates a mobile phone, which includes a main body 3701, a housing 3702, a display portion 3703, an audio input portion 3704, an audio output portion 3705, operation keys 3706, an external connection port 3707, an antenna 3708, and the like. The light-emitting device of the present invention can be used for the display portion 3703. Note that the display portion 3703 can suppress current consumption of the mobile phone by displaying white characters on a black background.
[0229]
If the light emission luminance of the organic light emitting material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used in a front type or rear type projector.
[0230]
In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the organic light emitting material has a very high response speed, the light emitting device is preferable for displaying moving images.
[0231]
In addition, since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background. It is desirable to do.
[0232]
As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic device of this embodiment may use the light emitting device having any structure shown in Embodiments 1 to 6.
[0233]
[Example 8]
In this embodiment, a top view of the pixel structure shown in FIG. 21 is described with reference to FIG.
[0234]
In FIG. 22, a plurality of active layers are provided by patterning the same layer (same layer) in a region where a TFT is formed, and then a first gate line 2102, a second gate line 2103, and a gate electrode of each transistor. Are provided by patterning the same layer (same layer), and then the source signal line 2101 and the current supply line 2108 are provided by patterning the same layer (same layer), and finally the EL element (light emitting element) One electrode (here, referred to as an anode) is provided.
[0235]
A selection TFT 2104 in which a part of the first gate line 2102 becomes a gate electrode is provided. The TFT 2104 has a double gate structure in which two gate electrodes are provided in one active layer, so that selection (switching) is ensured as compared with a single gate structure in which one gate electrode is provided in one active layer. It can be carried out. The TFT 2104 can also have a multi-gate structure in which three or more gate electrodes are provided in one active layer.
[0236]
In addition, the channel length (L) of the TFT 2105 is increased in order to reduce variations in the TFT. Further, by increasing L, the saturation region of the TFT can be flattened.
[0237]
Further, a TFT 2106 having a gate electrode connected to the second gate line 2103 through a contact is provided. In addition, a storage capacitor 2107 formed of an active layer and the same layer as the scan line is provided.
[0238]
Such a TFT configuration uses a top gate type structure in which a gate electrode is on a semiconductor film (channel formation region) and a reverse bottom gate type structure, and is offset in an impurity region (source region or drain region). A structure or a GOLD structure may be used.
【The invention's effect】
According to the present invention, in a semiconductor device configured using a unipolar TFT, particularly an N-channel TFT having excellent electrical characteristics as an element, the gate-source voltage of the driving TFT does not fluctuate due to deterioration of the EL element. Thus, even when the EL element is deteriorated, it is possible to make it difficult for the luminance to decrease. In addition, the configuration proposed in the present invention is not particularly complicated, and does not greatly increase the number of elements constituting the pixel, so that it can be applied without incurring a demerit such as a decrease in aperture ratio. It can be said that it is very useful.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an embodiment of the present invention and its operation.
FIG. 2 is a diagram for explaining an operation when a TFT is unipolar in a conventional configuration.
FIG. 3 is a diagram for explaining the operation of the circuit having the configuration of FIG. 1;
FIG. 4 is a diagram illustrating an embodiment of the present invention and its operation.
FIG. 5 is a diagram illustrating an embodiment of the present invention and its operation.
FIG. 6 is a diagram illustrating an embodiment of the present invention and its operation.
FIG. 7 is a diagram comparing the present invention with a conventional example regarding a change in potential around a gate electrode and a source region of a driving TFT.
FIG. 8 is a diagram for introducing an example of a pixel including a unipolar TFT.
FIG. 9 is a diagram showing an embodiment of the present invention.
FIG. 10 is a diagram illustrating a time gray scale method.
FIG. 11 illustrates a time gray scale method.
FIG. 12 is a diagram for explaining an embodiment of the present invention and its operation.
13A and 13B illustrate a manufacturing process of a semiconductor device.
14A to 14C illustrate a manufacturing process of a semiconductor device.
FIGS. 15A and 15B are a top view and a cross-sectional view of a semiconductor device. FIGS.
FIG. 16 is a diagram showing a configuration of a semiconductor device that performs display using an analog video signal.
17 is a diagram showing an example of a source signal line driver circuit and a gate signal line driver circuit in the apparatus of FIG.
FIG 18 illustrates a structure of a semiconductor device that performs display using a digital video signal.
FIG. 19 is a diagram showing an example of a source signal line driver circuit in the apparatus of FIG.
FIG. 20 illustrates an example of an electronic device to which the present invention can be applied.
FIG. 21 is a diagram illustrating an embodiment of the present invention and its operation.
FIG 22 is a top view of a pixel structure of the invention.

Claims (9)

  1. And switching elements, and the first to third transistors, a capacitance element, a light emitting element, a source signal line, and first and second gate signal lines, a current supply line, first and second power supply Line and
    One end of the switching element, the source signal line and is electrically connected to the other end of the switching element is electrically connected to a gate of said first transistor,
    The first electrode of the second transistor, said the first electrode and electrically connected to the first transistor, the second electrode of the second transistor is electrically said first power supply line And the gate of the second transistor is electrically connected to the first gate signal line,
    A first electrode of the third transistor, the first being the second electrode and electrically connected to the transistor, the second electrode of the third transistor, the current supply line and electrically connected A gate of the third transistor is electrically connected to the second gate signal line;
    The first electrode of the first transistor is electrically connected to one end of the light emitting element,
    The other end of the light emitting element is electrically connected to the second power supply line,
    Characterized in that one end of said capacitive element, said first electrically connected to the gate of the transistor, the other end of the capacitive element, which is the first electrode and electrically connected to said first transistor Display device.
  2. And switching elements, and the first to third transistors, a capacitance element, a light emitting element, a source signal line, and first and second gate signal lines, a current supply line, first and second power supply Line and
    One end of the switching element, the source signal line and is electrically connected to the other end of the switching element is electrically connected to a gate of said first transistor,
    The first electrode of the second transistor, said the first electrode and electrically connected to the first transistor, the second electrode of the second transistor is electrically said first power supply line And the gate of the second transistor is electrically connected to the first gate signal line,
    The first electrode of the third transistor, said first electrically connected to the gate of the transistor, a second electrode of the third transistor, a first electrode electrically of the first transistor And the gate of the third transistor is electrically connected to the second gate signal line,
    The first electrode of the first transistor is electrically connected to one end of the light emitting element, a second electrode of the first transistor is connected the current supply line and electrically,
    The other end of the light emitting element is electrically connected to the second power supply line,
    Characterized in that one end of said capacitive element, said first electrically connected to the gate of the transistor, the other end of the capacitive element, which is the first electrode and electrically connected to said first transistor Display device.
  3. And switching elements, and the first to third transistors, a capacitance element, a light emitting element, a source signal line, and first and second gate signal lines, a current supply line, first and second power supply Line and
    One end of the switching element, the source signal line and is electrically connected to the other end of the switching element is electrically connected to a gate of said first transistor,
    The first electrode of the second transistor, said the first electrode and electrically connected to the first transistor, the second electrode of the second transistor is electrically said first power supply line And the gate of the second transistor is electrically connected to the first gate signal line,
    The first electrode of the third transistor is electrically connected to the gate of the first transistor, and the second electrode of the third transistor is electrically connected to the first power supply line. , The gate of the third transistor is electrically connected to the second gate signal line,
    The first electrode of the first transistor is electrically connected to one end of the light emitting element, a second electrode of the first transistor is connected the current supply line and electrically,
    The other end of the light emitting element is electrically connected to the second power supply line,
    Characterized in that one end of said capacitive element, said first electrically connected to the gate of the transistor, the other end of the capacitive element, which is the first electrode and electrically connected to said first transistor Display device.
  4. In any one of Claim 1 thru | or 3 ,
    The conductivity type of the first transistor is an N-channel type,
    Characterized in that it has a relationship of the potential V 1 of the current supply line, the first potential V 2 of the power supply line, potential V 3 of the second power supply line is V 1> V 2, and V 1> V 3 Display device.
  5. In any one of Claims 1 thru | or 4 ,
    The potential V 2 of the first power supply line, potential V 3 of the second power supply line display device characterized by having a relationship of V 2 <V 3.
  6. In any one of Claim 1 thru | or 3 ,
    The conductivity type of the first transistor is a P-channel type,
    The potential V 1 of the the current supply line, characterized in that it has a relationship of the first potential V 2 of the power supply line, potential V 3 of the second power supply line is V 1 <V 2, and V 1 <V 3 A display device.
  7. In any one of Claims 1 to 3 and Claim 6 ,
    The display device, wherein the potential V 2 of the first power supply line and the potential V 3 of the second power supply line have a relationship of V 2 > V 3 .
  8. In any one of Claims 1 thru | or 7 ,
    Video signal from said source signal line, via the switching element, a display device, characterized in that input to the gate of the first transistor.
  9. In claim 8 ,
    The display device, wherein the video signal is a voltage signal.
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