JP2001083924A - Drive circuit and drive method of current control type light emitting element - Google Patents

Drive circuit and drive method of current control type light emitting element

Info

Publication number
JP2001083924A
JP2001083924A JP25438699A JP25438699A JP2001083924A JP 2001083924 A JP2001083924 A JP 2001083924A JP 25438699 A JP25438699 A JP 25438699A JP 25438699 A JP25438699 A JP 25438699A JP 2001083924 A JP2001083924 A JP 2001083924A
Authority
JP
Japan
Prior art keywords
voltage
circuit
light emitting
emitting element
buffer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25438699A
Other languages
Japanese (ja)
Inventor
Yutaka Minamino
裕 南野
Atsuhiro Yamano
敦浩 山野
Takashi Okada
隆史 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP25438699A priority Critical patent/JP2001083924A/en
Publication of JP2001083924A publication Critical patent/JP2001083924A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0819Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/027Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/04Maintaining the quality of display appearance
    • G09G2320/043Preventing or counteracting the effects of ageing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit for uniformly gradation-controlling an EL that is a current driving element according to an external input signal by containing, in a buffer, a circuit for compensating the offset voltage that is the difference between the input terminal voltage of a buffer element and the voltage outputted from the output terminal of the buffer element. SOLUTION: Since the charging voltage of a load is VIN-Vt when no offset canceller is attached, the dispersion of threshold voltage Vt appears as an output deviation. However, when an offset canceller is attached, the charging voltage of the load is equal to the input voltage VIN and basically never influenced by the dispersion of the threshold voltage Vt. A circuit for compensating the offset voltage resulted from the dispersion of the threshold voltage Vt is built in a transistor for controlling the luminance of a light emitting element. Therefore, this drive circuit for light emitting element capable of providing a satisfactory image characteristic with a relatively small number of transistors can be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ディスプレイに用
いられる発光素子の駆動装置に関し、特に有機及び無機
EL(エレクトロルミネンス)、又はLED(発光ダイ
オード)等のような発光輝度が素子を流れる電流により
制御される電流制御型発光素子の駆動回路の構成ならび
に駆動方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for a light emitting element used for a display, and more particularly, to a current flowing through the element such as an organic and inorganic EL (electroluminescence) or an LED (light emitting diode). The present invention relates to a configuration and a driving method of a drive circuit of a current control type light-emitting element controlled by the device.

【0002】[0002]

【従来の技術】有機及び無機EL、又はLED等のよう
な発光素子をアレイ状に組み合わせ、ドットマトリクス
により文字表示を行うディスプレイは、テレビ、携帯端
末等に広く利用されている。
2. Description of the Related Art Displays which combine light emitting elements such as organic and inorganic ELs or LEDs in an array and display characters using a dot matrix are widely used in televisions, portable terminals and the like.

【0003】特に、自発光素子を用いたこれらのディス
プレイは、液晶を用いたディスプレイと異なり、照明の
ためのバックライトを必要としない、視野角が広い等の
特徴を有し、注目を集めている。
[0003] In particular, these displays using self-luminous elements, unlike displays using liquid crystal, have features such as not requiring a backlight for illumination and having a wide viewing angle, and have attracted attention. I have.

【0004】中でも、トランジスタ等とこれらの発光素
子とを組み合わせてスタティック駆動を行うアクティブ
マトリクス型と呼ばれるディスプレイは、ダイナミック
駆動を行う単純マトリクス駆動のディスプレイと比較し
て、高輝度、高コントラスト、高精細等の優位性を持っ
ており近年注目されている。
[0004] Above all, an active matrix type display which performs static driving by combining a transistor or the like and these light emitting elements is higher in brightness, higher contrast and higher definition than a simple matrix driving display which performs dynamic driving. Etc., and has been attracting attention in recent years.

【0005】この種のディスプレイの従来例として、図
7に、Society for Information Display発行の1997年
秋期大会予稿集『Asiadisplay '97』の第216〜219頁
(セイコーエプソン)の発表から引用した、発光素子に
ELを使用したアクティブマトリクス型ディスプレイの
発光素子駆動回路を示す。
[0005] As a conventional example of this type of display, FIG. 7 shows a light emission quoted from the announcement of the Society for Information Display's 1997 Autumn Conference Proceedings "Asiadisplay '97", pp. 216-219 (Seiko Epson). 1 shows a light emitting element driving circuit of an active matrix display using EL as an element.

【0006】図7を参照して、この駆動回路での発光原
理を説明する。スイッチング用トランジスタ71のゲー
トに接続された走査線72が選択されて活性化される
と、トランジスタ71がオン状態となり、トランジスタ
71に接続されたデータ線73から信号がコンデンサ7
4に書き込まれる。コンデンサ74は電流制御用トラン
ジスタ75のゲート・ソース間電圧を決定する。
The principle of light emission in this drive circuit will be described with reference to FIG. When the scanning line 72 connected to the gate of the switching transistor 71 is selected and activated, the transistor 71 is turned on, and a signal is transmitted from the data line 73 connected to the transistor 71 to the capacitor 7.
4 is written. The capacitor 74 determines the gate-source voltage of the current control transistor 75.

【0007】そして、走査線72が非選択となりトラン
ジスタ71がオフ状態になると、コンデンサ74の両端
間の電圧は次の周期に走査線72が選択されるまで保持
される。
When the scanning line 72 is not selected and the transistor 71 is turned off, the voltage between both ends of the capacitor 74 is held until the scanning line 72 is selected in the next cycle.

【0008】コンデンサ74の両端間の電圧に応じて、
電源電極76→トランジスタ75のドレイン−ソース→
EL素子77→共通電極78という経路に沿って電流が
流れ、この電流によりEL素子77が発光する。
According to the voltage between both ends of the capacitor 74,
Power supply electrode 76 → Drain-source of transistor 75 →
A current flows along the path from the EL element 77 to the common electrode 78, and this current causes the EL element 77 to emit light.

【0009】一般的にコンピュータの端末、パソコンの
モニタ、テレビ等の動画表示を行うためには、各画素の
輝度が変化する階調表示が出来ることが望ましい。
In general, in order to display moving images on a computer terminal, a personal computer monitor, a television, or the like, it is desirable to be able to perform gradation display in which the luminance of each pixel changes.

【0010】図7の駆動回路において階調表示を行うに
は、トランジスタ75のゲート・ソース電極間に閾値付
近の電圧を印加する必要がある。
In order to perform gradation display in the drive circuit of FIG. 7, it is necessary to apply a voltage near the threshold value between the gate and source electrodes of the transistor 75.

【0011】しかし、トランジスタのゲート電圧・ソー
ス電流特性に、図8に示すようなばらつきがあると、例
えば図7のトランジスタ75のゲート電極にゲート電圧
VAを印加した場合、トランジスタ75に流れる電流は
IA(実線で示す曲線とVAとの交点)とIB(破線で
示す曲線とVAとの交点)のように異なるため、EL素
子77に流れる電流も変わり、本来ならば同じ輝度であ
るはずの領域の輝度が異なり、このため、例えば輝度む
ら等の画質劣化が生じることになる。
However, if the gate voltage-source current characteristics of the transistors have variations as shown in FIG. 8, for example, when a gate voltage VA is applied to the gate electrode of the transistor 75 in FIG. Since IA (intersection between the curve indicated by the solid line and VA) and IB (intersection between the curve indicated by the dashed line and VA), the current flowing through the EL element 77 also changes, and the area that should have the same luminance should be the same. Are different from each other, which causes image quality deterioration such as uneven brightness.

【0012】ポリシリコンを材料とした薄膜トランジス
タにおいては、結晶シリコンによるトランジスタに比較
して、一般的にこのしきい値のばらつきが大きく、その
値は±0.1V程度と推察される。
[0012] In a thin film transistor using polysilicon, the variation in the threshold value is generally larger than that in a transistor using crystalline silicon, and the value is estimated to be about ± 0.1 V.

【0013】しきい値が±0.1Vばらついたとすれ
ば、トランジスタ75を流れる電流は、しきい値が2V
程度ならばリニア領域で動作させた場合は5%程度、飽
和領域で動作させた場合は10%程度電流値が変動す
る。図9はEL素子の電流−輝度特性である。電流−輝
度特性は階調表示させる領域Aにおいてはリニアな特性
であるので、前期電流値のばらつきは、そのまま輝度特
性のばらつきとなって現れる。
If the threshold voltage varies by ± 0.1 V, the current flowing through the transistor 75 is 2 V
The current value fluctuates by about 5% when operating in the linear region, and by about 10% when operating in the saturation region. FIG. 9 shows current-luminance characteristics of the EL element. Since the current-luminance characteristic is a linear characteristic in the region A where the gradation is displayed, the variation of the current value directly appears as the variation of the luminance characteristic.

【0014】この問題を解決するため、特開平2−14
8687号公報には、素子の閾値付近でのばらつきがあ
っても、この影響を受けずに階調表示を行うELディス
プレイ装置が提案されている。
To solve this problem, Japanese Patent Laid-Open No. 2-14 / 1990
JP-A-8687 proposes an EL display device that performs gradation display without being affected by variations near the threshold value of the element.

【0015】図10を参照して、特開平2−14868
7号公報に提案される回路を説明する。図10は、図7
の点線内の電流制御回路79に対応する回路部を示して
おり、16階調表示を行う場合についての例を示すもの
である。階調制御を行うためにデータ線の本数は4本に
増加している。
With reference to FIG.
The circuit proposed in Japanese Patent Publication No. 7 will be described. FIG.
3 shows a circuit section corresponding to the current control circuit 79 in a dotted line, and shows an example of a case where 16 gradation display is performed. The number of data lines has been increased to four in order to perform gradation control.

【0016】図10において、94〜97は発光素子駆
動用のトランジスタ、98はカレントミラー回路、99
は発光素子、100はトランジスタの各ソース端子及び
発光素子が接続された共通電極の抵抗成分である。トラ
ンジスタ94〜97のドレイン電極は共通接続されてカ
レントミラー回路98の入力端に接続されている。
In FIG. 10, reference numerals 94 to 97 denote transistors for driving light emitting elements, 98 denotes a current mirror circuit, and 99 denotes a current mirror circuit.
Is a light emitting element, and 100 is a resistance component of each source terminal of the transistor and a common electrode to which the light emitting element is connected. The drain electrodes of the transistors 94 to 97 are commonly connected and connected to the input terminal of the current mirror circuit 98.

【0017】図10において、4ビット入力より階調に
対応した組み合わせの信号電圧がトランジスタ94〜9
7のゲート電圧として印加される。そして、トランジス
タ94〜97のうちオン状態のトランジスタに流れる電
流の合計値と同一の電流値がカレントミラー回路98の
出力端から発光素子99に供給され、その電流値に応じ
て発光素子99が発光する。
In FIG. 10, a combination of signal voltages corresponding to gradations from 4-bit inputs is applied to transistors 94-9.
7 is applied as the gate voltage. Then, the same current value as the sum of the currents flowing through the ON transistors among the transistors 94 to 97 is supplied to the light emitting element 99 from the output terminal of the current mirror circuit 98, and the light emitting element 99 emits light according to the current value. I do.

【0018】例えばトランジスタ94〜97がオン時の
電流値の対数をとった値をそれぞれ倍になるようにすれ
ば(即ち、I2はI1の2倍、I3はI2の2倍(=I
1の22倍)、I4はI3の2倍(=I1の23倍)とす
れば)、トランジスタ94〜97のオンする組み合わせ
により16階調の表示を行うことができる。なお、I1
〜I4はトランジスタ94〜97がオン状態時のソース
電流をそれぞれ表している。
For example, if the values obtained by taking the logarithms of the current values when the transistors 94 to 97 are turned on are respectively doubled (ie, I2 is twice I1 and I3 is twice I2 (= I
(2 times 1), I4 is 2 times I3 (= 23 times I1), and 16 gradations can be displayed by the combination of turning on the transistors 94 to 97. Note that I1
I4 represent source currents when the transistors 94-97 are on.

【0019】このときトランジスタを図8のゲート電圧
VBに対応する電流が飽和した領域の電圧で使用するよ
うにすれば、トランジスタの閾値付近での特性がばらつ
いていても、その影響を受けるがことなく、輝度のばら
つきも生じない。しかしながら階調数が増えた場合カレ
ントミラー回路が増加すると共に、ビットにおおじて信
号線の数が増加し駆動回路が複雑となる。
At this time, if the transistor is used at a voltage in a region where the current corresponding to the gate voltage VB shown in FIG. 8 is saturated, even if the characteristics of the transistor in the vicinity of the threshold value vary, the influence is affected. There is no luminance variation. However, when the number of gradations increases, the number of current mirror circuits increases, and the number of signal lines increases depending on bits, which complicates the driving circuit.

【0020】[0020]

【発明が解決しようとする課題】上述のように、アクテ
ィブマトリックス型のEL発光装置においては、これま
では階調表示を実現させるために、カレントミラー回路
あるいは低電流回路及び電流制御用トランジスタなどを
1画素内に設ける必要がある。生産等を考慮した場合、
複数個のトランジスタを画素内に設けることは、トラン
ジスタの不良確率の増加による歩留まりの低下が予想さ
れ、高い歩留まりを確保するためには1画素内に少ない
トランジスタで階調表示させる、望ましくは必要最小限
のトランジスタ数で階調表示を実現させることが必要で
ある。加えてトランジスタ数の増加に伴いEL素子の発
光に関わる有効な部分の面積が減少する。このような問
題を解決するためには図7の駆動回路において電流駆動
用のTFTのしきい値電圧のばらつきを補正することが
可能なシンプルな回路構成の提案が必要である。
As described above, in an active matrix type EL light emitting device, a current mirror circuit or a low current circuit, a current controlling transistor, and the like have hitherto been used to realize a gray scale display. It must be provided within one pixel. When considering production, etc.,
Providing a plurality of transistors in a pixel is expected to decrease the yield due to an increase in the failure probability of the transistor. In order to secure a high yield, a gray scale display is performed with a small number of transistors in one pixel. It is necessary to realize gray scale display with a limited number of transistors. In addition, as the number of transistors increases, the area of an effective portion related to light emission of the EL element decreases. In order to solve such a problem, it is necessary to propose a simple circuit configuration capable of correcting the variation in the threshold voltage of the current driving TFT in the driving circuit of FIG.

【0021】[0021]

【課題を解決するための手段】本発明は前述の電流駆動
素子であるELを外部からの入力信号のレベルに応じて
ムラなく階調制御するための駆動回路を提案するもので
ある。具体的な回路構成は以下の通りである。
SUMMARY OF THE INVENTION The present invention proposes a driving circuit for controlling the EL, which is the above-mentioned current driving element, without unevenness in accordance with the level of an external input signal. The specific circuit configuration is as follows.

【0022】素子に流れる電流に応じて輝度が変化する
発光素子からなる画素を選択するための走査線と、前記
画素を駆動するための電圧を供給するデータ線とが基板
上にマトリクス状に配設され、前記走査線と前記データ
線との交差部に、発光素子の輝度を制御するための電圧
がデータ線より供給されており、前記走査線により与え
られる走査信号により前記データ線の電圧をスイッチン
グする第一の薄膜トランジスタと、前記発光素子にその
出力端子が接続され、前記スイッチング用の薄膜トラン
ジスタの出力端子とその入力端子が接続されているバッ
ファ素子と該バッファ素子の入力端子電圧と該バッファ
素子の出力端子から出力される電圧の差であるオフセッ
ト電圧が補償される回路がバッファ内部に内蔵されてい
るアクティブマトリクス型の電流制御型発光素子の駆動
回路を提案するものである。
A scanning line for selecting a pixel composed of a light emitting element whose luminance changes according to a current flowing through the element, and a data line for supplying a voltage for driving the pixel are arranged in a matrix on a substrate. A voltage for controlling the luminance of a light emitting element is supplied from a data line to an intersection of the scanning line and the data line, and a voltage of the data line is changed by a scanning signal given by the scanning line. A first thin film transistor for switching, an output terminal connected to the light emitting element, an output terminal of the thin film transistor for switching and an input terminal connected to the buffer element, an input terminal voltage of the buffer element, and the buffer element A circuit that compensates for the offset voltage, which is the difference between the voltages output from the output terminals of the It proposes a driving circuit of the box-type current-controlled light-emitting elements.

【0023】一般的には前記バッファ素子が前記発光素
子とソースフォロワ接続されており、ソースフォロワの
用いられる電流制御用薄膜トランジスタのしきい値電圧
のばらつきをキャンセルするための補償コンデンサ及び
該補償コンデンサにしきい値電圧を記憶させるためのス
イッチング回路が組み込まれている構成がシンプルな構
成であると思われる。
Generally, the buffer element is connected to the light emitting element by a source follower, and a compensation capacitor for canceling a variation in threshold voltage of a current control thin film transistor using the source follower, and a compensation capacitor for the compensation capacitor. It is considered that the configuration in which the switching circuit for storing the threshold voltage is incorporated is a simple configuration.

【0024】この構成では3種類の基本的構成が提案で
きる。
In this configuration, three basic configurations can be proposed.

【0025】(1−1)前記バッファ回路が前記発光素
子の入力端子とソースフォロワ接続されているn−チャ
ンネル型の薄膜トランジスタ及びから構成される場合、
(1−2)前記バッファ回路が前記発光素子の入力端子
とソースフォロワ接続されているp−チャンネル型の薄
膜トランジスタ及びから構成される場合、(1−3)前
記ソースフォロワがnチャンネルトランジスタとpチャ
ンネルトランジスタがプッシュプル接続された構成であ
る場合、である。バッファ回路としてソースフォロワ構
成以外の提案として、「前記バッファ素子が差動増幅器
により構成され、該差動増幅器の出力オフセットをキャ
ンセルするための補償コンデンサ及び該補償コンデンサ
にしきい値電圧を記憶させるためのスイッチング回路が
組み込まれている回路」があげられる。
(1-1) When the buffer circuit comprises an n-channel type thin film transistor which is connected to the input terminal of the light emitting element by a source follower,
(1-2) When the buffer circuit is composed of a p-channel type thin film transistor connected to the input terminal of the light emitting element and a source follower, (1-3) the source follower is an n-channel transistor and a p-channel transistor This is the case when the transistors have a push-pull connection configuration. As a proposal other than the source follower configuration as the buffer circuit, there is a proposal that “the buffer element is configured by a differential amplifier, a compensation capacitor for canceling an output offset of the differential amplifier, and a threshold voltage for storing a threshold voltage in the compensation capacitor. Circuit in which a switching circuit is incorporated ".

【0026】以上の回路構成を提案するものである。The above circuit configuration is proposed.

【0027】上記それぞれの構成における各ノードに印
加するタイミングチャートとこれに伴う各トランジスタ
の動作を説明する。
A timing chart applied to each node in each of the above structures and the operation of each transistor associated therewith will be described.

【0028】まずソースフォロワーの動作を説明する。
ここでは電流制御用のトランジスタがnチャンネル型の
場合を説明する。
First, the operation of the source follower will be described.
Here, a case where the current control transistor is an n-channel transistor will be described.

【0029】(1)入力電圧Vinがゲート電圧に印可
されると、トランジスタがONし、最初は大きなドレイ
ン電流が流れて負荷を充電するが、負荷の電圧が上昇す
るとトランジスタのソース電圧が上昇し、ゲート−ソー
ス間電圧が徐々に小さくなるのでドレイン電流が小さく
なり、ゲート−ソース間電圧がしきい値電圧Vtになる
まで負荷が充電されるとトランジスタはOFFし充電は
ストップする。
(1) When the input voltage Vin is applied to the gate voltage, the transistor turns on and a large drain current flows at first to charge the load. However, when the load voltage increases, the source voltage of the transistor increases. Since the gate-source voltage gradually decreases, the drain current decreases. When the load is charged until the gate-source voltage reaches the threshold voltage Vt, the transistor turns off and charging stops.

【0030】(2)ソースフォロワのゲートに入力電圧
Vinを印可した場合、負荷はVin−Vtまで充電さ
れることになりしきい値電圧Vtがばらつくと出力電圧
はそのまま出力偏差となって現れる。
(2) When the input voltage Vin is applied to the gate of the source follower, the load is charged up to Vin-Vt, and when the threshold voltage Vt varies, the output voltage appears as an output deviation as it is.

【0031】現状のポリシリコンではしきい値電圧のば
らつきは±0.5V程度の範囲であるためにこのままで
はしきい値電圧のばらつきが輝度のばらつきとなって現
れる。次にオフセットキャンセラー付きのソースフォロ
ワの動作を図1を用いて説明する。動作は大きく3ステ
ップに分けられる。
In the current polysilicon, the variation of the threshold voltage is in the range of about ± 0.5 V. Therefore, the variation of the threshold voltage appears as the variation of the luminance as it is. Next, the operation of the source follower with an offset canceller will be described with reference to FIG. The operation is roughly divided into three steps.

【0032】<第一ステップ>スイッチS1,S2,S
3がオンしゲートにはしきい値検出用電圧Vofがゲー
トに印可され、ソースはグランドに設置されるのでソー
スフォロワのトランジスタはオンする。同時にスイッチ
S5をオンすることによって、負荷の電荷を放電させ
る。負荷をリセットする理由はNchソースフォロワの
場合負荷を充電することは出来るが、負荷に蓄えられて
いる電荷を放電できないためである。
<First Step> Switches S1, S2, S
3 is turned on, the threshold detection voltage Vof is applied to the gate, and the source is set to the ground, so that the source follower transistor is turned on. At the same time, by turning on the switch S5, the load is discharged. The reason for resetting the load is that the load can be charged in the case of the Nch source follower, but the charge stored in the load cannot be discharged.

【0033】<第二ステップ>スイッチS3をオフする
事によりトランジスタを流れる電流をゼロにする。これ
によりトランジスタのソース電圧はゲート−ソース間電
圧がしきい値電圧Vtに等しくなるまで上昇する。その
結果しきい値検出用容量にはしきい値に等しい値が保持
される。
<Second Step> By turning off the switch S3, the current flowing through the transistor is reduced to zero. As a result, the source voltage of the transistor increases until the gate-source voltage becomes equal to the threshold voltage Vt. As a result, the threshold detection capacitor holds a value equal to the threshold.

【0034】<第三ステップ>スイッチS1、S2がオ
フされスイッチS0がオンされることによりトランジス
タのゲートにはしきい値検出用容量を通して入力電圧V
in+しきい値電圧Vtが印可される。従ってトランジ
スタのソース電圧は、ゲート電圧からしきい値電圧を引
いた値であるVinとなりスイッチS5をオフしてスイ
ッチS4をオンする事により負荷はVinの電圧まで充
電されることになる。
<Third Step> When the switches S1 and S2 are turned off and the switch S0 is turned on, the input voltage V is applied to the gate of the transistor through the threshold detection capacitor.
in + threshold voltage Vt is applied. Therefore, the source voltage of the transistor becomes Vin, which is a value obtained by subtracting the threshold voltage from the gate voltage, and the load is charged to Vin by turning off the switch S5 and turning on the switch S4.

【0035】以上の動作により、オフセットキャンセラ
ーを付けない場合は、負荷の充電電圧はVin−Vtで
あるので、しきい値電圧Vtがばらつくと出力偏差とな
って現れるが、オフセットキャンセラーを付けると、負
荷の充電電圧は入力電圧Vinと等しくなり、基本的に
しきい値電圧Vtのばらつきの影響を受けない。
According to the above operation, when the offset canceller is not provided, the load charging voltage is Vin-Vt. Therefore, when the threshold voltage Vt varies, the output appears as an output deviation. The charging voltage of the load becomes equal to the input voltage Vin, and is basically not affected by the variation of the threshold voltage Vt.

【0036】図2はオフセットキャンセラー付きソース
フォロワのシミュレーション結果である。シミュレーシ
ョン条件は (1)しきい値電圧ばらつきは±0.5Vを想定 (2)しきい値検出用容量は0.5pF、しきい値検出
用電圧Vof=7.5V (3)入力電圧=8.0V (4)1水平時間=30μsec である。
FIG. 2 is a simulation result of a source follower with an offset canceller. The simulation conditions are as follows: (1) Threshold voltage variation is assumed to be ± 0.5 V (2) Threshold detection capacitance is 0.5 pF, threshold detection voltage Vof = 7.5 V (3) Input voltage = 8 0.0 V (4) One horizontal time = 30 μsec.

【0037】第一ステップでは、ソースフォロワのトラ
ンジスタがオンされるが、スイッチS3のオン抵抗のた
め出力電圧(ソース電圧)は完全にゼロにならない。第
二ステップでは、しきい値ばらつきの影響により、出力
電圧がばらついていることが解る。しきい値検出用電圧
Vofと出力電圧の差がしきい値電圧Vtに等しく、こ
の値がしきい値検出用容量に記憶される。第三ステップ
では入力電圧Vinにしきい値電圧Vtを加えた値がゲ
ートに印可されるので、出力電圧はしきい値電圧に関係
なく、ほぼ入力電圧Vinに等しくなっている。オフセ
ットキャンセル能力は図3の下の図に示す拡大図より、
しきい値ばらつき0.5Vに対して、出力偏差は±10
mVまで抑制することが可能である。
In the first step, the transistor of the source follower is turned on, but the output voltage (source voltage) does not become completely zero due to the ON resistance of the switch S3. In the second step, it can be seen that the output voltage varies due to the influence of the threshold variation. The difference between the threshold detection voltage Vof and the output voltage is equal to the threshold voltage Vt, and this value is stored in the threshold detection capacitor. In the third step, a value obtained by adding the threshold voltage Vt to the input voltage Vin is applied to the gate, so that the output voltage is substantially equal to the input voltage Vin regardless of the threshold voltage. The offset canceling ability is shown in the enlarged view in the lower part of FIG.
The output deviation is ± 10 for a threshold variation of 0.5V.
mV.

【0038】以上は電流制御用トランジスタがnチャン
ネルの場合であるが、トランジスタがpチャンネルタイ
プの場合も想定される。
The above is the case where the current control transistor is an n-channel transistor, but it is also conceivable that the transistor is a p-channel transistor.

【0039】本回路構成を図4に示す。pチャンネルト
ランジスタはnチャンネルトランジスタに比較して電流
駆動能力は劣るが、トランジスタ信頼性の面ではnチャ
ンネルトランジスタよりも安定である。基本的にはpチ
ャンネルタイプの場合も同様なオフセットキャンセル動
作は可能であるが、pチャンネルソースフォロワは負荷
に対して放電しかできないので負荷を予め電源電圧まで
充電するプリチャージ回路が必要である。
FIG. 4 shows this circuit configuration. The p-channel transistor has lower current driving capability than the n-channel transistor, but is more stable than the n-channel transistor in terms of transistor reliability. Basically, a similar offset canceling operation is possible in the case of the p-channel type, but since the p-channel source follower can only discharge the load, a precharge circuit for charging the load to the power supply voltage in advance is required.

【0040】そのほかにn−チャンネルとp−チャンネ
ルをプッシュプル接続した回路が提案できる。プッシュ
プルは負荷に対して充電、放電共に出来るのでチャージ
ング回路は必要ない。プッシュプル回路を用いた場合の
構成を図5に示す。
In addition, a circuit in which an n-channel and a p-channel are push-pull connected can be proposed. Since the push-pull can charge and discharge the load, no charging circuit is required. FIG. 5 shows a configuration using a push-pull circuit.

【0041】次にバッファ構成として、差動増幅回路を
用いることは可能である。差動増幅回路はソースフォロ
ワ回路に比較して負帰還がかかるので、しきい値電圧ば
らつきに起因するオフセットを含めたすべてのオフセッ
トの原因如何に関わらずVinとVoutの差を検出す
る事が出来る。
Next, it is possible to use a differential amplifier circuit as the buffer configuration. Since the differential amplifier circuit receives a negative feedback as compared with the source follower circuit, the difference between Vin and Vout can be detected regardless of the cause of all offsets including the offset caused by threshold voltage variation. .

【0042】オフセットキャンセラー付き差動増幅回路
の動作を図6を使って説明する。
The operation of the differential amplifier circuit with an offset canceller will be described with reference to FIG.

【0043】<第一ステップ>2個のスイッチAがオン
し差動増幅器の反転入力端子と非反転入力端子間に検出
用容量が接続されたバッファ回路となる。差動増幅器の
非反転入力端子に入力電圧Vinが印可され、出力電圧
がVout=Vin+ΔVとなっているとする。バッフ
ァ回路を構成しているので、反転入力端子の電圧もVi
n+ΔVになる。従って検出用容量には非反転入力端子
の入力電圧Vinと、反転入力端子の出力電圧Vin+
ΔVの差であるΔVが検出され保持される。
<First Step> The two switches A are turned on to form a buffer circuit in which a detection capacitor is connected between the inverting input terminal and the non-inverting input terminal of the differential amplifier. It is assumed that the input voltage Vin is applied to the non-inverting input terminal of the differential amplifier, and the output voltage is Vout = Vin + ΔV. Since the buffer circuit is configured, the voltage of the inverting input terminal is also Vi.
n + ΔV. Therefore, the detection capacitor has an input voltage Vin of the non-inverting input terminal and an output voltage Vin + of the inverting input terminal.
ΔV, which is the difference between ΔV, is detected and held.

【0044】<第二ステップ>スイッチAがOFFされ
スイッチBがONされるので、出力電圧は検出用容量を
通して反転入力端子にフィードバックされる。非反転入
力端子には第一ステップ同様入力電圧Vinが印可され
ているので差動増幅器の内部回路は同じ状態を保つため
に反転入力端子の電圧はVin+ΔVにならなければな
らない。出力端子と反転入力端子間には、ΔVの電位差
を持った検出用容量が接続されているので、反転入力端
子の電圧がVin+ΔVになるためには、出力電圧はV
out=Vinにならなければならない。
<Second Step> Since the switch A is turned off and the switch B is turned on, the output voltage is fed back to the inverting input terminal through the detection capacitor. Since the input voltage Vin is applied to the non-inverting input terminal as in the first step, the voltage at the inverting input terminal must be Vin + ΔV in order to maintain the same state in the internal circuit of the differential amplifier. Since a detection capacitor having a potential difference of ΔV is connected between the output terminal and the inverting input terminal, in order for the voltage of the inverting input terminal to be Vin + ΔV, the output voltage must be V
out = Vin.

【0045】以上の動作により差動増幅回路にオフセッ
トキャンセラーを付けることで、様々な要因で発生する
出力偏差ΔVを抑制する事が出来る。出力電圧は常に入
力電圧Vinに等しい。
By adding an offset canceller to the differential amplifier circuit by the above operation, it is possible to suppress the output deviation ΔV caused by various factors. The output voltage is always equal to the input voltage Vin.

【0046】図11はオフセットキャンセラー付きオペ
アンプのシミュレーション結果である。シミュレーショ
ン条件としては (1)差動増幅回路のバッファ部はプッシュプル型 (2)出力偏差検出用容量=1.0pF (3)入力電圧=7.0V (4)負荷抵抗=1.0kΩ、負荷容量=20pF (5)1水平時間=30μsec を仮定し、しきい値ばらつきが±0.5Vの結果を図1
2に示す。
FIG. 11 shows a simulation result of an operational amplifier with an offset canceller. The simulation conditions are as follows: (1) The push-pull type buffer section of the differential amplifier circuit (2) Output deviation detection capacitance = 1.0 pF (3) Input voltage = 7.0 V (4) Load resistance = 1.0 kΩ, load Capacitance = 20 pF (5) Assuming that 1 horizontal time = 30 μsec, the result of ± 0.5 V variation in threshold voltage is shown in FIG.
It is shown in FIG.

【0047】第一ステップでは、しきい値ばらつきによ
り、入力電圧に対して出力電圧が大きくばらついている
が、この差を出力偏差検出用容量で検出し補正すること
により、第二ステップではしきい値ばらつきに影響され
ることなく、出力電圧は入力電圧にほぼ等しくなってい
る。オフセットキャンセル能力は図12の下の拡大図よ
り、しきい値ばらつき±0.5Vに対して、出力偏差±
5mVまで抑制できることが出来る。
In the first step, the output voltage greatly varies with respect to the input voltage due to the variation in the threshold value. The difference is detected and corrected by the output deviation detecting capacitor, and the second step is the threshold. The output voltage is almost equal to the input voltage without being affected by the value variation. From the enlarged view at the bottom of FIG. 12, the offset canceling capability shows that the output deviation ±
It can be suppressed up to 5 mV.

【0048】[0048]

【発明の実施の形態】図面を参照して、本発明の実施例
を以下に説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0049】(実施例1)図1は本発明の第1の実施例
の回路図であり、発光素子として電荷注入型の有機薄膜
EL素子(以下「有機薄膜EL素子」と略記する)を用
いた場合のものである。
(Embodiment 1) FIG. 1 is a circuit diagram of a first embodiment of the present invention, wherein a charge injection type organic thin film EL element (hereinafter abbreviated as "organic thin film EL element") is used as a light emitting element. It is when it was.

【0050】図1において、15は発光素子である有機
薄膜EL素子、12は有機薄膜EL素子15に流れる電
流を制御する抵抗素子、14は有機EL素子に電流を流
し続けるコンデンサ、13はコンデンサ14に信号電圧
を供給するスイッチングトランジスタ、16はスイッチ
ングトランジスタ13を選択する走査信号を供給する走
査線、17は走査線16がオンとされ選択されたスイッ
チングトランジスタ13を介してコンデンサ14に電荷
を供給するデータ線、18は有機薄膜EL素子14に電
流を供給する電源電極、19はデータ線17との間の電
位差でトランジスタの動作点を決定する共通電極であ
る。
In FIG. 1, reference numeral 15 denotes an organic thin-film EL element which is a light-emitting element; 12, a resistance element for controlling a current flowing through the organic thin-film EL element 15; 14, a capacitor which keeps current flowing through the organic EL element; , A scanning line for supplying a scanning signal for selecting the switching transistor 13, and a scanning line 16 is turned on to supply a charge to the capacitor 14 via the selected switching transistor 13. A data line, 18 is a power supply electrode for supplying a current to the organic thin-film EL element 14, and 19 is a common electrode for determining the operating point of the transistor based on a potential difference between the data line 17.

【0051】上述の駆動回路のよる発光原理は先に述べ
た通りである。
The principle of light emission by the above driving circuit is as described above.

【0052】ポリシリコンは気相成長法によりアモルフ
ァスシリコンを堆積しレーザーアニールする事で溶融再
結晶化しポリシリコンとなる。前記ポリシリコン中にイ
オンドーピング法によりリンイオンを打ち込みトランジ
スタのソース及びドレイン電極部を作成する。抵抗素子
12は前記トランジスタのソース及びドレイン領域とな
る部分と同一のプロセスで作成されている。本実施例1
では電流制御用トランジスタをnチャンネル型としてい
る。従ってスイッチング回路として負荷を放電させるこ
とが出来ないので負荷の電荷をリセットさせる回路を設
けた。
Polysilicon is melt-recrystallized by depositing amorphous silicon by a vapor phase growth method and performing laser annealing to form polysilicon. Phosphorus ions are implanted into the polysilicon by an ion doping method to form source and drain electrode portions of the transistor. The resistance element 12 is formed by the same process as that for forming the source and drain regions of the transistor. Example 1
In this example, the current control transistor is an n-channel transistor. Therefore, since a load cannot be discharged as a switching circuit, a circuit for resetting the charge of the load is provided.

【0053】(実施例2)実施例2における回路構成を
図4に示す。本実施例は電流制御トランジスタをpチャ
ンネルタイプとしたものである。この駆動回路の発光原
理は基本的に実施例1と同様であるが、pチャンネルト
ラジスタは負荷に対して放電しかできないので、負荷を
予め電源電圧まで充電するプリチャージ回路を負荷し
た。
(Embodiment 2) FIG. 4 shows a circuit configuration in Embodiment 2. In this embodiment, the current control transistor is a p-channel type. The light emission principle of this drive circuit is basically the same as that of the first embodiment. However, since the p-channel transistor can only discharge to the load, a precharge circuit for charging the load to the power supply voltage in advance is loaded.

【0054】(実施例3)実施例3はソースフォロワの
構成をnチャンネル、pチャンネルのプッシュプル構成
としたものである。回路構成は図5に示す回路と同一で
ある。プッシュプル構成は負荷に対して充電、放電共に
出来るが回路規模が大きくなることと、定常電流が流れ
るので消費電力が比較的大きくなる。
(Embodiment 3) In Embodiment 3, the configuration of the source follower is an n-channel, p-channel push-pull configuration. The circuit configuration is the same as the circuit shown in FIG. In the push-pull configuration, both charging and discharging can be performed with respect to the load, but the power consumption is relatively large because the circuit scale is large and a steady current flows.

【0055】(実施例4)実施例4はバッファの構成を
差動増幅器をもちいて構成したものである。回路構成は
図6に示す回路と同一である。差動増幅器を用いた構成
にした場合は、前述のソースフォロワ構成に比較して回
路構成がやや複雑になるが回路自身にフィードバック作
用があるためにキャンセル出来るオフセット電圧のレベ
ルが高くなる特徴がある。
(Embodiment 4) In Embodiment 4, the buffer is configured using a differential amplifier. The circuit configuration is the same as the circuit shown in FIG. When a configuration using a differential amplifier is used, the circuit configuration is slightly more complicated than the above-described source follower configuration, but the level of the offset voltage that can be canceled is higher because the circuit itself has a feedback action. .

【0056】[0056]

【発明の効果】以上説明したように本発明によれば、発
光素子の輝度をトランジスタのしきい値電圧のばらつき
などに起因するオフセット電圧を補償する回路が内蔵さ
れており、比較的少ないトランジスタ数で良好な画像特
性を得られるアクティブマトリクス型の電流制御型発光
素子の駆動回路を実現できる。
As described above, according to the present invention, a circuit for compensating for the offset voltage caused by the variation of the threshold voltage of the transistor and the like of the luminance of the light emitting element is built in, and the number of transistors is relatively small. Thus, it is possible to realize a drive circuit of an active matrix type current control type light emitting element which can obtain good image characteristics.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例の構成を示す回路図FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

【図2】オフセットキャンセラー付きソースフォロワの
シミュレーション結果を示す図
FIG. 2 is a diagram showing a simulation result of a source follower with an offset canceller;

【図3】図2の結果の拡大図FIG. 3 is an enlarged view of the result of FIG. 2;

【図4】電流制御用トランジスタがpチャンネルタイプ
の場合のオフセットキャンセラー付きソースフォロワの
回路構成を示す図
FIG. 4 is a diagram showing a circuit configuration of a source follower with an offset canceller when a current control transistor is a p-channel type.

【図5】ソースフォロワ回路としてプッシュプル回路の
構成とした場合を示す図
FIG. 5 is a diagram showing a case where a push-pull circuit is configured as a source follower circuit;

【図6】オフセットキャンセラー付き差動増幅回路を示
す図
FIG. 6 is a diagram showing a differential amplifier circuit with an offset canceller.

【図7】従来のアクティブマトリックス型ELディスプ
レイの駆動回路を示す図
FIG. 7 is a diagram showing a driving circuit of a conventional active matrix EL display.

【図8】ポリシリコン薄膜トランジスタのゲート電圧−
ソース電流特性を示す図
FIG. 8 shows a gate voltage of a polysilicon thin film transistor.
Diagram showing source current characteristics

【図9】EL素子の電流−電圧特性を示す図FIG. 9 shows current-voltage characteristics of an EL element.

【図10】従来例による4ビット相当の階調表示のため
のEL駆動回路を示す図
FIG. 10 is a diagram showing an EL drive circuit for gradation display corresponding to 4 bits according to a conventional example.

【図11】オフセットキャンセラー付き差動増幅回路の
シミュレーション結果を示す図
FIG. 11 is a diagram showing a simulation result of a differential amplifier circuit with an offset canceller.

【図12】図11の結果の拡大図FIG. 12 is an enlarged view of the result of FIG. 11;

【符号の説明】[Explanation of symbols]

12 抵抗素子 13 スイッチングトランジスタ 14 コンデンサ 15 有機薄膜EL素子 16 走査線 17 データ線 18 電源電極 19 共通電極 DESCRIPTION OF SYMBOLS 12 Resistance element 13 Switching transistor 14 Capacitor 15 Organic thin film EL element 16 Scanning line 17 Data line 18 Power supply electrode 19 Common electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 岡田 隆史 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5C080 AA06 AA07 BB05 DD05 DD22 DD25 DD28 EE19 EE29 FF11 JJ03 JJ04 JJ05 KK43  ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Takashi Okada 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. (reference) 5C080 AA06 AA07 BB05 DD05 DD22 DD25 DD28 EE19 EE29 FF11 JJ03 JJ04 JJ05 KK43

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】素子に流れる電流に応じて輝度が変化する
発光素子からなる画素を選択するための走査線と、前記
画素を駆動するための電圧を供給するデータ線とが基板
上にマトリクス状に配設され、前記走査線と前記データ
線との交差部に、発光素子の輝度を制御するための電圧
がデータ線より供給されており、前記走査線により与え
られる走査信号により前記データ線の電圧をスイッチン
グする第一の薄膜トランジスタと、前記発光素子にその
出力端子が接続されており、前記スイッチング用の薄膜
トランジスタの出力端子とその入力端子が接続されてい
るバッファ回路と該バッファ回路の入力端子電圧と該バ
ッファ回路の出力端子から出力される電圧の差であるオ
フセット電圧が補償される回路がバッファ回路内部に内
蔵されているアクティブマトリクス型の電流制御型発光
素子の駆動回路。
1. A scanning line for selecting a pixel composed of a light emitting element whose luminance changes according to a current flowing through the element, and a data line for supplying a voltage for driving the pixel are formed in a matrix on a substrate. A voltage for controlling the luminance of the light emitting element is supplied from a data line to an intersection of the scanning line and the data line, and a voltage of the data line is controlled by a scanning signal given by the scanning line. A first thin film transistor for switching a voltage, an output terminal connected to the light emitting element, an output terminal of the switching thin film transistor and an input terminal connected to the buffer circuit, and an input terminal voltage of the buffer circuit. And a circuit for compensating for the offset voltage, which is the difference between the voltage output from the buffer circuit and the output terminal of the buffer circuit. Ibumatorikusu type driving circuit of the current control type light emitting device.
【請求項2】バッファ回路が発光素子の入力端子とソー
スフォロワ接続されている薄膜トランジスタからなり、
ソースフォロワ接続されている電流制御用薄膜トランジ
スタのしきい値電圧のばらつきをキャンセルするための
補償コンデンサ及び該補償コンデンサにしきい値電圧を
記憶させるためのスイッチング回路が前記バッファ回路
に組み込まれている請求項1記載のアクティブマトリク
ス型の電流制御型発光素子の駆動回路。
2. A buffer circuit comprising a thin film transistor connected to an input terminal of a light emitting element by a source follower.
The buffer circuit includes a compensation capacitor for canceling a variation in threshold voltage of the current control thin film transistor connected to the source follower, and a switching circuit for storing the threshold voltage in the compensation capacitor. 2. A drive circuit for an active matrix type current control type light emitting device according to claim 1.
【請求項3】バッファ回路が発光素子の入力端子とソー
スフォロワ接続されているn−チャンネル型の薄膜トラ
ンジスタ及びから構成されており、スイッチング回路に
より補償コンデンサにしきい値電圧が書き込まれる前に
負荷に予め蓄えられている電荷を放電することを特徴と
するアクティブマトリクス型の電流制御型発光素子の駆
動方法。
3. A buffer circuit comprising an n-channel type thin film transistor connected to an input terminal of a light emitting element and a source follower, and a switching circuit preloads a load before a threshold voltage is written to a compensation capacitor. A method for driving an active matrix type current control type light emitting element, characterized by discharging stored electric charge.
【請求項4】バッファ回路が発光素子の入力端子とソー
スフォロワ接続されているp−チャンネル型の薄膜トラ
ンジスタ及びから構成されており、スイッチング回路に
より補償コンデンサにしきい値電圧が書き込まれる前に
負荷を予め電源電圧まで充電するプリチャージすること
を特徴とするアクティブマトリクス型の電流制御型発光
素子の駆動方法。
4. A buffer circuit comprising a p-channel type thin film transistor connected to an input terminal of a light emitting element and a source follower, wherein a load is previously set before a threshold voltage is written to a compensation capacitor by a switching circuit. A method for driving an active-matrix current-controlled light-emitting element, comprising precharging to charge to a power supply voltage.
【請求項5】ソースフォロワ接続されるトランジスタが
nチャンネルトランジスタとpチャンネルトランジスタ
がプッシュプル接続されていることを特徴とする請求項
2記載のアクティブマトリクス型の電流制御型発光素子
の駆動回路。
5. The drive circuit for an active matrix type current control type light emitting device according to claim 2, wherein the source follower-connected transistors are n-channel transistors and p-channel transistors are push-pull connected.
【請求項6】バッファ回路が差動増幅器により構成さ
れ、該差動増幅器の出力オフセットをキャンセルするた
めの補償コンデンサ及び該補償コンデンサにしきい値電
圧を記憶させるためのスイッチング回路が組み込まれて
いる請求項1記載のアクティブマトリクス型の電流制御
型発光素子の駆動回路。
6. A buffer circuit comprising a differential amplifier, a compensation capacitor for canceling an output offset of the differential amplifier, and a switching circuit for storing a threshold voltage in the compensation capacitor. Item 2. A drive circuit for an active matrix type current control type light emitting element according to item 1.
【請求項7】素子に流れる電流に応じて輝度が変化する
発光素子からなる画素を選択するための走査線と、前記
画素を駆動するための電圧を供給するデータ線とが基板
上にマトリクス状に配設され、前記走査線と前記データ
線との交差部に、発光素子の輝度を制御するための電圧
がデータ線より供給されており、前記走査線により与え
られる走査信号により前記データ線の電圧をスイッチン
グする薄膜トランジスタと、前記発光素子にその出力端
子が接続されており、前記スイッチング用の薄膜トラン
ジスタの出力端子とその入力端子が接続されているバッ
ファ回路と該バッファ回路の入力端子電圧と該バッファ
回路の出力端子から出力される電圧の差であるオフセッ
ト電圧が補償される補償回路とを有する電流制御型発光
素子であって、前記補償回路が前記バッファ回路に内蔵
されていることを特徴とする電流制御型発光素子。
7. A scanning line for selecting a pixel formed of a light emitting element whose luminance changes according to a current flowing through the element, and a data line for supplying a voltage for driving the pixel are formed in a matrix on a substrate. A voltage for controlling the luminance of the light emitting element is supplied from a data line to an intersection of the scanning line and the data line, and a voltage of the data line is controlled by a scanning signal given by the scanning line. A thin film transistor for switching a voltage, an output terminal connected to the light emitting element, an output terminal of the thin film transistor for switching and an input terminal connected to the buffer circuit, an input terminal voltage of the buffer circuit, and the buffer A compensation circuit for compensating for an offset voltage which is a difference between voltages output from output terminals of the circuit. Current-controlled light-emitting element characterized in that the compensation circuit is incorporated in the buffer circuit.
JP25438699A 1999-09-08 1999-09-08 Drive circuit and drive method of current control type light emitting element Pending JP2001083924A (en)

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