JP2001083924A - Drive circuit and drive method of current control type light emitting element - Google Patents

Drive circuit and drive method of current control type light emitting element

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Publication number
JP2001083924A
JP2001083924A JP25438699A JP25438699A JP2001083924A JP 2001083924 A JP2001083924 A JP 2001083924A JP 25438699 A JP25438699 A JP 25438699A JP 25438699 A JP25438699 A JP 25438699A JP 2001083924 A JP2001083924 A JP 2001083924A
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voltage
circuit
light emitting
emitting element
buffer circuit
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Japanese (ja)
Inventor
Yutaka Minamino
Takashi Okada
Atsuhiro Yamano
裕 南野
敦浩 山野
隆史 岡田
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Matsushita Electric Ind Co Ltd
松下電器産業株式会社
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Priority to JP25438699A priority Critical patent/JP2001083924A/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0819Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/027Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/04Maintaining the quality of display appearance
    • G09G2320/043Preventing or counteracting the effects of ageing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit for uniformly gradation-controlling an EL that is a current driving element according to an external input signal by containing, in a buffer, a circuit for compensating the offset voltage that is the difference between the input terminal voltage of a buffer element and the voltage outputted from the output terminal of the buffer element. SOLUTION: Since the charging voltage of a load is VIN-Vt when no offset canceller is attached, the dispersion of threshold voltage Vt appears as an output deviation. However, when an offset canceller is attached, the charging voltage of the load is equal to the input voltage VIN and basically never influenced by the dispersion of the threshold voltage Vt. A circuit for compensating the offset voltage resulted from the dispersion of the threshold voltage Vt is built in a transistor for controlling the luminance of a light emitting element. Therefore, this drive circuit for light emitting element capable of providing a satisfactory image characteristic with a relatively small number of transistors can be realized.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、ディスプレイに用いられる発光素子の駆動装置に関し、特に有機及び無機EL(エレクトロルミネンス)、又はLED(発光ダイオード)等のような発光輝度が素子を流れる電流により制御される電流制御型発光素子の駆動回路の構成ならびに駆動方法に関する。 The present invention relates to a current flowing relates to a drive device of a light emitting element used in the display, in particular organic and inorganic EL (electroluminescence), or LED emission luminance, such as (light emitting diode) or the like element construction and method of driving a driving circuit of the current-controlled light-emitting elements controlled by the.

【0002】 [0002]

【従来の技術】有機及び無機EL、又はLED等のような発光素子をアレイ状に組み合わせ、ドットマトリクスにより文字表示を行うディスプレイは、テレビ、携帯端末等に広く利用されている。 Combinations BACKGROUND ART Organic and inorganic EL, or a light emitting element such as an LED or the like in an array, a display for character display by the dot matrix are widely used television, a portable terminal or the like.

【0003】特に、自発光素子を用いたこれらのディスプレイは、液晶を用いたディスプレイと異なり、照明のためのバックライトを必要としない、視野角が広い等の特徴を有し、注目を集めている。 In particular, these displays using self-luminous elements is different from the display using the liquid crystal, does not require a backlight for lighting, characterized in wide viewing angle, etc., it attracted attention there.

【0004】中でも、トランジスタ等とこれらの発光素子とを組み合わせてスタティック駆動を行うアクティブマトリクス型と呼ばれるディスプレイは、ダイナミック駆動を行う単純マトリクス駆動のディスプレイと比較して、高輝度、高コントラスト、高精細等の優位性を持っており近年注目されている。 [0004] Among them, a display called active matrix that performs static driving by combining transistors such as a such a light-emitting element, as compared to the display of simple matrix drive that performs dynamic driving, high luminance, high contrast, high definition has been attracting attention in recent years has the advantage of equal.

【0005】この種のディスプレイの従来例として、図7に、Society for Information Display発行の1997年秋期大会予稿集『Asiadisplay '97』の第216〜219頁(セイコーエプソン)の発表から引用した、発光素子にELを使用したアクティブマトリクス型ディスプレイの発光素子駆動回路を示す。 [0005] As a conventional example of this kind of display, in Figure 7, it was taken from the announcement of the Society for Information Display issuance of the 1997 Fall Convention Proceedings No. 216 to 219 pages of "Asiadisplay '97" (Seiko Epson), a light-emitting a light emitting element driving circuit of an active matrix display using the EL to the element.

【0006】図7を参照して、この駆動回路での発光原理を説明する。 [0006] With reference to FIG. 7, the light emission principle of this driving circuit. スイッチング用トランジスタ71のゲートに接続された走査線72が選択されて活性化されると、トランジスタ71がオン状態となり、トランジスタ71に接続されたデータ線73から信号がコンデンサ7 The scanning line 72 connected to the gate of the switching transistor 71 is selected and activated, the transistor 71 is turned on, the signal from the data line 73 connected to the transistor 71 is capacitor 7
4に書き込まれる。 4 is written to. コンデンサ74は電流制御用トランジスタ75のゲート・ソース間電圧を決定する。 Capacitor 74 determines the gate-source voltage of the current controlling transistor 75.

【0007】そして、走査線72が非選択となりトランジスタ71がオフ状態になると、コンデンサ74の両端間の電圧は次の周期に走査線72が選択されるまで保持される。 [0007] Then, the scanning lines 72 transistor 71 becomes non-selection is turned off, the voltage across the capacitor 74 is held until the scanning line 72 is selected in the next cycle.

【0008】コンデンサ74の両端間の電圧に応じて、 [0008] Depending on the voltage across capacitor 74,
電源電極76→トランジスタ75のドレイン−ソース→ The drain of the power supply electrode 76 → transistor 75 - source →
EL素子77→共通電極78という経路に沿って電流が流れ、この電流によりEL素子77が発光する。 Current flows along the path of the EL element 77 → the common electrode 78, the EL element 77 emits light by the current.

【0009】一般的にコンピュータの端末、パソコンのモニタ、テレビ等の動画表示を行うためには、各画素の輝度が変化する階調表示が出来ることが望ましい。 [0009] Generally, computer terminals, monitors of personal computers, in order to perform a moving image display such as a television, it is desirable that gradation display luminance of each pixel changes is possible.

【0010】図7の駆動回路において階調表示を行うには、トランジスタ75のゲート・ソース電極間に閾値付近の電圧を印加する必要がある。 [0010] To perform gradation display in the driver circuit of FIG. 7, it is necessary to apply a voltage in the vicinity of the threshold between the gate and source electrodes of the transistor 75.

【0011】しかし、トランジスタのゲート電圧・ソース電流特性に、図8に示すようなばらつきがあると、例えば図7のトランジスタ75のゲート電極にゲート電圧VAを印加した場合、トランジスタ75に流れる電流はIA(実線で示す曲線とVAとの交点)とIB(破線で示す曲線とVAとの交点)のように異なるため、EL素子77に流れる電流も変わり、本来ならば同じ輝度であるはずの領域の輝度が異なり、このため、例えば輝度むら等の画質劣化が生じることになる。 [0011] However, the gate voltage and the source current characteristics of the transistor, when there is a variation as shown in FIG. 8, for example when applying the gate voltage VA to the gate electrode of the transistor 75 in FIG. 7, the current flowing through the transistor 75 IA for different as the (point of intersection of the curve and the VA shown by the solid line) IB of (the intersection of the curve and the VA shown in dashed lines), also vary the current flowing through the EL element 77, the area that should be the same brightness would otherwise different brightness, Thus, for example, so that the deterioration of image quality such as brightness unevenness.

【0012】ポリシリコンを材料とした薄膜トランジスタにおいては、結晶シリコンによるトランジスタに比較して、一般的にこのしきい値のばらつきが大きく、その値は±0.1V程度と推察される。 [0012] In thin film transistor polysilicon material, as compared to the transistor by the crystalline silicon, generally the variation of the threshold is large, its value is estimated to approximately ± 0.1 V.

【0013】しきい値が±0.1Vばらついたとすれば、トランジスタ75を流れる電流は、しきい値が2V [0013] If the threshold is varied ± 0.1V, the current flowing through the transistor 75, the threshold is 2V
程度ならばリニア領域で動作させた場合は5%程度、飽和領域で動作させた場合は10%程度電流値が変動する。 If the extent of about 5% when operating in the linear region, the current value of about 10% when operating in the saturation region varies. 図9はEL素子の電流−輝度特性である。 Figure 9 is a current of the EL elements - a luminance characteristic. 電流−輝度特性は階調表示させる領域Aにおいてはリニアな特性であるので、前期電流値のばらつきは、そのまま輝度特性のばらつきとなって現れる。 Current - the brightness characteristic is a linear characteristic in the area A for gradation display, the variation of the previous period current value appears as a variation in luminance characteristics.

【0014】この問題を解決するため、特開平2−14 [0014] In order to solve this problem, JP-A-2-14
8687号公報には、素子の閾値付近でのばらつきがあっても、この影響を受けずに階調表示を行うELディスプレイ装置が提案されている。 The 8687 JP, even if there are variations in the vicinity of the threshold of the device, EL display device has been proposed to perform gradation display without affected.

【0015】図10を参照して、特開平2−14868 [0015] Referring to FIG. 10, JP-A-2-14868
7号公報に提案される回路を説明する。 The circuit proposed in 7 JP be described. 図10は、図7 Figure 10, as shown in FIG. 7
の点線内の電流制御回路79に対応する回路部を示しており、16階調表示を行う場合についての例を示すものである。 It shows a circuit portion corresponding to the current control circuit 79 within the dotted line of, illustrates an example of a case of performing 16 gradation display. 階調制御を行うためにデータ線の本数は4本に増加している。 Number of data lines in order to perform gradation control is increased to four.

【0016】図10において、94〜97は発光素子駆動用のトランジスタ、98はカレントミラー回路、99 [0016] In FIG. 10, 94-97 the transistor for driving the light emitting element, 98 is a current mirror circuit, 99
は発光素子、100はトランジスタの各ソース端子及び発光素子が接続された共通電極の抵抗成分である。 The light emitting element 100 is a resistance component of the common electrodes each source terminal and the light emitting element of the transistors are connected. トランジスタ94〜97のドレイン電極は共通接続されてカレントミラー回路98の入力端に接続されている。 The drain electrode of the transistor 94 to 97 are connected in common to the input terminal of the current mirror circuit 98.

【0017】図10において、4ビット入力より階調に対応した組み合わせの信号電圧がトランジスタ94〜9 [0017] In FIG. 10, the signal voltage of the combination corresponding to the grayscale than 4 bits input transistor 94-9
7のゲート電圧として印加される。 It is applied as a 7 gate voltage. そして、トランジスタ94〜97のうちオン状態のトランジスタに流れる電流の合計値と同一の電流値がカレントミラー回路98の出力端から発光素子99に供給され、その電流値に応じて発光素子99が発光する。 Then, the same current value and the total value of the current flowing through the transistor in the on state of the transistor 94 to 97 is supplied to the light emitting element 99 from the output terminal of the current mirror circuit 98, the light emitting element 99 is emitting light according to the current value to.

【0018】例えばトランジスタ94〜97がオン時の電流値の対数をとった値をそれぞれ倍になるようにすれば(即ち、I2はI1の2倍、I3はI2の2倍(=I [0018] For example, if transistors 94 to 97 is a value obtained by taking the logarithm of the current value during the on state so that each doubled (i.e., I2 is twice the I1, I3 twice the I2 (= I
1の22倍)、I4はI3の2倍(=I1の23倍)とすれば)、トランジスタ94〜97のオンする組み合わせにより16階調の表示を行うことができる。 Times 1 22), I4 is if twice the I3 (23 times = I1)), can be displayed 16 gradations by a combination of ON of the transistor 94-97. なお、I1 It should be noted, I1
〜I4はトランジスタ94〜97がオン状態時のソース電流をそれぞれ表している。 ~I4 transistors 94-97 represents the source current during the on-state, respectively.

【0019】このときトランジスタを図8のゲート電圧VBに対応する電流が飽和した領域の電圧で使用するようにすれば、トランジスタの閾値付近での特性がばらついていても、その影響を受けるがことなく、輝度のばらつきも生じない。 [0019] If to be used in a voltage region where the current is saturated, corresponding this time, the transistor gate voltage VB of FIG. 8, even if variations in characteristics in the vicinity of the threshold of the transistor, affected it without does not occur variations in luminance. しかしながら階調数が増えた場合カレントミラー回路が増加すると共に、ビットにおおじて信号線の数が増加し駆動回路が複雑となる。 However with the current mirror circuit increases when the gradation number is increased, the number increases and the drive circuit of the signal line uncle your bits becomes complicated.

【0020】 [0020]

【発明が解決しようとする課題】上述のように、アクティブマトリックス型のEL発光装置においては、これまでは階調表示を実現させるために、カレントミラー回路あるいは低電流回路及び電流制御用トランジスタなどを1画素内に設ける必要がある。 As described above [0006] In the EL light-emitting device of the active matrix type, in order Previously to realize gray scale display, and a current mirror circuit or a low-current circuit and the current control transistor it is necessary to provide in one pixel. 生産等を考慮した場合、 If you take into account the production, etc.,
複数個のトランジスタを画素内に設けることは、トランジスタの不良確率の増加による歩留まりの低下が予想され、高い歩留まりを確保するためには1画素内に少ないトランジスタで階調表示させる、望ましくは必要最小限のトランジスタ数で階調表示を実現させることが必要である。 Providing a plurality of transistors in a pixel can be expected reduction in yield due to an increase in the failure probability of the transistors, in order to ensure a high yield to gradation display with less transistors in one pixel, preferably the minimum required it is necessary to realize a gradation display by the number of transistors of the limit. 加えてトランジスタ数の増加に伴いEL素子の発光に関わる有効な部分の面積が減少する。 In addition the area of ​​the effective portion relating to light emission of the EL element with the increase in the number of transistors is reduced. このような問題を解決するためには図7の駆動回路において電流駆動用のTFTのしきい値電圧のばらつきを補正することが可能なシンプルな回路構成の提案が必要である。 In order to solve such a problem, it is necessary to propose a possible simple circuit configuration to correct the variation in the threshold voltage of the TFT for current driving in the driving circuit of FIG.

【0021】 [0021]

【課題を解決するための手段】本発明は前述の電流駆動素子であるELを外部からの入力信号のレベルに応じてムラなく階調制御するための駆動回路を提案するものである。 The present invention SUMMARY OF] is to propose a drive circuit for evenly gradation control in accordance with the level of the input signal from outside the EL is above the current driving element. 具体的な回路構成は以下の通りである。 Specific circuit configuration is as follows.

【0022】素子に流れる電流に応じて輝度が変化する発光素子からなる画素を選択するための走査線と、前記画素を駆動するための電圧を供給するデータ線とが基板上にマトリクス状に配設され、前記走査線と前記データ線との交差部に、発光素子の輝度を制御するための電圧がデータ線より供給されており、前記走査線により与えられる走査信号により前記データ線の電圧をスイッチングする第一の薄膜トランジスタと、前記発光素子にその出力端子が接続され、前記スイッチング用の薄膜トランジスタの出力端子とその入力端子が接続されているバッファ素子と該バッファ素子の入力端子電圧と該バッファ素子の出力端子から出力される電圧の差であるオフセット電圧が補償される回路がバッファ内部に内蔵されているアクティブマト The scanning lines for selecting pixels to a light emitting element which changes its luminance according to a current flowing through the element, distribution in a matrix into a data line for supplying a voltage for driving the pixels on the substrate is set, the intersections of the scanning lines and the data lines, and a voltage for controlling the brightness of the light emitting element is supplied from the data line, a voltage of the data line by the scanning signal supplied by the scanning lines a first thin film transistor for switching said output terminal to the light emitting element is connected, the input terminal voltage and the buffer elements of the output terminal and the buffer element and the buffer element having an input terminal connected to the thin film transistor for the switching active matrix the circuit offset voltage is a difference between the voltage output from the output terminal is compensated is incorporated in the buffer クス型の電流制御型発光素子の駆動回路を提案するものである。 It proposes a driving circuit of the box-type current-controlled light-emitting elements.

【0023】一般的には前記バッファ素子が前記発光素子とソースフォロワ接続されており、ソースフォロワの用いられる電流制御用薄膜トランジスタのしきい値電圧のばらつきをキャンセルするための補償コンデンサ及び該補償コンデンサにしきい値電圧を記憶させるためのスイッチング回路が組み込まれている構成がシンプルな構成であると思われる。 [0023] In general, the buffer elements are light emitting element and the source-follower connection, the compensation capacitor and the compensation capacitor for canceling the variation in the threshold voltage of the current control thin film transistor used the source follower configuration in which the switching circuit for storing the threshold voltage is incorporated appears to be simple configuration.

【0024】この構成では3種類の基本的構成が提案できる。 [0024] In this configuration can be proposed is the basic configuration of the three types.

【0025】(1−1)前記バッファ回路が前記発光素子の入力端子とソースフォロワ接続されているn−チャンネル型の薄膜トランジスタ及びから構成される場合、 [0025] (1-1) if the buffer circuit is constituted thin film transistor and a input terminal and a source-follower the connected n- channel type of the light emitting element,
(1−2)前記バッファ回路が前記発光素子の入力端子とソースフォロワ接続されているp−チャンネル型の薄膜トランジスタ及びから構成される場合、(1−3)前記ソースフォロワがnチャンネルトランジスタとpチャンネルトランジスタがプッシュプル接続された構成である場合、である。 (1-2) if the buffer circuit is constituted thin film transistor and a input terminal and a source-follower the connected p- channel type of the light emitting element, (1-3) the source follower n-channel transistor and p-channel If the transistor is a push-pull connected to each other, it is. バッファ回路としてソースフォロワ構成以外の提案として、「前記バッファ素子が差動増幅器により構成され、該差動増幅器の出力オフセットをキャンセルするための補償コンデンサ及び該補償コンデンサにしきい値電圧を記憶させるためのスイッチング回路が組み込まれている回路」があげられる。 As a proposal other than the source-follower configuration as the buffer circuit, "the buffer element is made up of a differential amplifier, for storing the threshold voltage compensation capacitor and the compensation capacitor for canceling the output offset of the differential amplifier circuit "in which the switching circuit is incorporated, and the like.

【0026】以上の回路構成を提案するものである。 [0026] is intended to propose a circuit configuration of the above.

【0027】上記それぞれの構成における各ノードに印加するタイミングチャートとこれに伴う各トランジスタの動作を説明する。 [0027] To explain the operation of the transistors associated therewith a timing chart to be applied to each node in the above respective configurations.

【0028】まずソースフォロワーの動作を説明する。 [0028] First, explaining the operation of the source follower.
ここでは電流制御用のトランジスタがnチャンネル型の場合を説明する。 Here transistor for current control will be described the case of n-channel type.

【0029】(1)入力電圧Vinがゲート電圧に印可されると、トランジスタがONし、最初は大きなドレイン電流が流れて負荷を充電するが、負荷の電圧が上昇するとトランジスタのソース電圧が上昇し、ゲート−ソース間電圧が徐々に小さくなるのでドレイン電流が小さくなり、ゲート−ソース間電圧がしきい値電圧Vtになるまで負荷が充電されるとトランジスタはOFFし充電はストップする。 [0029] (1) When the input voltage Vin is applied to the gate voltage, the transistor is turned ON, first, but charges the load is large drain current flows, the voltage of the load increases the source voltage of the transistor rises the gate - drain current is reduced source voltage gradually decreases, the gate - when the load to the source voltage becomes a threshold voltage Vt is charged transistor is OFF charging stops.

【0030】(2)ソースフォロワのゲートに入力電圧Vinを印可した場合、負荷はVin−Vtまで充電されることになりしきい値電圧Vtがばらつくと出力電圧はそのまま出力偏差となって現れる。 [0030] (2) When applying an input voltage Vin to the gate of the source follower, the load and the output voltage threshold voltage Vt will be charged to Vin-Vt varies appears as it is as the output deviation.

【0031】現状のポリシリコンではしきい値電圧のばらつきは±0.5V程度の範囲であるためにこのままではしきい値電圧のばらつきが輝度のばらつきとなって現れる。 [0031] The variation in threshold voltage in the state of the polysilicon appear variation in the threshold voltage becomes a variation in luminance remains this to be a range of about ± 0.5V. 次にオフセットキャンセラー付きのソースフォロワの動作を図1を用いて説明する。 Will now be described with reference to FIG. 1 the operation of the source follower with the offset canceller. 動作は大きく3ステップに分けられる。 Operation is roughly divided into three steps.

【0032】<第一ステップ>スイッチS1,S2,S [0032] <First Step> switches S1, S2, S
3がオンしゲートにはしきい値検出用電圧Vofがゲートに印可され、ソースはグランドに設置されるのでソースフォロワのトランジスタはオンする。 3 is a threshold detection voltage Vof is applied to the gate is turned on by the gate, the source is turned on transistor of the source follower because it is installed in the ground. 同時にスイッチS5をオンすることによって、負荷の電荷を放電させる。 By turning on the switch S5 simultaneously discharges the electric charge of the load. 負荷をリセットする理由はNchソースフォロワの場合負荷を充電することは出来るが、負荷に蓄えられている電荷を放電できないためである。 The reason for resetting the load although it is possible to charge the case where the load of the Nch source follower is can not be discharged the charge stored in the load.

【0033】<第二ステップ>スイッチS3をオフする事によりトランジスタを流れる電流をゼロにする。 [0033] The current through transistor by turning off the <Second step> switch S3 to zero. これによりトランジスタのソース電圧はゲート−ソース間電圧がしきい値電圧Vtに等しくなるまで上昇する。 Thus the source voltage of the transistor gate - rises to the source voltage becomes equal to the threshold voltage Vt. その結果しきい値検出用容量にはしきい値に等しい値が保持される。 The resulting threshold detection capacitance value equal to the threshold are retained.

【0034】<第三ステップ>スイッチS1、S2がオフされスイッチS0がオンされることによりトランジスタのゲートにはしきい値検出用容量を通して入力電圧V [0034] <Third step> input through threshold detection capacitance to the gate of the transistor by switches S1, S2 switch S0 is turned off is the on-voltage V
in+しきい値電圧Vtが印可される。 in + threshold voltage Vt is applied. 従ってトランジスタのソース電圧は、ゲート電圧からしきい値電圧を引いた値であるVinとなりスイッチS5をオフしてスイッチS4をオンする事により負荷はVinの電圧まで充電されることになる。 Thus the source voltage of the transistor, a load by which to turn off the Vin next switch S5 is a value obtained by subtracting the threshold voltage from the gate voltage to turn on the switch S4 will be charged to a voltage of Vin.

【0035】以上の動作により、オフセットキャンセラーを付けない場合は、負荷の充電電圧はVin−Vtであるので、しきい値電圧Vtがばらつくと出力偏差となって現れるが、オフセットキャンセラーを付けると、負荷の充電電圧は入力電圧Vinと等しくなり、基本的にしきい値電圧Vtのばらつきの影響を受けない。 [0035] With the above operation, if without the offset canceller, the charging voltage of the load is the Vin-Vt, but appears as the output deviation threshold voltage Vt varies, and put the offset canceller, charging voltage of the load becomes equal to the input voltage Vin, it is not affected by variations in basically the threshold voltage Vt.

【0036】図2はオフセットキャンセラー付きソースフォロワのシミュレーション結果である。 [0036] FIG. 2 is a simulation result of the offset canceller with a source follower. シミュレーション条件は (1)しきい値電圧ばらつきは±0.5Vを想定 (2)しきい値検出用容量は0.5pF、しきい値検出用電圧Vof=7.5V (3)入力電圧=8.0V (4)1水平時間=30μsec である。 Simulation conditions (1) the threshold voltage variation assumed ± 0.5V (2) threshold detection capacitance is 0.5 pF, the threshold detection voltage Vof = 7.5V (3) Input Voltage = 8 .0V (4) 1 horizontal time = a 30 .mu.sec.

【0037】第一ステップでは、ソースフォロワのトランジスタがオンされるが、スイッチS3のオン抵抗のため出力電圧(ソース電圧)は完全にゼロにならない。 [0037] In a first step, the transistor of the source follower is turned on, the output voltage (source voltage) for the on-resistance of the switch S3 is not completely zero. 第二ステップでは、しきい値ばらつきの影響により、出力電圧がばらついていることが解る。 In a second step, it can be seen that due to the influence of the threshold voltage variation, and variations in the output voltage. しきい値検出用電圧Vofと出力電圧の差がしきい値電圧Vtに等しく、この値がしきい値検出用容量に記憶される。 Equal the difference between the threshold detection voltage Vof and the output voltage is the threshold voltage Vt, and this value is stored in the capacitor detection threshold. 第三ステップでは入力電圧Vinにしきい値電圧Vtを加えた値がゲートに印可されるので、出力電圧はしきい値電圧に関係なく、ほぼ入力電圧Vinに等しくなっている。 Since the third step the value obtained by adding the threshold voltage Vt to the input voltage Vin is applied to the gate, the output voltage regardless of the threshold voltage is equal to approximately the input voltage Vin. オフセットキャンセル能力は図3の下の図に示す拡大図より、 Offset canceling capacity than enlarged view shown in the lower diagram of Figure 3,
しきい値ばらつき0.5Vに対して、出力偏差は±10 Against a threshold variation 0.5V, the output deviation ± 10
mVまで抑制することが可能である。 It is possible to suppress up to mV.

【0038】以上は電流制御用トランジスタがnチャンネルの場合であるが、トランジスタがpチャンネルタイプの場合も想定される。 The above is a case where the current control transistor is an n-channel, transistors are also contemplated for p-channel type.

【0039】本回路構成を図4に示す。 [0039] The present circuit arrangement shown in FIG. pチャンネルトランジスタはnチャンネルトランジスタに比較して電流駆動能力は劣るが、トランジスタ信頼性の面ではnチャンネルトランジスタよりも安定である。 p-channel transistor is inferior current driving capability as compared to the n-channel transistor, but in terms of transistor reliability is more stable than n-channel transistors. 基本的にはpチャンネルタイプの場合も同様なオフセットキャンセル動作は可能であるが、pチャンネルソースフォロワは負荷に対して放電しかできないので負荷を予め電源電圧まで充電するプリチャージ回路が必要である。 It is basically possible also similar offset cancel operation when a p-channel type, p-channel source follower requires a precharge circuit for charging in advance to the supply voltage the load can not only discharge to the load.

【0040】そのほかにn−チャンネルとp−チャンネルをプッシュプル接続した回路が提案できる。 [0040] In addition to the push n- channel and p- channel pull the connected circuit can be proposed. プッシュプルは負荷に対して充電、放電共に出来るのでチャージング回路は必要ない。 Pull the charging circuit is not required charge, the discharge together can the load. プッシュプル回路を用いた場合の構成を図5に示す。 The configuration in the case of using the push-pull circuit shown in FIG.

【0041】次にバッファ構成として、差動増幅回路を用いることは可能である。 [0041] As next buffer configuration, it is possible to use a differential amplifier circuit. 差動増幅回路はソースフォロワ回路に比較して負帰還がかかるので、しきい値電圧ばらつきに起因するオフセットを含めたすべてのオフセットの原因如何に関わらずVinとVoutの差を検出する事が出来る。 Since the differential amplifier circuit takes negative feedback compared to the source follower circuit, it is possible to detect the difference between Vin and Vout regardless of the cause whether all offsets including an offset due to the threshold voltage variation .

【0042】オフセットキャンセラー付き差動増幅回路の動作を図6を使って説明する。 [0042] To explain the operation of the offset canceller with a differential amplifier circuit with Figure 6.

【0043】<第一ステップ>2個のスイッチAがオンし差動増幅器の反転入力端子と非反転入力端子間に検出用容量が接続されたバッファ回路となる。 [0043] a <First Step> two switches A is turned on buffer circuit inverting input terminal and the detection capacitance between the non-inverting input terminal is connected to a differential amplifier. 差動増幅器の非反転入力端子に入力電圧Vinが印可され、出力電圧がVout=Vin+ΔVとなっているとする。 Input voltage Vin to the non-inverting input terminal of the differential amplifier is applied, the output voltage is that a Vout = Vin + [Delta] V. バッファ回路を構成しているので、反転入力端子の電圧もVi Since constitute a buffer circuit, the voltage at the inverting input terminal also Vi
n+ΔVになる。 Become n + ΔV. 従って検出用容量には非反転入力端子の入力電圧Vinと、反転入力端子の出力電圧Vin+ Therefore, the detection capacitance and the input voltage Vin of the non-inverting input terminal, an output voltage of the inverting input terminal Vin +
ΔVの差であるΔVが検出され保持される。 Is the difference [Delta] V [Delta] V is detected is maintained.

【0044】<第二ステップ>スイッチAがOFFされスイッチBがONされるので、出力電圧は検出用容量を通して反転入力端子にフィードバックされる。 [0044] Since <Second step> switch A is turned OFF switch B is turned ON, the output voltage is fed back to the inverting input terminal through a detection capacitance. 非反転入力端子には第一ステップ同様入力電圧Vinが印可されているので差動増幅器の内部回路は同じ状態を保つために反転入力端子の電圧はVin+ΔVにならなければならない。 Voltage of the non-inverted input terminal inverting input terminal to the internal circuits of the differential amplifier because the first step similar input voltages Vin is applied to maintain the same state must become Vin + [Delta] V. 出力端子と反転入力端子間には、ΔVの電位差を持った検出用容量が接続されているので、反転入力端子の電圧がVin+ΔVになるためには、出力電圧はV Between inverting input terminal and output terminal, the detection capacitor having a potential difference [Delta] V is connected, to a voltage of the inverting input terminal becomes Vin + [Delta] V, the output voltage V
out=Vinにならなければならない。 It must become out = Vin.

【0045】以上の動作により差動増幅回路にオフセットキャンセラーを付けることで、様々な要因で発生する出力偏差ΔVを抑制する事が出来る。 [0045] By applying an offset canceller to the differential amplifier circuit the above operation, it is possible to suppress the output deviation ΔV generated by various factors. 出力電圧は常に入力電圧Vinに等しい。 The output voltage is always equal to the input voltage Vin.

【0046】図11はオフセットキャンセラー付きオペアンプのシミュレーション結果である。 [0046] FIG. 11 is a simulation result of the offset canceller with an operational amplifier. シミュレーション条件としては (1)差動増幅回路のバッファ部はプッシュプル型 (2)出力偏差検出用容量=1.0pF (3)入力電圧=7.0V (4)負荷抵抗=1.0kΩ、負荷容量=20pF (5)1水平時間=30μsec を仮定し、しきい値ばらつきが±0.5Vの結果を図1 The simulation condition (1) buffer of the differential amplifier circuit is push-pull (2) output deviation detection capacitance = 1.0 pF (3) Input Voltage = 7.0 V (4) load resistance = 1.0kΩ, load volume = 20 pF (5) 1 horizontal time = assuming 30 .mu.sec, Figure 1 the results of the threshold variation ± 0.5V
2に示す。 2 shows.

【0047】第一ステップでは、しきい値ばらつきにより、入力電圧に対して出力電圧が大きくばらついているが、この差を出力偏差検出用容量で検出し補正することにより、第二ステップではしきい値ばらつきに影響されることなく、出力電圧は入力電圧にほぼ等しくなっている。 [0047] In the first step, the threshold voltage variation, the output voltage is greatly varied with respect to the input voltage, by detecting and correcting the difference in output deviation detection capacitance, threshold in the second step without being affected by the value variation, the output voltage is substantially equal to the input voltage. オフセットキャンセル能力は図12の下の拡大図より、しきい値ばらつき±0.5Vに対して、出力偏差± Than enlarged view of the lower offset cancellation capability 12, against a threshold variation ± 0.5V, the output deviation ±
5mVまで抑制できることが出来る。 It can be suppressed to 5mV.

【0048】 [0048]

【発明の実施の形態】図面を参照して、本発明の実施例を以下に説明する。 With reference to the DETAILED DESCRIPTION OF THE INVENTION drawings, an embodiment of the present invention are described below.

【0049】(実施例1)図1は本発明の第1の実施例の回路図であり、発光素子として電荷注入型の有機薄膜EL素子(以下「有機薄膜EL素子」と略記する)を用いた場合のものである。 [0049] (Embodiment 1) FIG. 1 is a circuit diagram of a first embodiment of the present invention, use a charge injection type organic thin film EL element (hereinafter abbreviated as "organic thin film EL element") as a light-emitting element it is one where you were.

【0050】図1において、15は発光素子である有機薄膜EL素子、12は有機薄膜EL素子15に流れる電流を制御する抵抗素子、14は有機EL素子に電流を流し続けるコンデンサ、13はコンデンサ14に信号電圧を供給するスイッチングトランジスタ、16はスイッチングトランジスタ13を選択する走査信号を供給する走査線、17は走査線16がオンとされ選択されたスイッチングトランジスタ13を介してコンデンサ14に電荷を供給するデータ線、18は有機薄膜EL素子14に電流を供給する電源電極、19はデータ線17との間の電位差でトランジスタの動作点を決定する共通電極である。 [0050] In FIG. 1, 15 is an organic thin film EL element is a light emitting element, 12 is the resistance element for controlling a current flowing through the organic thin film EL element 15, 14 continues to flow a current to the organic EL element capacitor, 13 a capacitor 14 switching transistor for supplying a signal voltage to, 16 scanning lines for supplying scanning signals for selecting the switching transistors 13, 17 supplies a charge to the capacitor 14 through the switching transistor 13 in which the scanning line 16 is turned on is selected data line, 18 is a power supply electrode for supplying current to the organic thin film EL element 14, 19 is a common electrode for determining the operating point of the potential difference transistor between the data line 17.

【0051】上述の駆動回路のよる発光原理は先に述べた通りである。 The principle of light emission by the above-described driving circuit is as previously described.

【0052】ポリシリコンは気相成長法によりアモルファスシリコンを堆積しレーザーアニールする事で溶融再結晶化しポリシリコンとなる。 [0052] polysilicon becomes polysilicon melt recrystallization by laser annealing depositing amorphous silicon by vapor deposition. 前記ポリシリコン中にイオンドーピング法によりリンイオンを打ち込みトランジスタのソース及びドレイン電極部を作成する。 To create the source and drain electrodes of the transistor implanted phosphorus ions by an ion doping method in the polysilicon. 抵抗素子12は前記トランジスタのソース及びドレイン領域となる部分と同一のプロセスで作成されている。 Resistive element 12 is created by the source and the drain region portion of the same process of the transistor. 本実施例1 Embodiment 1
では電流制御用トランジスタをnチャンネル型としている。 In it has a current controlling transistor and the n-channel type. 従ってスイッチング回路として負荷を放電させることが出来ないので負荷の電荷をリセットさせる回路を設けた。 Thus providing the circuit for resetting the charge of the load it is not possible to discharge the load as a switching circuit.

【0053】(実施例2)実施例2における回路構成を図4に示す。 [0053] The circuit configuration in (Example 2) Example 2 shown in FIG. 本実施例は電流制御トランジスタをpチャンネルタイプとしたものである。 This embodiment is obtained by the current control transistor and the p-channel type. この駆動回路の発光原理は基本的に実施例1と同様であるが、pチャンネルトラジスタは負荷に対して放電しかできないので、負荷を予め電源電圧まで充電するプリチャージ回路を負荷した。 Although emission principle of this driving circuit is basically the same as in Example 1 because p-channel Toraji Star can only discharge the load, it was loaded with a precharge circuit for charging in advance to supply a voltage to the load.

【0054】(実施例3)実施例3はソースフォロワの構成をnチャンネル、pチャンネルのプッシュプル構成としたものである。 [0054] (Example 3) Example 3 is obtained by the configuration of the source follower n-channel, a push-pull configuration of a p-channel. 回路構成は図5に示す回路と同一である。 Circuit configuration is the same as the circuit shown in FIG. プッシュプル構成は負荷に対して充電、放電共に出来るが回路規模が大きくなることと、定常電流が流れるので消費電力が比較的大きくなる。 Charge the push-pull configuration load, discharge and that it increases the circuit scale can both power consumption is relatively large because the steady current flows.

【0055】(実施例4)実施例4はバッファの構成を差動増幅器をもちいて構成したものである。 [0055] (Example 4) Example 4 is constructed by using a differential amplifier configuration of the buffer. 回路構成は図6に示す回路と同一である。 Circuit configuration is the same as the circuit shown in FIG. 差動増幅器を用いた構成にした場合は、前述のソースフォロワ構成に比較して回路構成がやや複雑になるが回路自身にフィードバック作用があるためにキャンセル出来るオフセット電圧のレベルが高くなる特徴がある。 If a configuration using a differential amplifier, has the characteristic that although the circuit configuration as compared to the source follower configuration described above is rather complex increases the level of the offset voltage can be canceled due to the feedback effect on circuit itself .

【0056】 [0056]

【発明の効果】以上説明したように本発明によれば、発光素子の輝度をトランジスタのしきい値電圧のばらつきなどに起因するオフセット電圧を補償する回路が内蔵されており、比較的少ないトランジスタ数で良好な画像特性を得られるアクティブマトリクス型の電流制御型発光素子の駆動回路を実現できる。 According to the present invention as described in the foregoing, a circuit for compensating for an offset voltage caused by the luminance of the light emitting element such as a variation in the threshold voltage of the transistor and is built in a relatively small number of transistors in can be realized driving circuit of an active matrix type of the current control type light emitting element obtained a good image characteristics.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の第1の実施例の構成を示す回路図 Circuit diagram showing a configuration of a first embodiment of the present invention; FIG

【図2】オフセットキャンセラー付きソースフォロワのシミュレーション結果を示す図 FIG. 2 is a diagram showing the simulation result of the offset canceller with a source follower

【図3】図2の結果の拡大図 Enlarged view of the results of FIG. 3] FIG. 2

【図4】電流制御用トランジスタがpチャンネルタイプの場合のオフセットキャンセラー付きソースフォロワの回路構成を示す図 Figure 4 shows a current control transistor showing a circuit configuration of an offset canceller with source follower when the p-channel type

【図5】ソースフォロワ回路としてプッシュプル回路の構成とした場合を示す図 FIG. 5 shows a case of the configuration of a push-pull circuit as a source follower circuit

【図6】オフセットキャンセラー付き差動増幅回路を示す図 6 shows an offset canceller with a differential amplifier circuit

【図7】従来のアクティブマトリックス型ELディスプレイの駆動回路を示す図 7 is a diagram showing a driving circuit of a conventional active matrix type EL display

【図8】ポリシリコン薄膜トランジスタのゲート電圧− [8] the gate voltage of the polysilicon thin film transistors -
ソース電流特性を示す図 It shows the source current characteristics

【図9】EL素子の電流−電圧特性を示す図 [9] the current of the EL element - shows voltage characteristics

【図10】従来例による4ビット相当の階調表示のためのEL駆動回路を示す図 Shows the EL driving circuit for FIG. 10 prior art example according to 4-bit equivalent gradation display

【図11】オフセットキャンセラー付き差動増幅回路のシミュレーション結果を示す図 11 is a diagram showing a simulation result of an offset canceller with a differential amplifier circuit

【図12】図11の結果の拡大図 Enlarged view of the results of [12] 11

【符号の説明】 DESCRIPTION OF SYMBOLS

12 抵抗素子 13 スイッチングトランジスタ 14 コンデンサ 15 有機薄膜EL素子 16 走査線 17 データ線 18 電源電極 19 共通電極 12 resistive element 13 the switching transistor 14 capacitor 15 organic thin film EL element 16 scan lines 17 data lines 18 supply electrode 19 common electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 岡田 隆史 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5C080 AA06 AA07 BB05 DD05 DD22 DD25 DD28 EE19 EE29 FF11 JJ03 JJ04 JJ05 KK43 ────────────────────────────────────────────────── ─── front page of the continuation (72) inventor Takashi Okada Osaka Prefecture Kadoma Oaza Kadoma 1006 address Matsushita Electric industrial Co., Ltd. in the F-term (reference) 5C080 AA06 AA07 BB05 DD05 DD22 DD25 DD28 EE19 EE29 FF11 JJ03 JJ04 JJ05 KK43

Claims (7)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】素子に流れる電流に応じて輝度が変化する発光素子からなる画素を選択するための走査線と、前記画素を駆動するための電圧を供給するデータ線とが基板上にマトリクス状に配設され、前記走査線と前記データ線との交差部に、発光素子の輝度を制御するための電圧がデータ線より供給されており、前記走査線により与えられる走査信号により前記データ線の電圧をスイッチングする第一の薄膜トランジスタと、前記発光素子にその出力端子が接続されており、前記スイッチング用の薄膜トランジスタの出力端子とその入力端子が接続されているバッファ回路と該バッファ回路の入力端子電圧と該バッファ回路の出力端子から出力される電圧の差であるオフセット電圧が補償される回路がバッファ回路内部に内蔵されているアク 1. A scanning lines for selecting pixels to a light emitting element which changes its luminance according to a current flowing through the device, and a data line for supplying a voltage for driving the pixel matrix on the substrate to be disposed, the intersections of the scanning lines and the data lines, the voltage for controlling the brightness of the light emitting element is supplied from the data lines, the data lines by the scanning signal supplied by the scanning lines a first thin film transistor for switching a voltage, said has its output terminal to the light emitting element is connected, the input terminal voltage of the buffer circuit and the buffer circuit output terminal of the thin film transistor for the switching and its input terminal is connected Accession offset voltage is a difference between the voltage output from the output terminal of the buffer circuit circuit to be compensated is incorporated in the buffer circuit and ィブマトリクス型の電流制御型発光素子の駆動回路。 Ibumatorikusu type driving circuit of the current control type light emitting device.
  2. 【請求項2】バッファ回路が発光素子の入力端子とソースフォロワ接続されている薄膜トランジスタからなり、 2. A consists TFT buffer circuit is an input terminal and a source-follower-connected light-emitting element,
    ソースフォロワ接続されている電流制御用薄膜トランジスタのしきい値電圧のばらつきをキャンセルするための補償コンデンサ及び該補償コンデンサにしきい値電圧を記憶させるためのスイッチング回路が前記バッファ回路に組み込まれている請求項1記載のアクティブマトリクス型の電流制御型発光素子の駆動回路。 Claim switching circuit for storing the threshold voltage compensation capacitor and the compensation capacitor for canceling the variation in the threshold voltage of the current control thin film transistor is a source follower connection is incorporated in the buffer circuit active matrix driving circuit of the current control type light emitting device of 1, wherein.
  3. 【請求項3】バッファ回路が発光素子の入力端子とソースフォロワ接続されているn−チャンネル型の薄膜トランジスタ及びから構成されており、スイッチング回路により補償コンデンサにしきい値電圧が書き込まれる前に負荷に予め蓄えられている電荷を放電することを特徴とするアクティブマトリクス型の電流制御型発光素子の駆動方法。 Wherein and the buffer circuit is composed of a thin film transistor and the input terminal of the source follower the connected n- channel type light emitting device, in advance in the load before the threshold voltage compensation capacitor by the switching circuit is written the driving method of an active matrix type of the current control type light emitting device characterized by discharging the stored its dependent charge.
  4. 【請求項4】バッファ回路が発光素子の入力端子とソースフォロワ接続されているp−チャンネル型の薄膜トランジスタ及びから構成されており、スイッチング回路により補償コンデンサにしきい値電圧が書き込まれる前に負荷を予め電源電圧まで充電するプリチャージすることを特徴とするアクティブマトリクス型の電流制御型発光素子の駆動方法。 Wherein and the buffer circuit is composed of an input terminal of the source follower the connected p- channel type thin film transistor and a light emitting device, pre-loaded before the threshold voltage to the compensation capacitor by the switching circuit is written the driving method of an active matrix type of the current control type light emitting device characterized by precharging charged to the supply voltage.
  5. 【請求項5】ソースフォロワ接続されるトランジスタがnチャンネルトランジスタとpチャンネルトランジスタがプッシュプル接続されていることを特徴とする請求項2記載のアクティブマトリクス型の電流制御型発光素子の駆動回路。 5. The driving circuit of an active matrix type of the current control type light emitting device according to claim 2, wherein the source-follower-connected are transistors n-channel transistor and a p-channel transistor is characterized in that it is a push-pull connection.
  6. 【請求項6】バッファ回路が差動増幅器により構成され、該差動増幅器の出力オフセットをキャンセルするための補償コンデンサ及び該補償コンデンサにしきい値電圧を記憶させるためのスイッチング回路が組み込まれている請求項1記載のアクティブマトリクス型の電流制御型発光素子の駆動回路。 6. The buffer circuit is constituted by a differential amplifier, wherein the switching circuit for storing the threshold voltage compensation capacitor and the compensation capacitor for canceling the output offset of the differential amplifier is incorporated active matrix driving circuit of the current control type light emitting device of claim 1, wherein.
  7. 【請求項7】素子に流れる電流に応じて輝度が変化する発光素子からなる画素を選択するための走査線と、前記画素を駆動するための電圧を供給するデータ線とが基板上にマトリクス状に配設され、前記走査線と前記データ線との交差部に、発光素子の輝度を制御するための電圧がデータ線より供給されており、前記走査線により与えられる走査信号により前記データ線の電圧をスイッチングする薄膜トランジスタと、前記発光素子にその出力端子が接続されており、前記スイッチング用の薄膜トランジスタの出力端子とその入力端子が接続されているバッファ回路と該バッファ回路の入力端子電圧と該バッファ回路の出力端子から出力される電圧の差であるオフセット電圧が補償される補償回路とを有する電流制御型発光素子であって、前 7. A scan line for selecting the pixels consisting of light emitting element which changes its luminance according to a current flowing through the device, and a data line for supplying a voltage for driving the pixel matrix on the substrate to be disposed, the intersections of the scanning lines and the data lines, the voltage for controlling the brightness of the light emitting element is supplied from the data lines, the data lines by the scanning signal supplied by the scanning lines a thin film transistor for switching a voltage, said has its output terminal to the light emitting element is connected, the input terminal voltage and the buffer output terminal and the buffer circuit and the buffer circuit having an input terminal connected to the thin film transistor for the switching a current-controlled light-emitting element and a compensation circuit offset voltage is compensated is the difference in voltage output from the output terminal of the circuit, before 補償回路が前記バッファ回路に内蔵されていることを特徴とする電流制御型発光素子。 Current-controlled light-emitting element characterized in that the compensation circuit is incorporated in the buffer circuit.
JP25438699A 1999-09-08 1999-09-08 Drive circuit and drive method of current control type light emitting element Pending JP2001083924A (en)

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JP2004271577A (en) * 2003-03-05 2004-09-30 Toshiba Matsushita Display Technology Co Ltd El display device
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JP2006003716A (en) * 2004-06-18 2006-01-05 Seiko Epson Corp Electronic circuit, its controlling method, electro-optic device, and electronic appliance
JPWO2004045251A1 (en) * 2002-11-13 2006-03-16 松下電器産業株式会社 The light-emitting device
US7098904B2 (en) 2001-11-19 2006-08-29 Nec Electronics Corporation Display control circuit and display device
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US7307463B2 (en) 2003-04-09 2007-12-11 Semiconductor Energy Laboratory Co., Ltd. Source follower, voltage follower, and semiconductor device
US7365713B2 (en) 2001-10-24 2008-04-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
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US7436376B2 (en) 2001-10-10 2008-10-14 Hitachi, Ltd. Image display device
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US7456810B2 (en) 2001-10-26 2008-11-25 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and driving method thereof
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US7777698B2 (en) 2002-04-26 2010-08-17 Toshiba Matsushita Display Technology, Co., Ltd. Drive method of EL display panel
US7808008B2 (en) 2007-06-29 2010-10-05 Semiconductor Energy Laboratory Co., Ltd. Display device and driving method thereof
US7924244B2 (en) 2002-01-24 2011-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving the semiconductor device
US7924248B2 (en) 2002-04-26 2011-04-12 Toshiba Matsushita Display Technology Co., Ltd. Drive method of EL display apparatus
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US8994029B2 (en) 2001-10-24 2015-03-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
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US9892679B2 (en) 2001-10-24 2018-02-13 Semiconductor Energy Laboratory Co., Ltd. Display device
US8659027B2 (en) 2001-10-24 2014-02-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
US7365713B2 (en) 2001-10-24 2008-04-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
US8378356B2 (en) 2001-10-24 2013-02-19 Semiconductor Energy Laboratory Co., Ltd. Display device including pixel
US9449549B2 (en) 2001-10-24 2016-09-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
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US8035109B2 (en) 2001-10-24 2011-10-11 Semiconductor Energy Laboratory Co., Ltd. Display device including EL element
US9171870B2 (en) 2001-10-26 2015-10-27 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and driving method thereof
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US10043862B2 (en) 2001-10-26 2018-08-07 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and driving method thereof
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US8063859B2 (en) 2001-10-26 2011-11-22 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and driving method thereof
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US8941314B2 (en) 2001-10-26 2015-01-27 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and driving method thereof
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US9601560B2 (en) 2001-10-26 2017-03-21 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and driving method
JP2016191930A (en) * 2001-11-13 2016-11-10 株式会社半導体エネルギー研究所 Display device and electronic apparatus
US8242986B2 (en) 2001-11-13 2012-08-14 Semiconductor Energy Laboratory Co., Ltd. Display device and method for driving the same
US10128280B2 (en) 2001-11-13 2018-11-13 Semiconductor Energy Laboratory Co., Ltd. Display device and method for driving the same
US9825068B2 (en) 2001-11-13 2017-11-21 Semiconductor Energy Laboratory Co., Ltd. Display device and method for driving the same
JP2003216110A (en) * 2001-11-13 2003-07-30 Semiconductor Energy Lab Co Ltd Display device
JP2016173580A (en) * 2001-11-13 2016-09-29 株式会社半導体エネルギー研究所 Display device
US8508443B2 (en) 2001-11-13 2013-08-13 Semiconductor Energy Laboratory Co., Ltd. Display device and method for driving the same
JP2014160270A (en) * 2001-11-13 2014-09-04 Semiconductor Energy Lab Co Ltd Display device, display module and electronic apparatus
JP2013178528A (en) * 2001-11-13 2013-09-09 Semiconductor Energy Lab Co Ltd Display device
JP4485119B2 (en) * 2001-11-13 2010-06-16 株式会社半導体エネルギー研究所 Display device
US8059068B2 (en) 2001-11-13 2011-11-15 Semiconductor Energy Laboratory Co., Ltd. Display device and method for driving the same
US7098904B2 (en) 2001-11-19 2006-08-29 Nec Electronics Corporation Display control circuit and display device
US7746157B2 (en) 2001-11-28 2010-06-29 Semiconductor Energy Laboratory Co., Ltd. Electric circuit
US6927618B2 (en) 2001-11-28 2005-08-09 Semiconductor Energy Laboratory Co., Ltd. Electric circuit
US8841941B2 (en) 2001-11-28 2014-09-23 Semiconductor Energy Laboratory Co., Ltd. Electric circuit
JP2013102465A (en) * 2001-11-28 2013-05-23 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2011250462A (en) * 2001-11-28 2011-12-08 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic equipment
US8536937B2 (en) 2001-11-28 2013-09-17 Semiconductor Energy Laboratory Co., Ltd. Electric circuit
US7348825B2 (en) 2001-11-28 2008-03-25 Semiconductor Energy Laboratory Co., Ltd. Electric circuit
US9419570B2 (en) 2001-11-28 2016-08-16 Semiconductor Energy Laboratory Co., Ltd. Electric circuit
US10089923B2 (en) 2001-11-28 2018-10-02 Semiconductor Energy Laboratory Co., Ltd. Electric circuit
US8400191B2 (en) 2001-11-28 2013-03-19 Semiconductor Energy Laboratory Co., Ltd. Electric circuit
US8253446B2 (en) 2002-01-17 2012-08-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic apparatus using the same
US8669791B2 (en) 2002-01-17 2014-03-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic apparatus using the same
JP2012253828A (en) * 2002-01-17 2012-12-20 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2013176143A (en) * 2002-01-17 2013-09-05 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic apparatus
US8149043B2 (en) 2002-01-17 2012-04-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic apparatus using the same
JP2008206195A (en) * 2002-01-17 2008-09-04 Semiconductor Energy Lab Co Ltd Semiconductor device
US8928362B2 (en) 2002-01-17 2015-01-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic apparatus using the same
JP2011205699A (en) * 2002-01-17 2011-10-13 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic apparatus
US7924244B2 (en) 2002-01-24 2011-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving the semiconductor device
US9450036B2 (en) 2002-01-24 2016-09-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving the semiconductor device
US10355068B2 (en) 2002-01-24 2019-07-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving the semiconductor device
US8497823B2 (en) 2002-01-24 2013-07-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving the semiconductor device
US8994622B2 (en) 2002-01-24 2015-03-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving the semiconductor device
US8063855B2 (en) 2002-04-26 2011-11-22 Toshiba Matsushita Display Technology Co., Ltd. Drive method of EL display panel
US7924248B2 (en) 2002-04-26 2011-04-12 Toshiba Matsushita Display Technology Co., Ltd. Drive method of EL display apparatus
US7932880B2 (en) 2002-04-26 2011-04-26 Toshiba Matsushita Display Technology Co., Ltd. EL display panel driving method
US7777698B2 (en) 2002-04-26 2010-08-17 Toshiba Matsushita Display Technology, Co., Ltd. Drive method of EL display panel
JPWO2004045251A1 (en) * 2002-11-13 2006-03-16 松下電器産業株式会社 The light-emitting device
US7796098B2 (en) 2002-11-13 2010-09-14 Panasonic Corporation Light emitting device
JP2004280059A (en) * 2003-02-24 2004-10-07 Chi Mei Electronics Corp Display device
JP4734529B2 (en) * 2003-02-24 2011-07-27 京セラ株式会社 Display device
JP2004295131A (en) * 2003-03-04 2004-10-21 Frank Robert Libsch Drive circuit for display device
JP4703103B2 (en) * 2003-03-05 2011-06-15 東芝モバイルディスプレイ株式会社 Driving method of active matrix type EL display device
JP2004271577A (en) * 2003-03-05 2004-09-30 Toshiba Matsushita Display Technology Co Ltd El display device
CN1319039C (en) * 2003-03-21 2007-05-30 友达光电股份有限公司 Active matrix organic light emitting diode pixel circuit capable of automatically compensating current
US7307463B2 (en) 2003-04-09 2007-12-11 Semiconductor Energy Laboratory Co., Ltd. Source follower, voltage follower, and semiconductor device
KR101033676B1 (en) 2003-05-19 2011-05-12 소니 주식회사 A pixel circuit, display device and a method for driving a pixel circuit
JP2005189497A (en) * 2003-12-25 2005-07-14 Toshiba Matsushita Display Technology Co Ltd Method for driving current output type semiconductor circuit
CN100399401C (en) 2004-01-22 2008-07-02 友达光电股份有限公司 Buffer for liquid crystal display and offset voltage compensation method thereof
JP2010160508A (en) * 2004-05-20 2010-07-22 Kyocera Corp Method of driving image display device
US8937581B2 (en) 2004-05-28 2015-01-20 Sony Corporation Display device having shared column lines
US8988327B2 (en) 2004-05-28 2015-03-24 Sony Corporation Display device having shared column lines
US9711086B2 (en) 2004-05-28 2017-07-18 Sony Corporation Display device having shared column lines
US9460669B2 (en) 2004-05-28 2016-10-04 Sony Corporation Display device having shared column lines
US10170042B2 (en) 2004-05-28 2019-01-01 Sony Corporation Display device having shared column lines
US9934726B2 (en) 2004-05-28 2018-04-03 Sony Corporation Display device having shared column lines
US8643572B2 (en) 2004-05-28 2014-02-04 Sony Corporation Pixel circuit and display device having an electrooptic element controlled in luminance by a signal line
US9202424B2 (en) 2004-05-28 2015-12-01 Sony Corporation Display device having shared column lines
US8378930B2 (en) 2004-05-28 2013-02-19 Sony Corporation Pixel circuit and display device having symmetric pixel circuits and shared voltage lines
US8519915B2 (en) 2004-05-28 2013-08-27 Sony Corporation Pixel circuit and display device having an electrooptic element
US8823607B2 (en) 2004-06-02 2014-09-02 Sony Corporation Pixel circuit, active matrix apparatus and display apparatus with first and second reference potentials applied to source and gate of drive transistor
US10276102B2 (en) 2004-06-02 2019-04-30 Sony Corporation Pixel circuit, active matrix apparatus and display apparatus
US10002567B2 (en) 2004-06-02 2018-06-19 Sony Corporation Pixel circuit, active matrix apparatus and display apparatus with first and second reference potentials applied to gate and other terminal of drive transistor
US9454929B2 (en) 2004-06-02 2016-09-27 Sony Corporation Pixel circuit, active matrix apparatus and display apparatus with first and second reference potentials applied to source, and gate of drive transistor
US9454928B2 (en) 2004-06-02 2016-09-27 Sony Corporation Pixel circuit, active matrix apparatus and display apparatus with first and second reference potentials applied to source, and gate of drive transistor
US8441417B2 (en) 2004-06-02 2013-05-14 Sony Corporation Pixel circuit, active matrix apparatus and display apparatus
KR101200066B1 (en) 2004-06-02 2012-11-12 소니 주식회사 Pixel circuit, active matrix apparatus and display apparatus
JP2006003716A (en) * 2004-06-18 2006-01-05 Seiko Epson Corp Electronic circuit, its controlling method, electro-optic device, and electronic appliance
JP2006301159A (en) * 2005-04-19 2006-11-02 Seiko Epson Corp Electronic circuit, its driving method, electro-optical device, and electronic equipment
US8338835B2 (en) 2007-06-29 2012-12-25 Semiconductor Energy Laboratory Co., Ltd. Display device and driving method thereof
US8816359B2 (en) 2007-06-29 2014-08-26 Semiconductor Energy Laboratory Co., Ltd. Display device and driving method thereof
US7808008B2 (en) 2007-06-29 2010-10-05 Semiconductor Energy Laboratory Co., Ltd. Display device and driving method thereof
JP2008276263A (en) * 2008-08-04 2008-11-13 Sony Corp Pixel circuit, method for driving the same, display device and method for driving the same
JP4544355B2 (en) * 2008-08-04 2010-09-15 ソニー株式会社 Pixel circuit, driving method thereof, display device, and driving method thereof
JP2010078922A (en) * 2008-09-26 2010-04-08 Toshiba Corp Display device and method of driving the same
US8749454B2 (en) 2008-10-07 2014-06-10 Panasonic Corporation Image display device and method of controlling the same
JP4719821B2 (en) * 2008-10-07 2011-07-06 パナソニック株式会社 Image display device and control method thereof
US8248331B2 (en) 2008-10-07 2012-08-21 Panasonic Corporation Image display device and method of controlling the same
US8018404B2 (en) 2008-10-07 2011-09-13 Panasonic Corporation Image display device and method of controlling the same
US9454932B2 (en) 2011-11-24 2016-09-27 Joled Inc. Display device and method of controlling the same
WO2013076772A1 (en) * 2011-11-24 2013-05-30 パナソニック株式会社 Display device and control method thereof
JP2013178311A (en) * 2012-02-28 2013-09-09 Canon Inc Pixel circuit and driving method of the same

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