JP2008276263A - Pixel circuit, method for driving the same, display device and method for driving the same - Google Patents

Pixel circuit, method for driving the same, display device and method for driving the same Download PDF

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JP2008276263A
JP2008276263A JP2008200405A JP2008200405A JP2008276263A JP 2008276263 A JP2008276263 A JP 2008276263A JP 2008200405 A JP2008200405 A JP 2008200405A JP 2008200405 A JP2008200405 A JP 2008200405A JP 2008276263 A JP2008276263 A JP 2008276263A
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JP4544355B2 (en
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Katsuhide Uchino
勝秀 内野
Yukito Iida
幸人 飯田
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Sony Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which enables high definition by simplification of a pixel circuit. <P>SOLUTION: In a transistor 3A for sampling, a gate is connected to a scanning line WSL 101, a source is connected to a signal line DTL 101 and a drain is connected to a gate of a transistor 3B for driving. In the transistor 3B for driving, a source is connected to a light emitting element 3D and a drain is connected to a power line DSL 101. The power line is switched between first potential and second potential. The transistor 3B for driving flows drive current to the light emitting element 3D according to signal potential held in holding capacitor 3C. The potential of the power line DSL 101 becomes the second potential to the first potential while the transistor 3A for sampling is conducted and reference potential different from the second potential is supplied to the signal line DTL 101. The signal potential is held by the holding capacitor 3C while the transistor 3A for sampling is conducted and the signal potential is supplied to the signal line DTL 101. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は発光素子を画素に用いたアクティブマトリクス型の表示装置及びその駆動方法に関する。又、画素回路及びその駆動方法に関する。   The present invention relates to an active matrix display device using a light emitting element for a pixel and a driving method thereof. The present invention also relates to a pixel circuit and a driving method thereof.

発光素子として有機ELデバイスを用いた平面自発光型の表示装置の開発が近年盛んになっている。有機ELデバイスは有機薄膜に電界をかけると発光する現象を利用したデバイスである。有機ELデバイスは印加電圧が10V以下で駆動するため低消費電力である。また有機ELデバイスは自ら光を発する自発光素子であるため、照明部材を必要とせず軽量化及び薄型化が容易である。さらに有機ELデバイスの応答速度は数μs程度と非常に高速であるので、動画表示時の残像が発生しない。   In recent years, development of flat self-luminous display devices using organic EL devices as light-emitting elements has become active. An organic EL device is a device that utilizes the phenomenon of light emission when an electric field is applied to an organic thin film. Since the organic EL device is driven at an applied voltage of 10 V or less, it has low power consumption. In addition, since the organic EL device is a self-luminous element that emits light, it does not require an illumination member and can be easily reduced in weight and thickness. Furthermore, since the response speed of the organic EL device is as high as several μs, an afterimage does not occur when displaying a moving image.

有機ELデバイスを画素に用いた平面自発光型の表示装置の中でも、とりわけ駆動素子として薄膜トランジスタを各画素に集積形成したアクティブマトリクス型の表示装置の開発が盛んである。アクティブマトリクス型平面自発光表示装置は、例えば以下の特許文献1ないし5に記載されている。
特開2003−255856 特開2003−271095 特開2004−133240 特開2004−029791 特開2004−093682 特開2004−295131
Among planar self-luminous display devices that use organic EL devices as pixels, active matrix display devices in which thin film transistors are integrated and formed as driving elements in each pixel are particularly active. Active matrix type flat self-luminous display devices are described in, for example, Patent Documents 1 to 5 below.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A JP 2004-295131 A

しかしながら、従来のアクティブマトリクス型平面自発光表示装置は、プロセス変動により発光素子を駆動するトランジスタの閾電圧や移動度がばらついてしまう。また、有機ELデバイスの特性が経時的に変動する。この様な駆動用トランジスタの特性ばらつきや有機ELデバイスの特性変動は、発光輝度に影響を与えてしまう。表示装置の画面全体にわたって発光輝度を均一に制御するため、各画素回路内で上述したトランジスタや有機ELデバイスの特性変動を補正する必要がある。従来からかかる補正機能を画素毎に備えた表示装置が提案されている。しかしながら、従来の補正機能を備えた画素回路は、補正用の電位を供給する配線と、スイッチング用のトランジスタと、スイッチング用のパルスが必要であり、画素回路の構成が複雑である。画素回路の構成要素が多いことから、ディスプレイの高精細化の妨げとなっていた。   However, in the conventional active matrix type flat self-luminous display device, the threshold voltage and mobility of the transistor driving the light emitting element vary due to process variations. In addition, the characteristics of the organic EL device vary with time. Such variation in characteristics of the driving transistor and characteristic variation of the organic EL device affect the light emission luminance. In order to uniformly control the light emission luminance over the entire screen of the display device, it is necessary to correct the above-described characteristic variation of the transistor and the organic EL device in each pixel circuit. Conventionally, a display device having such a correction function for each pixel has been proposed. However, a conventional pixel circuit having a correction function requires a wiring for supplying a correction potential, a switching transistor, and a switching pulse, and the configuration of the pixel circuit is complicated. Since there are many components of the pixel circuit, it has been an obstacle to high-definition display.

上述した従来の技術の課題に鑑み、本発明は画素回路の簡素化によりディスプレイの高精細化を可能にした表示装置及びその駆動方法を提供することを目的とする。かかる目的を達成するために以下の手段を講じた。即ち本発明にかかる画素回路は、発光素子と、サンプリング用トランジスタと、駆動用トランジスタと、保持容量とを含み、前記サンプリング用トランジスタは、そのゲートが走査線に接続し、そのソース及びドレインの一方が信号線に接続し、他方が該駆動用トランジスタのゲートに接続し、前記駆動用トランジスタは、そのソース及びドレインの一方が該発光素子に接続し、他方が電源線に接続し、該電源線は第1電位と第2電位とで切り替わり、前記保持容量は、該駆動用トランジスタのソースおよびドレインの一方とゲートの間に接続しており、前記駆動用トランジスタは、該保持容量に保持された信号電位に応じて駆動電流を該発光素子に流し、前記サンプリング用トランジスタが導通している間であって、該第2電位と異なる基準電位が該信号線に供給されている間に、電源線の電位は第2電位から第1電位になり、前記サンプリング用トランジスタが導通している間であって、信号電位が該信号線に供給されている間に、信号電位が該保持容量に保持される。   SUMMARY OF THE INVENTION In view of the above-described problems of the conventional technology, an object of the present invention is to provide a display device and a driving method thereof that enable high definition display by simplifying a pixel circuit. In order to achieve this purpose, the following measures were taken. That is, a pixel circuit according to the present invention includes a light emitting element, a sampling transistor, a driving transistor, and a storage capacitor. The sampling transistor has a gate connected to a scanning line, and has one of a source and a drain. Is connected to the signal line, the other is connected to the gate of the driving transistor, and one of the source and drain of the driving transistor is connected to the light emitting element, and the other is connected to the power supply line. Is switched between the first potential and the second potential, and the storage capacitor is connected between one of the source and drain of the driving transistor and the gate, and the driving transistor is held in the storage capacitor A driving current is passed through the light emitting element in accordance with a signal potential, and the sampling transistor is in a conductive state and is different from the second potential. While the potential is supplied to the signal line, the potential of the power supply line is changed from the second potential to the first potential, and the signal potential is supplied to the signal line while the sampling transistor is conductive. During this time, the signal potential is held in the holding capacitor.

好ましくは、前記サンプリング用トランジスタが導通している間であって、該第1電位と該第2電位の間にある基準電位が該信号線に供給されている間に、電源線の電位は該第2電位から該第1電位になる。又、前記保持容量の一端に該基準電位を書込み他端に該第2電位を書込み、その後前記サンプリング用トランジスタが導通している間であって該基準電位が該信号線に供給されている間に、電源線の電位を該第2電位から該第1電位にする。この場合、前記保持容量の一端に該基準電位を書込み他端に該第2電位を書込んで両端の電位差を前記駆動用トランジスタの閾電圧より大きく設定し、その後前記サンプリング用トランジスタが導通している間であって該基準電位が該信号線に供給されている間に電源線の電位を該第2電位から該第1電位にして、該保持容量の他端の電位を該保持容量の一端の電位に向かって変化させる。又該走査線は線順次走査され、前記電源線も該線順次走査に合わせて走査して順次電源線の電位が該第2電位から該第1電位に切り替わる。   Preferably, while the sampling transistor is conducting, and while the reference potential between the first potential and the second potential is supplied to the signal line, the potential of the power supply line is From the second potential to the first potential. Further, the reference potential is written to one end of the storage capacitor, the second potential is written to the other end, and then the reference potential is supplied to the signal line while the sampling transistor is conductive. In addition, the potential of the power supply line is changed from the second potential to the first potential. In this case, the reference potential is written to one end of the storage capacitor, the second potential is written to the other end, and the potential difference between both ends is set to be larger than the threshold voltage of the driving transistor, and then the sampling transistor is turned on. While the reference potential is supplied to the signal line, the potential of the power supply line is changed from the second potential to the first potential, and the potential of the other end of the storage capacitor is set to one end of the storage capacitor. Vary toward the potential. Further, the scanning lines are scanned line by line, and the power supply lines are also scanned in accordance with the line sequential scanning, so that the potential of the power supply line is sequentially switched from the second potential to the first potential.

又本発明にかかる表示装置は、画素アレイ部とこれを駆動する駆動部とからなり、前記画素アレイ部は、行状の走査線と、列状の信号線と、両者が交差する部分に配された行列状の画素とを備え、前記画素は、発光素子と、サンプリング用トランジスタと、駆動用トランジスタと、保持容量とを含み、前記サンプリング用トランジスタは、そのゲートが該走査線に接続し、そのソース及びドレインの一方が該信号線に接続し、他方が該駆動用トランジスタのゲートに接続し、前記駆動用トランジスタは、そのソース及びドレインの一方が該発光素子に接続し、他方が該電源線に接続し、前記保持容量は、該ソースおよびドレインの一方と該駆動用トランジスタのゲートの間に接続しており、前記駆動部は、基準電位又は信号電位を供給する映像信号供給回路と、該電源線に第1電位と第2電位を供給する電源スキャナとを備え、前記駆動用トランジスタは、該電源線から電流の供給を受け該保持容量に保持された信号電位に応じて駆動電流を該発光素子に流し、前記サンプリング用トランジスタが導通している間であって、該第2電位と異なる基準電位が該信号線に供給されている間に、該電源線の電位は該第2電位から該第1電位になり、前記サンプリング用トランジスタが導通している間であって、該信号電位が該信号線に供給されている間に、該信号電位が該保持容量に保持される。   The display device according to the present invention includes a pixel array section and a drive section for driving the pixel array section, and the pixel array section is arranged at a portion where the row-shaped scanning lines and the column-shaped signal lines intersect with each other. The pixel includes a light emitting element, a sampling transistor, a driving transistor, and a storage capacitor. The sampling transistor has a gate connected to the scanning line, and One of the source and the drain is connected to the signal line, the other is connected to the gate of the driving transistor, and the driving transistor has one of the source and the drain connected to the light emitting element and the other connected to the power supply line The storage capacitor is connected between one of the source and the drain and the gate of the driving transistor, and the driving unit supplies a reference potential or a signal potential. A signal supply circuit; and a power supply scanner for supplying a first potential and a second potential to the power supply line, wherein the driving transistor is supplied with a current from the power supply line and has a signal potential held in the holding capacitor. Accordingly, a driving current is supplied to the light emitting element, and the potential of the power supply line is supplied while the sampling transistor is conductive and a reference potential different from the second potential is supplied to the signal line. Is changed from the second potential to the first potential, and the signal potential is applied to the storage capacitor while the sampling transistor is conducting and the signal potential is supplied to the signal line. Retained.

好ましくは、前記サンプリング用トランジスタが導通している間であって、該第1電位と該第2電位の間にある基準電位が該信号線に供給されている間に、電源線の電位は該第2電位から該第1電位になる。一態様では、前記保持容量の一端に該基準電位を書込み他端に該第2電位を書込み、その後前記サンプリング用トランジスタが導通している間であって該基準電位が該信号線に供給されている間に、電源線の電位を該第2電位から該第1電位にする。この場合、前記保持容量の一端に該基準電位を書込み他端に該第2電位を書込んで両端の電位差を前記駆動用トランジスタの閾電圧より大きく設定し、その後前記サンプリング用トランジスタが導通している間であって該基準電位が該信号線に供給されている間に電源線の電位を該第2電位から該第1電位にして、該保持容量の他端の電位を該保持容量の一端の電位に向かって変化させる。又前記電源スキャナは、各電源線を線順次走査して、順次各電源線の電位を該第2電位から該第1電位に切り替える。   Preferably, while the sampling transistor is conducting, and while the reference potential between the first potential and the second potential is supplied to the signal line, the potential of the power supply line is From the second potential to the first potential. In one embodiment, the reference potential is written to one end of the storage capacitor, the second potential is written to the other end, and then the reference potential is supplied to the signal line while the sampling transistor is conductive. During this period, the potential of the power supply line is changed from the second potential to the first potential. In this case, the reference potential is written to one end of the storage capacitor, the second potential is written to the other end, and the potential difference between both ends is set to be larger than the threshold voltage of the driving transistor, and then the sampling transistor is turned on. While the reference potential is supplied to the signal line, the potential of the power supply line is changed from the second potential to the first potential, and the potential of the other end of the storage capacitor is set to one end of the storage capacitor. Vary toward the potential. The power supply scanner scans each power supply line sequentially and sequentially switches the potential of each power supply line from the second potential to the first potential.

本発明にかかる表示装置は、画素毎に閾電圧補正機能、移動度補正機能、ブートストラップ機能などを備えている。閾電圧補正機能により駆動用トランジスタの閾電圧変動を補正することが出来る。また移動度補正機能により同じく駆動用トランジスタの移動度変動を補正することが出来る。また発光時における保持容量のブートストラップ動作により、有機ELデバイスの特性変動に関わらず、常に一定の発光輝度を保つことが出来る。即ち有機ELデバイスの電流‐電圧特性が経時変動しても、駆動用トランジスタのゲート‐ソース間電圧がブートストラップした保持容量により一定に保たれるため、発光輝度を一定に維持することが出来る。   The display device according to the present invention includes a threshold voltage correction function, a mobility correction function, a bootstrap function, and the like for each pixel. The threshold voltage variation of the driving transistor can be corrected by the threshold voltage correction function. Similarly, the mobility variation of the driving transistor can be corrected by the mobility correction function. In addition, by the bootstrap operation of the storage capacitor at the time of light emission, it is possible to always maintain a constant light emission luminance regardless of fluctuations in the characteristics of the organic EL device. That is, even if the current-voltage characteristic of the organic EL device varies with time, the gate-source voltage of the driving transistor is kept constant by the bootstrap holding capacitor, so that the light emission luminance can be kept constant.

本発明は各画素に上述した閾電圧補正機能、移動度補正機能、ブートストラップ動作などを組み込むため、各画素に供給する電源電圧をスイッチングパルスとして使用する。電源電圧をスイッチングパルス化することで、閾電圧補正用のスイッチングトランジスタやそのゲートを制御する走査線が不要になる。結果として、画素回路の構成素子と配線が大幅に削減でき、画素エリアを縮小することが可能となり、ディスプレイの高精細化を達成できる。また移動度補正を映像信号電位のサンプリングと同時に行うとこで、移動度補正期間を映像信号とサンプリング用パルスの位相差で調整することが可能である。さらには、移動度補正期間を映像信号のレベルに自動的に追従させることが出来る。また画素の構成素子が少ないことにより、駆動用トランジスタのゲートに寄生する容量が少なくなる為、ブートストラップ動作が確実となり、有機ELデバイスの経時変動に対する補正能力を改善することが出来る。   In the present invention, since the above-described threshold voltage correction function, mobility correction function, bootstrap operation, and the like are incorporated in each pixel, a power supply voltage supplied to each pixel is used as a switching pulse. By making the power supply voltage into a switching pulse, a switching transistor for threshold voltage correction and a scanning line for controlling the gate thereof become unnecessary. As a result, the constituent elements and wiring of the pixel circuit can be greatly reduced, the pixel area can be reduced, and high definition of the display can be achieved. Further, by performing the mobility correction simultaneously with the sampling of the video signal potential, the mobility correction period can be adjusted by the phase difference between the video signal and the sampling pulse. Furthermore, the mobility correction period can automatically follow the level of the video signal. In addition, since the number of constituent elements of the pixel is small, the capacitance parasitic to the gate of the driving transistor is reduced, so that the bootstrap operation is ensured, and the correction capability with respect to the temporal variation of the organic EL device can be improved.

本発明によれば、有機ELデバイスなどの発光素子を画素に用いたアクティブマトリクス型の表示装置において、各画素が駆動用トランジスタの閾電圧補正機能と移動度補正機能及び有機ELデバイスの経時変動補正機能(ブートストラップ動作)を備えており、高品位の画質を得ることが出来る。特に移動度補正については映像信号電位に追従して適切な補正期間を自動的に設定できるため、画像の輝度や絵柄によらず移動度補正が可能である。従来このような補正機能を備えた画素回路は構成素子数が多いためレイアウト面積が大きくなり、ディスプレイの高精細化には不向きであったが、本発明では電源電圧をスイッチングすることにより構成素子数と配線数を削減し、画素のレイアウト面積を小さくすることが可能である。以上により、高品位且つ高精細なフラットディスプレイを提供することが可能になる。   According to the present invention, in an active matrix display device using a light emitting element such as an organic EL device as a pixel, each pixel has a threshold voltage correction function and a mobility correction function of a driving transistor, and a temporal variation correction of the organic EL device. A function (bootstrap operation) is provided, and high-quality image quality can be obtained. In particular, with regard to mobility correction, an appropriate correction period can be automatically set following the video signal potential, so that mobility correction can be performed regardless of the brightness and design of the image. Conventionally, a pixel circuit having such a correction function has a large layout area due to a large number of constituent elements, which is not suitable for high-definition display. However, in the present invention, the number of constituent elements is changed by switching the power supply voltage. Thus, the number of wirings can be reduced, and the layout area of the pixel can be reduced. As described above, a high-quality and high-definition flat display can be provided.

以下図面を参照して本発明の実施の形態を詳細に説明する。まず最初に本発明の理解を容易にし且つ背景を明らかにするため、図1を参照して表示装置の一般的な構成を簡潔に説明する。図1は、一般的な表示装置の一画素分を示す模式的な回路図である。図示する様にこの画素回路は、直交配列した走査線1Eと信号線1Fの交差部に、サンプリング用トランジスタ1Aが配置されている。このサンプリング用トランジスタ1AはN型であり、そのゲートが走査線1Eに接続し、ドレインが信号線1Fに接続している。このサンプリング用トランジスタ1Aのソースには保持容量1Cの一方の電極と、駆動用トランジスタ1Bのゲートとが接続されている。駆動用トランジスタ1BはN型で、そのドレインには電源供給線1Gが接続し、そのソースには発光素子1Dのアノードが接続している。保持容量1Cの他方の電極と発光素子1Dのカソードは、接地配線1Hに接続している。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, in order to facilitate understanding of the present invention and to clarify the background, a general configuration of a display device will be briefly described with reference to FIG. FIG. 1 is a schematic circuit diagram showing one pixel of a general display device. As shown in the figure, in this pixel circuit, a sampling transistor 1A is arranged at the intersection of the scanning line 1E and the signal line 1F arranged orthogonally. The sampling transistor 1A is N-type, and has a gate connected to the scanning line 1E and a drain connected to the signal line 1F. One electrode of the storage capacitor 1C and the gate of the driving transistor 1B are connected to the source of the sampling transistor 1A. The driving transistor 1B is N-type, the power supply line 1G is connected to the drain, and the anode of the light emitting element 1D is connected to the source. The other electrode of the storage capacitor 1C and the cathode of the light emitting element 1D are connected to the ground wiring 1H.

図2は、図1に示した画素回路の動作説明に供するタイミングチャートである。このタイミングチャートは、信号線(1F)から供給される映像信号の電位(映像信号線電位)をサンプリングし、有機ELデバイスなどからなる発光素子1Dを発光状態にする動作を表している。走査線(1E)の電位(走査線電位)が高レベルに遷移することで、サンプリング用トランジスタ(1A)はオン状態となり、映像信号線電位を保持容量(1C)に充電する。これにより駆動用トランジスタ(1B)のゲート電位(Vg)は上昇を開始し、ドレイン電流を流し始める。その為発光素子(1D)のアノード電位は上昇し発光を開始する。この後走査線電位が低レベルに遷移すると保持容量(1C)に映像信号線電位が保持され、駆動用トランジスタ(1B)のゲート電位が一定となり、発光輝度が次のフレームまで一定に維持される。   FIG. 2 is a timing chart for explaining the operation of the pixel circuit shown in FIG. This timing chart represents an operation of sampling the potential (video signal line potential) of the video signal supplied from the signal line (1F) and setting the light emitting element 1D made of an organic EL device to a light emitting state. When the potential of the scanning line (1E) (scanning line potential) transitions to a high level, the sampling transistor (1A) is turned on, and the video signal line potential is charged in the storage capacitor (1C). As a result, the gate potential (Vg) of the driving transistor (1B) starts to rise and the drain current starts to flow. Therefore, the anode potential of the light emitting element (1D) rises and light emission starts. Thereafter, when the scanning line potential transitions to a low level, the video signal line potential is held in the holding capacitor (1C), the gate potential of the driving transistor (1B) becomes constant, and the light emission luminance is kept constant until the next frame. .

しかしながら駆動用トランジスタ(1B)の製造プロセスのばらつきにより、各画素ごとに閾電圧や移動度などの特性変動がある。この特性変動により、駆動用トランジスタ(1B)に同一のゲート電位を与えても、画素毎にドレイン電流(駆動電流)が変動し、発光輝度のばらつきになって現れる。また有機ELデバイスなどからなる発光素子(1D)の特性の経時変動により、発光素子(1D)のアノード電位が変動する。アノード電位の変動は駆動用トランジスタ(1B)のゲート‐ソース間電圧の変動となって現れ、ドレイン電流(駆動電流)の変動を引き起こす。この様な種々の原因による駆動電流の変動は画素ごとの発光輝度のばらつきとなって現れ、画質の劣化が起きる。   However, due to variations in the manufacturing process of the driving transistor (1B), there are variations in characteristics such as threshold voltage and mobility for each pixel. Due to this characteristic variation, even if the same gate potential is applied to the driving transistor (1B), the drain current (driving current) varies from pixel to pixel, resulting in variations in light emission luminance. In addition, the anode potential of the light emitting element (1D) varies due to the temporal variation of the characteristics of the light emitting element (1D) made of an organic EL device or the like. The fluctuation of the anode potential appears as a fluctuation of the gate-source voltage of the driving transistor (1B) and causes a fluctuation of the drain current (driving current). Such fluctuations in the drive current due to various causes appear as variations in light emission luminance for each pixel, resulting in degradation of image quality.

図3Aは、本発明にかかる表示装置の全体構成を示すブロック図である。図示する様に、本表示装置100は、画素アレイ部102とこれを駆動する駆動部(103,104,105)とからなる。画素アレイ部102は、行状の走査線WSL101〜10mと、列状の信号線DTL101〜10nと、両者が交差する部分に配された行列状の画素(PXLC)101と、各画素101の各行に対応して配された電源線DSL101〜10mとを備えている。駆動部(103,104,105)は、各走査線WSL101〜10mに順次制御信号を供給して画素101を行単位で線順次走査する主スキャナ(ライトスキャナWSCN)104と、この線順次走査に合わせて各電源線DSL101〜10mに第1電位と第2電位で切換る電源電圧を供給する電源スキャナ(DSCN)105と、この線順次走査に合わせて列状の信号線DTL101〜10nに映像信号となる信号電位と基準電位を供給する信号セレクタ(水平セレクタHSEL)103とを備えている。   FIG. 3A is a block diagram showing the overall configuration of the display device according to the present invention. As shown in the figure, the display device 100 includes a pixel array unit 102 and driving units (103, 104, 105) for driving the pixel array unit 102. The pixel array unit 102 includes row-like scanning lines WSL101 to 10m, column-like signal lines DTL101 to 10n, matrix-like pixels (PXLC) 101 arranged at portions where both intersect, and each pixel 101 in each row. Correspondingly arranged power supply lines DSL101 to 10m are provided. The drive unit (103, 104, 105) supplies a control signal to each of the scanning lines WSL101 to 10m in order to scan the pixels 101 line-sequentially in units of rows, and this line-sequential scanning. In addition, a power supply scanner (DSCN) 105 that supplies power supply voltages to be switched between the first potential and the second potential to the power supply lines DSL101 to 10m, and video signals to the column-shaped signal lines DTL101 to 10n in accordance with the line sequential scanning. And a signal selector (horizontal selector HSEL) 103 for supplying a reference potential and a reference potential.

図3Bは、図3Aに示した表示装置100に含まれる画素101の具体的な構成及び結線関係を示す回路図である。図示する様に、この画素101は、有機ELデバイスなどで代表される発光素子3Dと、サンプリング用トランジスタ3Aと、駆動用トランジスタ3Bと、保持容量3Cとを含む。サンプリング用トランジスタ3Aは、そのゲートが対応する走査線WSL101に接続し、そのソース及びドレインの一方が対応する信号線DTL101に接続し、他方が駆動用トランジスタ3Bのゲートgに接続する。駆動用トランジスタ3Bは、そのソースs及びドレインdの一方が発光素子3Dに接続し、他方が対応する電源線DSL101に接続している。本実施形態では、駆動用トランジスタ3Bのドレインdが電源線DSL101に接続する一方、ソースsが発光素子3Dのアノードに接続している。発光素子3Dのカソードは接地配線3Hに接続している。なおこの接地配線3Hは全ての画素101に対して共通に配線されている。保持容量3Cは、駆動用トランジスタ3Bのソースsとゲートgの間に接続している。   FIG. 3B is a circuit diagram showing a specific configuration and connection relationship of the pixel 101 included in the display device 100 shown in FIG. 3A. As illustrated, the pixel 101 includes a light emitting element 3D represented by an organic EL device or the like, a sampling transistor 3A, a driving transistor 3B, and a storage capacitor 3C. Sampling transistor 3A has its gate connected to corresponding scanning line WSL101, one of its source and drain connected to corresponding signal line DTL101, and the other connected to gate g of driving transistor 3B. One of the source s and the drain d of the driving transistor 3B is connected to the light emitting element 3D, and the other is connected to the corresponding power supply line DSL101. In the present embodiment, the drain d of the driving transistor 3B is connected to the power supply line DSL101, while the source s is connected to the anode of the light emitting element 3D. The cathode of the light emitting element 3D is connected to the ground wiring 3H. The ground wiring 3H is wired in common to all the pixels 101. The storage capacitor 3C is connected between the source s and the gate g of the driving transistor 3B.

かかる構成において、サンプリング用トランジスタ3Aは、走査線WSL101から供給された制御信号に応じて導通し、信号線DTL101から供給された信号電位をサンプリングして保持容量3Cに保持する。駆動用トランジスタ3Bは、第1電位にある電源線DSL101から電流の供給を受け保持容量3Cに保持された信号電位に応じて駆動電流を発光素子3Dに流す。電源スキャナ(DSCN)105は、サンプリング用トランジスタ3Aが導通した後で信号セレクタ(HSEL)103が信号線DTL101に基準電位を供給している間に、電源線DSL101を第1電位と第2電位との間で切換え、以って駆動用トランジスタ3Bの閾電圧Vthに相当する電圧を保持容量3Cに保持しておく。かかる閾電圧補正機能により、本表示装置100は画素毎にばらつく駆動用トランジスタ3Bの閾電圧の影響をキャンセルすることが出来る。   In such a configuration, the sampling transistor 3A is turned on in response to the control signal supplied from the scanning line WSL101, samples the signal potential supplied from the signal line DTL101, and holds it in the holding capacitor 3C. The driving transistor 3B is supplied with current from the power supply line DSL101 at the first potential, and causes a driving current to flow to the light emitting element 3D in accordance with the signal potential held in the holding capacitor 3C. The power supply scanner (DSCN) 105 sets the power supply line DSL101 to the first potential and the second potential while the signal selector (HSEL) 103 supplies the reference potential to the signal line DTL101 after the sampling transistor 3A is turned on. Thus, a voltage corresponding to the threshold voltage Vth of the driving transistor 3B is held in the holding capacitor 3C. With this threshold voltage correction function, the display device 100 can cancel the influence of the threshold voltage of the driving transistor 3B, which varies from pixel to pixel.

図3Bに示した画素101は上述した閾電圧補正機能に加え、移動度補正機能を備えている。即ち信号セレクタ(HSEL)103は、サンプリング用トランジスタ3Aが導通した後第1のタイミングで信号線DTL101を基準電位から信号電位に切換る一方、主スキャナ(WSCN)104は、第1のタイミングの後第2のタイミングで走査線WSL101に対する制御信号の印加を解除してサンプリング用トランジスタ3Aを非道通状態とし、第1及び第2のタイミングの間の期間を適切に設定することで、保持容量3Cに信号電位を保持する際、駆動用トランジスタ3Bの移動度μに対する補正を信号電位に加えている。この場合、駆動部(103,104,105)は、信号セレクタ103が供給する映像信号と主スキャナ104が供給する制御信号との相対的な位相差を調整して、第1及び第2のタイミングの間の期間(移動度補正期間)を最適化することが出来る。また信号セレクタ103は、基準電位から信号電位に切換る映像信号の立ち上がりに傾斜をつけて、第1及び第2のタイミングの間の移動度補正期間を信号電位に自動的に追従させることも出来る。   The pixel 101 illustrated in FIG. 3B has a mobility correction function in addition to the threshold voltage correction function described above. That is, the signal selector (HSEL) 103 switches the signal line DTL101 from the reference potential to the signal potential at the first timing after the sampling transistor 3A is turned on, while the main scanner (WSCN) 104 is switched after the first timing. By canceling the application of the control signal to the scanning line WSL101 at the second timing to place the sampling transistor 3A in the non-passing state and appropriately setting the period between the first and second timings, the holding capacitor 3C When the signal potential is held, correction for the mobility μ of the driving transistor 3B is added to the signal potential. In this case, the drive unit (103, 104, 105) adjusts the relative phase difference between the video signal supplied from the signal selector 103 and the control signal supplied from the main scanner 104, and the first and second timings are adjusted. (Period of mobility correction) can be optimized. The signal selector 103 can also automatically follow the signal potential in the mobility correction period between the first and second timings by inclining the rising edge of the video signal switching from the reference potential to the signal potential. .

図3Bに示した画素回路101はさらにブートストラップ機能も備えている。即ち主スキャナ(WSCN)104は、保持容量3Cに信号電位が保持された段階で走査線WSL101に対する制御信号の印加を解除し、サンプリング用トランジスタ3Aを非導通状態にして駆動用トランジスタ3Bのゲートgを信号線DTL101から電気的に切り離し、以って駆動用トランジスタ3Bのソース電位(Vs)の変動にゲート電位(Vg)が連動しゲートgとソースs間の電圧Vgsを一定に維持することが出来る。   The pixel circuit 101 shown in FIG. 3B further has a bootstrap function. That is, the main scanner (WSCN) 104 cancels the application of the control signal to the scanning line WSL101 at the stage where the signal potential is held in the holding capacitor 3C, sets the sampling transistor 3A in a non-conductive state, and the gate g of the driving transistor 3B. Is electrically disconnected from the signal line DTL101, so that the gate potential (Vg) is interlocked with the fluctuation of the source potential (Vs) of the driving transistor 3B, and the voltage Vgs between the gate g and the source s is kept constant. I can do it.

図4Aは、図3Bに示した画素101の動作説明に供するタイミングチャートである。時間軸を共通にして、走査線(WSL101)の電位変化、電源線(DSL101)の電位変化及び信号線(DTL101)の電位変化を表してある。またこれらの電位変化と並行に、駆動用トランジスタ3Bのゲート電位(Vg)及びソース電位(Vs)の変化も表してある。   FIG. 4A is a timing chart for explaining the operation of the pixel 101 shown in FIG. 3B. The change in the potential of the scanning line (WSL 101), the change in the potential of the power supply line (DSL 101), and the change in the potential of the signal line (DTL 101) are shown with a common time axis. In parallel with these potential changes, changes in the gate potential (Vg) and source potential (Vs) of the driving transistor 3B are also shown.

このタイミングチャートは、画素101の動作の遷移に合わせて期間を(B)〜(G)のように便宜的に区切ってある。発光期間(B)では発光素子3Dが発光状態にある。この後線順次走査の新しいフィールドに入ってまず最初の期間(C)で、駆動用トランジスタのゲート電位Vgが初期化される。次の期間(D)に進み、駆動用トランジスタのソース電位Vsも初期化される。この様に駆動用トランジスタ3Bのゲート電位Vg及びソース電位Vsを初期化することで、閾電圧補正動作の準備が完了する。続いて閾値補正期間(E)で実際に閾電圧補正動作が行われ、駆動用トランジスタ3Bのゲートgとソースsとの間に閾電圧Vthに相当する電圧が保持される。実際には、Vthに相当する電圧が、駆動用トランジスタ3Bのゲートgとソースsとの間に接続された保持容量3Cに書き込まれることになる。この後サンプリング期間/移動度補正期間(F)に進み、映像信号の信号電位VinがVthに足し込まれる形で保持容量3Cに書き込まれると共に、移動度補正用の電圧ΔVが保持容量3Cに保持された電圧から差し引かれる。この後発光期間(G)に進み、信号電圧Vinに応じた輝度で発光素子が発光する。その際信号電圧Vinは閾電圧Vthに相当する電圧と移動度補正用の電圧ΔVとによって調整されているため、発光素子3Dの発光輝度は駆動用トランジスタ3Bの閾電圧Vthや移動度μのばらつきの影響を受けることがない。なお発光期間(G)の最初でブートストラップ動作が行われ、駆動用トランジスタ3Bのゲート‐ソース間電圧Vgs=Vin+Vth−ΔVを一定に維持したまま、駆動用トランジスタ3Bのゲート電位Vg及びソース電位Vsが上昇する。   In this timing chart, periods are divided for convenience as (B) to (G) in accordance with the transition of the operation of the pixel 101. In the light emission period (B), the light emitting element 3D is in a light emitting state. In the first period (C) after entering the new field of the line sequential scanning, the gate potential Vg of the driving transistor is initialized. In the next period (D), the source potential Vs of the driving transistor is also initialized. Thus, by preparing the gate potential Vg and the source potential Vs of the driving transistor 3B, the preparation for the threshold voltage correction operation is completed. Subsequently, a threshold voltage correction operation is actually performed in the threshold correction period (E), and a voltage corresponding to the threshold voltage Vth is held between the gate g and the source s of the driving transistor 3B. Actually, a voltage corresponding to Vth is written in the holding capacitor 3C connected between the gate g and the source s of the driving transistor 3B. Thereafter, the process proceeds to the sampling period / mobility correction period (F), and the signal potential Vin of the video signal is written to the holding capacitor 3C in a form added to Vth, and the mobility correction voltage ΔV is held in the holding capacitor 3C. Is subtracted from the measured voltage. Thereafter, the light emitting element emits light at a luminance corresponding to the signal voltage Vin in the light emission period (G). At this time, since the signal voltage Vin is adjusted by a voltage corresponding to the threshold voltage Vth and the mobility correction voltage ΔV, the light emission luminance of the light emitting element 3D varies in the threshold voltage Vth and the mobility μ of the driving transistor 3B. Will not be affected. Note that a bootstrap operation is performed at the beginning of the light emission period (G), and the gate potential Vg and the source potential Vs of the driving transistor 3B are maintained while maintaining the gate-source voltage Vgs = Vin + Vth−ΔV of the driving transistor 3B constant. Rises.

引き続き図4B〜図4Gを参照して、図3Bに示した画素101の動作を詳細に説明する。なお、図4B〜図4Gの図番は、図4Aに示したタイミングチャートの各期間(B)〜(G)にそれぞれ対応している。理解を容易にするため、図4B〜図4Gは、説明の都合上発光素子3Dの容量成分を容量素子3Iとして図示してある。先ず図4Bに示すように発光期間(B)では、電源供給線DSL101が高電位Vcc_H(第1電位)にあり、駆動用トランジスタ3Bが駆動電流Idsを発光素子3Dに供給している。図示する様に、駆動電流Idsは高電位Vcc_Hにある電源供給線DSL101から駆動用トランジスタ3Bを介して発光素子3Dを通り、共通接地配線3Hに流れ込んでいる。   4B to 4G, the operation of the pixel 101 shown in FIG. 3B will be described in detail. 4B to 4G correspond to the periods (B) to (G) of the timing chart shown in FIG. 4A, respectively. For ease of understanding, FIGS. 4B to 4G show the capacitive component of the light emitting element 3D as the capacitive element 3I for convenience of explanation. First, as shown in FIG. 4B, in the light emission period (B), the power supply line DSL101 is at the high potential Vcc_H (first potential), and the driving transistor 3B supplies the driving current Ids to the light emitting element 3D. As shown in the figure, the drive current Ids flows from the power supply line DSL101 at the high potential Vcc_H through the light emitting element 3D through the drive transistor 3B and flows into the common ground wiring 3H.

続いて期間(C)に入ると図4Cに示すように、走査線WSL101が高電位側に遷移することでサンプリング用トランジスタ3Aがオン状態となり、駆動用トランジスタ3Bのゲート電位Vgは映像信号線DTL101の基準電位Voに初期化(リセット)される。   Subsequently, when the period (C) is entered, as shown in FIG. 4C, the sampling transistor 3A is turned on by the transition of the scanning line WSL101 to the high potential side, and the gate potential Vg of the driving transistor 3B is equal to the video signal line DTL101. Is initialized (reset) to the reference potential Vo.

次に期間(D)に進むと図4Dに示すように、電源供給線DSL101の電位が高電位Vcc_H(第1電位)から映像信号線DTL101の基準電位Voより十分低い電位Vcc_L(第2電位)に遷移する。これにより駆動用トランジスタ3Bのソース電位Vsが映像信号線DTL101の基準電位Voより十分低い電位Vcc_Lに初期化(リセット)される。具体的には駆動用トランジスタ3Bのゲート‐ソース間電圧Vgs(ゲート電位Vgとソース電位Vsの差)が駆動用トランジスタ3Bの閾電圧Vthより大きくなるように、電源供給線DSL101の低電位Vcc_L(第2電位)を設定する。   Next, in the period (D), as shown in FIG. 4D, the potential Vcc_L (second potential) at which the potential of the power supply line DSL101 is sufficiently lower than the reference potential Vo of the video signal line DTL101 from the high potential Vcc_H (first potential). Transition to. As a result, the source potential Vs of the driving transistor 3B is initialized (reset) to a potential Vcc_L that is sufficiently lower than the reference potential Vo of the video signal line DTL101. Specifically, the gate-source voltage Vgs (the difference between the gate potential Vg and the source potential Vs) of the driving transistor 3B is higher than the threshold voltage Vth of the driving transistor 3B, so that the low potential Vcc_L ( (Second potential) is set.

次に閾値補正期間(E)に進むと図4(E)に示すように、電源供給線DSL101の電位が低電位Vcc_Lから高電位Vcc_Hに遷移し、駆動用トランジスタ3Bのソース電位Vsが上昇を開始する。やがて駆動用トランジスタ3Bのゲート‐ソース間電圧Vgsが閾電圧Vthとなったところで電流がカットオフする。このようにして駆動用トランジスタ3Bの閾電圧Vthに相当する電圧が保持容量3Cに書き込まれる。これが閾電圧補正動作である。このとき電流が専ら保持容量3C側に流れ、発光素子3D側には流れないようにするため、発光素子3Dがカットオフとなるように共通接地配線3Hの電位を設定しておく。   Next, in the threshold correction period (E), as shown in FIG. 4E, the potential of the power supply line DSL101 transits from the low potential Vcc_L to the high potential Vcc_H, and the source potential Vs of the driving transistor 3B increases. Start. Eventually, the current is cut off when the gate-source voltage Vgs of the driving transistor 3B reaches the threshold voltage Vth. In this way, a voltage corresponding to the threshold voltage Vth of the driving transistor 3B is written to the storage capacitor 3C. This is the threshold voltage correction operation. At this time, the potential of the common ground wiring 3H is set so that the light emitting element 3D is cut off in order to prevent the current from flowing exclusively to the holding capacitor 3C and not to the light emitting element 3D.

次にサンプリング期間/移動度補正期間(F)に進むと、図4Fに示すように、第1のタイミングで映像信号線DTL101の電位が基準電位Voから信号電位Vinに遷移し、駆動用トランジスタ3Bのゲート電位VgはVinとなる。このとき発光素子3Dは始めカットオフ状態(ハイインピーダンス状態)にあるため駆動用トランジスタ3Bのドレイン電流Idsは発光素子の寄生容量3Iに流れ込む。これにより発光素子の寄生容量3Iは充電を開始する。よって駆動用トランジスタ3Bのソース電位Vsは上昇を開始し、第2のタイミングで駆動用トランジスタ3Bのゲート‐ソース間電圧VgsはVin+Vth−ΔVとなる。このようにして信号電位Vinのサンプリングと補正量ΔVの調整が行われる。Vinが高いほどIdsは大きくなり、ΔVの絶対値も大きくなる。したがって発光輝度レベルに応じた移動度補正が行える。またVinを一定とした場合、駆動用トランジスタ3Bの移動度μが大きいほどΔVの絶対値も大きくなる。換言すると移動度μが大きいほど負帰還量ΔVが大きくなるので、画素ごとの移動度μのばらつきを取り除くことが可能である。   Next, in the sampling period / mobility correction period (F), as shown in FIG. 4F, the potential of the video signal line DTL101 transits from the reference potential Vo to the signal potential Vin at the first timing, as shown in FIG. 4F, and the driving transistor 3B. The gate potential Vg becomes Vin. At this time, since the light emitting element 3D is initially in a cutoff state (high impedance state), the drain current Ids of the driving transistor 3B flows into the parasitic capacitance 3I of the light emitting element. Thereby, the parasitic capacitance 3I of the light emitting element starts to be charged. Therefore, the source potential Vs of the driving transistor 3B starts to rise, and the gate-source voltage Vgs of the driving transistor 3B becomes Vin + Vth−ΔV at the second timing. In this way, the signal potential Vin is sampled and the correction amount ΔV is adjusted. As Vin is higher, Ids increases and the absolute value of ΔV also increases. Therefore, mobility correction according to the light emission luminance level can be performed. When Vin is constant, the absolute value of ΔV increases as the mobility μ of the driving transistor 3B increases. In other words, since the negative feedback amount ΔV increases as the mobility μ increases, it is possible to remove variations in the mobility μ for each pixel.

最後に発光期間(G)になると、図4Gに示すように、走査線WSL101が低電位側に遷移し、サンプリング用トランジスタ3Aはオフ状態となる。これにより駆動用トランジスタ3Bのゲートgは信号線DTL101から切り離される。同時にドレイン電流Idsが発光素子3Dを流れ始める。これにより発光素子3Dのアノード電位は駆動電流Idsに応じて上昇する。発光素子3Dのアノード電位の上昇は、即ち駆動用トランジスタ3Bのソース電位Vsの上昇に他ならない。駆動用トランジスタ3Bのソース電位Vsが上昇すると、保持容量3Cのブートストラップ動作により、駆動用トランジスタ3Bのゲート電位Vgも連動して上昇する。ゲート電位Vgの上昇量はソース電位Vsの上昇量に等しくなる。故に、発光期間中駆動用トランジスタ3Bのゲート‐ソース間電圧VgsはVin+Vth−ΔVで一定に保持される。   Finally, in the light emission period (G), as shown in FIG. 4G, the scanning line WSL101 transitions to the low potential side, and the sampling transistor 3A is turned off. As a result, the gate g of the driving transistor 3B is disconnected from the signal line DTL101. At the same time, the drain current Ids starts to flow through the light emitting element 3D. As a result, the anode potential of the light emitting element 3D rises according to the drive current Ids. The increase in the anode potential of the light emitting element 3D is nothing but the increase in the source potential Vs of the driving transistor 3B. When the source potential Vs of the driving transistor 3B rises, the gate potential Vg of the driving transistor 3B also rises in conjunction with the bootstrap operation of the storage capacitor 3C. The increase amount of the gate potential Vg is equal to the increase amount of the source potential Vs. Therefore, the gate-source voltage Vgs of the driving transistor 3B is kept constant at Vin + Vth−ΔV during the light emission period.

図5は、駆動用トランジスタの電流電圧特性を示すグラフである。特に駆動用トランジスタが飽和領域で動作しているときのドレイン‐ソース間電流Idsは、Ids=(1/2)・μ・(W/L)・Cox・(Vgs−Vth)で表される。ここでμは移動度を示し、Wはゲート幅を表し、Lはゲート長を表し、Coxは単位面積あたりのゲート酸化膜容量を示す。このトランジスタ特性式から明らかなように、閾電圧Vthが変動すると、Vgsが一定であってもドレイン‐ソース間電流Idsが変動する。ここで本発明にかかる画素は、前述したように発光時のゲート‐ソース間電圧VgsがVin+Vth−ΔVで表されるため、これを上述のトランジスタ特性式に代入すると、ドレイン‐ソース間電流Idsは、Ids=(1/2)・μ・(W/L)・Cox・(Vin−ΔV)で表されることになり、閾電圧Vthに依存しない。結果として、閾電圧Vthが製造プロセスにより変動しても、ドレイン‐ソース間電流Idsは変動せず、有機ELデバイスの発光輝度も変動しない。 FIG. 5 is a graph showing the current-voltage characteristics of the driving transistor. In particular, the drain-source current Ids when the driving transistor operates in the saturation region is expressed by Ids = (1/2) · μ · (W / L) · Cox · (Vgs−Vth) 2. . Here, μ represents mobility, W represents gate width, L represents gate length, and Cox represents gate oxide film capacitance per unit area. As is clear from this transistor characteristic equation, when the threshold voltage Vth varies, the drain-source current Ids varies even if Vgs is constant. Here, in the pixel according to the present invention, the gate-source voltage Vgs at the time of light emission is expressed by Vin + Vth−ΔV as described above. Therefore, when this is substituted into the above transistor characteristic equation, the drain-source current Ids is Ids = (1/2) · μ · (W / L) · Cox · (Vin−ΔV) 2 , and does not depend on the threshold voltage Vth. As a result, even if the threshold voltage Vth varies depending on the manufacturing process, the drain-source current Ids does not vary, and the light emission luminance of the organic EL device does not vary.

何ら対策を施さないと、図5に示すように閾電圧がVthのときVgsに対応する駆動電流がIdsとなるのに対し、閾電圧Vth´のとき同じゲート電圧Vgsに対応する駆動電流Ids´はIdsと異なってしまう。   If no measures are taken, the drive current corresponding to Vgs becomes Ids when the threshold voltage is Vth as shown in FIG. 5, whereas the drive current Ids ′ corresponding to the same gate voltage Vgs when the threshold voltage is Vth ′. Is different from Ids.

図6Aは同じく駆動用トランジスタの電流電圧特性を示すグラフである。移動度がμとμ´で異なる2個の駆動用トランジスタについて、それぞれ特性カーブを挙げてある。グラフから明らかなように、移動度がμとμ´で異なると、一定のVgsであってもドレイン‐ソース間電流がIdsとIds´のようになり、変動してしまう。   FIG. 6A is a graph showing the current-voltage characteristics of the driving transistor. Characteristic curves are given for two driving transistors having different mobility in μ and μ ′. As is apparent from the graph, when the mobility is different between μ and μ ′, the drain-source current becomes Ids and Ids ′ and fluctuates even at a constant Vgs.

図6Bは、映像信号電位のサンプリング時及び移動度補正時における画素の動作を説明するもので、理解を容易にするため発光素子3Dの寄生容量3Iも表してある。映像信号電位のサンプリング時、サンプリング用トランジスタ3Aはオン状態であるため駆動用トランジスタ3Bのゲート電位Vgは映像信号電位Vinとなり、駆動用トランジスタ3Bのゲート‐ソース間電圧VgsはVin+Vthになる。このとき駆動用トランジスタ3Bはオン状態となり、さらに発光素子3Dはカットオフ状態であるため、ドレイン‐ソース間電流Idsが発光素子容量3Iに流れ込む。ドレイン‐ソース間電流Idsが発光素子容量3Iに流れ込むと、発光素子容量3Iは充電を開始し、発光素子3Dのアノード(したがって駆動用トランジスタ3Bのソース電位Vs)が上昇を開始する。駆動用トランジスタ3Bのソース電位VsがΔVだけ上昇すると、駆動用トランジスタ3Bのゲート‐ソース間電圧VgsはΔVだけ減少する。これが負帰還による移動度補正動作であり、ゲート‐ソース間電圧Vgsの減少量ΔVは、ΔV=Ids・Cel/tで決定され、ΔVが移動度補正のためのパラメータとなる。ここでCelは発光素子容量3Iの容量値を示し、tは移動度補正期間(第1のタイミングと第2のタイミングとの間の期間)を示す。   FIG. 6B illustrates the operation of the pixel at the time of sampling the video signal potential and correcting the mobility, and also shows the parasitic capacitance 3I of the light emitting element 3D for easy understanding. At the time of sampling the video signal potential, the sampling transistor 3A is in an on state, so that the gate potential Vg of the driving transistor 3B becomes the video signal potential Vin, and the gate-source voltage Vgs of the driving transistor 3B becomes Vin + Vth. At this time, the driving transistor 3B is turned on, and the light emitting element 3D is cut off, so that the drain-source current Ids flows into the light emitting element capacitor 3I. When the drain-source current Ids flows into the light emitting element capacitor 3I, the light emitting element capacitor 3I starts to be charged, and the anode of the light emitting element 3D (therefore, the source potential Vs of the driving transistor 3B) starts to rise. When the source potential Vs of the driving transistor 3B increases by ΔV, the gate-source voltage Vgs of the driving transistor 3B decreases by ΔV. This is a mobility correction operation by negative feedback, and the reduction amount ΔV of the gate-source voltage Vgs is determined by ΔV = Ids · Cel / t, and ΔV is a parameter for mobility correction. Here, Cel represents the capacitance value of the light emitting element capacitance 3I, and t represents a mobility correction period (a period between the first timing and the second timing).

図6Cは、移動度補正期間tを決定する画素回路の動作タイミングを説明する模式図である。図示の例は、映像線信号電位の立ち上がりに傾斜をつけることで、移動度補正期間tを映像線信号電位に自動的に追従させて、その最適化を図っている。図示する様に、移動度補正期間tは走査線WS101と映像信号線DTL101の位相差で決定され、さらに映像信号線DTL101の電位によっても決定される。移動度補正パラメータΔVはΔV=Ids・Cel/tである。この式から明らかなように、駆動用トランジスタ3Bのドレイン‐ソース間電流Idsが大きいほど、移動度補正パラメータΔVは大きくなる。逆に駆動用トランジスタ3Bのドレイン‐ソース間電流Idsが小さいとき、移動度補正パラメータΔVは小さくなる。この様に、移動度補正パラメータΔVはドレイン‐ソース間電流Idsに応じて決まる。その際移動度補正期間tは必ずしも一定である必要はなく、逆にIdsに応じて調整することが好ましい場合がある。例えばIdsが大きい場合移動度補正期間tは短めにし、逆にIdsが小さくなると、移動度補正期間tは長めに設定することが良い。そこで、図6Cに示した実施例では、少なくとも映像信号線電位の立ち上がりに傾斜をつけることで、映像信号線DTL101の電位が高いとき(Idsが大きいとき)補正期間tが短くなり、映像信号線DTL101の電位が低いとき(Idsが小さいとき)補正期間tは長くなるように、自動的に調整している。   FIG. 6C is a schematic diagram illustrating the operation timing of the pixel circuit that determines the mobility correction period t. In the illustrated example, the mobility correction period t automatically follows the video line signal potential by providing a slope to the rise of the video line signal potential to optimize the video line signal potential. As shown in the figure, the mobility correction period t is determined by the phase difference between the scanning line WS101 and the video signal line DTL101, and is further determined by the potential of the video signal line DTL101. The mobility correction parameter ΔV is ΔV = Ids · Cel / t. As is apparent from this equation, the mobility correction parameter ΔV increases as the drain-source current Ids of the driving transistor 3B increases. Conversely, when the drain-source current Ids of the driving transistor 3B is small, the mobility correction parameter ΔV is small. Thus, the mobility correction parameter ΔV is determined according to the drain-source current Ids. In this case, the mobility correction period t does not necessarily have to be constant, and on the contrary, it may be preferable to adjust the mobility correction period t according to Ids. For example, when Ids is large, the mobility correction period t should be short, and conversely, when Ids is small, the mobility correction period t should be set long. Therefore, in the embodiment shown in FIG. 6C, the correction period t is shortened when the potential of the video signal line DTL101 is high (when Ids is large) by tilting at least the rise of the video signal line potential, and the video signal line When the potential of the DTL 101 is low (when Ids is small), the correction period t is automatically adjusted to be long.

図6Dは、移動度補正時における駆動用トランジスタ3Bの動作点を説明するグラフである。製造プロセスにおける移動度μ,μ´のバラつきに対して、上述した移動度補正をかけることによって最適の補正パラメータΔV及びΔV´が決定され、駆動用トランジスタ3Bのドレイン‐ソース間電流Ids及びIds´が決定される。仮に移動度補正をかけないと、ゲート‐ソース間電圧Vgsに対して、移動度がμとμ´で異なると、これに応じてドレイン‐ソース間電流もIds0とIds0´で違ってしまう。これに対処するため移動度μ及びμ´に対してそれぞれ適切な補正ΔV及びΔV´をかけることで、ドレイン‐ソース間電流がIds及びIds´となり、同レベルとなる。図6Dのグラフから明らかなように、移動度μが高いとき補正量ΔVが大きくなる一方、移動度μ´が小さいとき補正量ΔV´も小さくなるように、負帰還をかけている。   FIG. 6D is a graph for explaining an operating point of the driving transistor 3B at the time of mobility correction. The optimum correction parameters ΔV and ΔV ′ are determined by performing the above-described mobility correction for the variations in the mobility μ and μ ′ in the manufacturing process, and the drain-source currents Ids and Ids ′ of the driving transistor 3B are determined. Is determined. If the mobility correction is not applied, if the mobility differs between μ and μ ′ with respect to the gate-source voltage Vgs, the drain-source current also differs depending on this between Ids0 and Ids0 ′. In order to cope with this, by applying appropriate corrections ΔV and ΔV ′ to the mobility μ and μ ′, respectively, the drain-source current becomes Ids and Ids ′, which are at the same level. As is apparent from the graph of FIG. 6D, negative feedback is applied so that the correction amount ΔV increases when the mobility μ is high, while the correction amount ΔV ′ also decreases when the mobility μ ′ is small.

図7Aは、有機ELデバイスで構成される発光素子3Dの電流‐電圧特性を示すグラフである。発光素子3Dに電流Ielが流れるとき、アノード‐カソード間電圧Velは一意的に決定される。図4Gに示したように発光期間中走査線WSL101が低電位側に遷移し、サンプリング用トランジスタ3Aがオフ状態になると、発光素子3Dのアノードは駆動用トランジスタ3Bのドレイン‐ソース間電流Idsで決定されるアノード‐カソード間電圧Vel分だけ上昇する。   FIG. 7A is a graph showing current-voltage characteristics of a light-emitting element 3D composed of an organic EL device. When the current Iel flows through the light emitting element 3D, the anode-cathode voltage Vel is uniquely determined. As shown in FIG. 4G, when the scanning line WSL101 transits to the low potential side during the light emission period and the sampling transistor 3A is turned off, the anode of the light emitting element 3D is determined by the drain-source current Ids of the driving transistor 3B. The anode-cathode voltage Vel increases.

図7Bは、発光素子3Dのアノード電位上昇時における駆動用トランジスタ3Bのゲート電位Vgとソース電位Vsの電位変動を示すグラフである。発光素子3Dのアノード上昇電圧がVelのとき、駆動用トランジスタ3BのソースもVelだけ上昇し、保持容量3Cのブートストラップ動作により駆動用トランジスタ3BのゲートもVel分上昇する。この為、ブートストラップ前に保持された駆動用トランジスタ3Bのゲート‐ソース間電圧Vgs=Vin+Vth−ΔVは、ブートストラップ後もそのまま保持される。また発光素子3Dの経時劣化によりそのアノード電位が変動しても、駆動用トランジスタ3Bのゲート‐ソース間電圧は常にVin+Vth−ΔVで一定に保持される。   FIG. 7B is a graph showing potential fluctuations of the gate potential Vg and the source potential Vs of the driving transistor 3B when the anode potential of the light emitting element 3D is increased. When the anode rising voltage of the light emitting element 3D is Vel, the source of the driving transistor 3B is also raised by Vel, and the gate of the driving transistor 3B is also raised by Vel by the bootstrap operation of the storage capacitor 3C. For this reason, the gate-source voltage Vgs = Vin + Vth−ΔV of the driving transistor 3B held before the bootstrap is held as it is after the bootstrap. Even if the anode potential fluctuates due to deterioration with time of the light emitting element 3D, the gate-source voltage of the driving transistor 3B is always kept constant at Vin + Vth−ΔV.

図7Cは、図3Bで説明した本発明の画素構成に、寄生容量7A及び7Bを付加した回路図である。この寄生容量7A及び7Bは駆動用トランジスタ3のゲートgに寄生している。前述したブートストラップ動作能力は保持容量の容量値をCs、寄生容量7A,7Bの容量値をそれぞれCw,Cpとした場合に、Cs/(Cs+Cw+Cp)で表され、これが1に近いほどブートストラップ動作能力が高い。つまり発光素子3Dの経時劣化に対する補正能力が高いことを示している。本発明では駆動用トランジスタ3Bのゲートgに接続する素子数を最小限にとどめており、Cpをほとんど無視できる。したがってブートストラップ動作能力はCs/(Cs+Cw)で表され、限りなく1に近いことになり、発光素子3Dの経時劣化に対する補正能力が高いことを示している。   FIG. 7C is a circuit diagram in which parasitic capacitances 7A and 7B are added to the pixel configuration of the present invention described in FIG. 3B. The parasitic capacitances 7A and 7B are parasitic on the gate g of the driving transistor 3. The bootstrap operation capability described above is expressed as Cs / (Cs + Cw + Cp) when the capacitance value of the storage capacitor is Cs and the capacitance values of the parasitic capacitors 7A and 7B are Cw and Cp, respectively. High ability. That is, the light-emitting element 3D has a high correction capability for deterioration with time. In the present invention, the number of elements connected to the gate g of the driving transistor 3B is minimized, and Cp can be almost ignored. Therefore, the bootstrap operation capability is represented by Cs / (Cs + Cw), which is as close to 1 as possible, indicating that the correction capability against the deterioration with time of the light emitting element 3D is high.

図8は、本発明にかかる表示装置の他の実施形態を示す模式的な回路図である。理解を容易にするため、図3Bに示した先の実施形態と対応する部分には対応する参照番号を付してある。異なる点は、図3Bに示した実施形態がNチャネル型のトランジスタを用いて画素回路を構成しているのに対し、図8の実施形態はPチャネル型のトランジスタを用いて画素回路を構成していることである。図8の画素回路も、図3Bに示した画素回路とまったく同様に閾電圧補正動作、移動度補正動作及びブートストラップ動作を行うことが出来る。   FIG. 8 is a schematic circuit diagram showing another embodiment of the display device according to the present invention. For ease of understanding, parts corresponding to those of the previous embodiment shown in FIG. 3B are given corresponding reference numerals. The difference is that the embodiment shown in FIG. 3B uses an N-channel transistor to form a pixel circuit, whereas the embodiment shown in FIG. 8 uses a P-channel transistor to form a pixel circuit. It is that. The pixel circuit in FIG. 8 can perform the threshold voltage correction operation, the mobility correction operation, and the bootstrap operation in exactly the same manner as the pixel circuit shown in FIG. 3B.

一般的な画素構成を示す回路図である。It is a circuit diagram which shows a general pixel structure. 図1に示した画素回路の動作説明に供するタイミングチャートである。2 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 1. 本発明にかかる表示装置の全体構成を示すブロック図である。1 is a block diagram showing an overall configuration of a display device according to the present invention. 本発明にかかる表示装置の実施形態を示す回路図である。It is a circuit diagram which shows embodiment of the display apparatus concerning this invention. 図3Bに示した実施形態の動作説明に供するタイミングチャートである。It is a timing chart with which it uses for operation | movement description of embodiment shown to FIG. 3B. 同じく動作説明に供する回路図である。It is a circuit diagram similarly used for operation | movement description. 同じく動作説明に供する回路図である。It is a circuit diagram similarly used for operation | movement description. 同じく動作説明に供する回路図である。It is a circuit diagram similarly used for operation | movement description. 同じく動作説明に供する回路図である。It is a circuit diagram similarly used for operation | movement description. 同じく動作説明に供する回路図である。It is a circuit diagram similarly used for operation | movement description. 同じく動作説明に供する回路図である。It is a circuit diagram similarly used for operation | movement description. 駆動用トランジスタの電流‐電圧特性を示すグラフである。It is a graph which shows the current-voltage characteristic of a driving transistor. 同じく駆動用トランジスタの電流‐電圧特性を示すグラフである。It is a graph which similarly shows the current-voltage characteristic of a driving transistor. 本発明にかかる表示装置の動作説明に供する回路図である。It is a circuit diagram with which it uses for operation | movement description of the display apparatus concerning this invention. 同じく動作説明に供する波形図である。It is a wave form diagram similarly provided for operation | movement description. 同じく動作説明に供する電流‐電圧特性グラフである。It is a current-voltage characteristic graph similarly used for operation explanation. 発光素子の電流‐電圧特性を示すグラフである。It is a graph which shows the current-voltage characteristic of a light emitting element. 駆動用トランジスタのブートストラップ動作を示す波形図である。It is a wave form diagram which shows the bootstrap operation | movement of the transistor for a drive. 本発明にかかる表示装置の動作説明に供する回路図である。It is a circuit diagram with which it uses for operation | movement description of the display apparatus concerning this invention. 本発明にかかる表示装置の他の実施形態を示す回路図である。It is a circuit diagram which shows other embodiment of the display apparatus concerning this invention.

符号の説明Explanation of symbols

100…表示装置、101…画素、102…画素アレイ部、103…水平セレクタ、104…ライトスキャナ、105…電源スキャナ、3A…サンプリング用トランジスタ、3B…駆動用トランジスタ、3C…保持容量、3D…発光素子 DESCRIPTION OF SYMBOLS 100 ... Display apparatus, 101 ... Pixel, 102 ... Pixel array part, 103 ... Horizontal selector, 104 ... Write scanner, 105 ... Power supply scanner, 3A ... Sampling transistor, 3B ... Drive transistor, 3C ... Retention capacity, 3D ... Light emission element

Claims (12)

発光素子と、サンプリング用トランジスタと、駆動用トランジスタと、保持容量とを含み、
前記サンプリング用トランジスタは、そのゲートが走査線に接続し、そのソース及びドレインの一方が信号線に接続し、他方が該駆動用トランジスタのゲートに接続し、
前記駆動用トランジスタは、そのソース及びドレインの一方が該発光素子に接続し、他方が電源線に接続し、該電源線は第1電位と第2電位とで切り替わり、
前記保持容量は、該駆動用トランジスタのソースおよびドレインの一方とゲートの間に接続しており、
前記駆動用トランジスタは、該保持容量に保持された信号電位に応じて駆動電流を該発光素子に流し、
前記サンプリング用トランジスタが導通している間であって、該第2電位と異なる基準電位が該信号線に供給されている間に、電源線の電位は第2電位から第1電位になり、
前記サンプリング用トランジスタが導通している間であって、信号電位が該信号線に供給されている間に、信号電位が該保持容量に保持される画素回路。
Including a light emitting element, a sampling transistor, a driving transistor, and a storage capacitor;
The sampling transistor has its gate connected to the scanning line, one of its source and drain connected to the signal line, and the other connected to the gate of the driving transistor,
The driving transistor has one of a source and a drain connected to the light emitting element, the other connected to a power supply line, and the power supply line is switched between a first potential and a second potential,
The storage capacitor is connected between one of the source and drain of the driving transistor and the gate,
The driving transistor causes a driving current to flow through the light emitting element in accordance with a signal potential held in the holding capacitor,
While the sampling transistor is conducting and a reference potential different from the second potential is supplied to the signal line, the potential of the power supply line changes from the second potential to the first potential,
A pixel circuit in which the signal potential is held in the holding capacitor while the sampling transistor is conductive and the signal potential is supplied to the signal line.
前記サンプリング用トランジスタが導通している間であって、該第1電位と該第2電位の間にある基準電位が該信号線に供給されている間に、電源線の電位は該第2電位から該第1電位になる請求項1記載の画素回路。   While the sampling transistor is conducting and the reference potential between the first potential and the second potential is supplied to the signal line, the potential of the power supply line is the second potential. The pixel circuit according to claim 1, wherein the first potential becomes the first potential. 前記保持容量の一端に該基準電位を書込み他端に該第2電位を書込み、その後前記サンプリング用トランジスタが導通している間であって該基準電位が該信号線に供給されている間に、電源線の電位を該第2電位から該第1電位にする請求項1記載の画素回路。   The reference potential is written to one end of the storage capacitor, the second potential is written to the other end, and the reference potential is supplied to the signal line while the sampling transistor is conductive. The pixel circuit according to claim 1, wherein the potential of the power supply line is changed from the second potential to the first potential. 前記保持容量の一端に該基準電位を書込み他端に該第2電位を書込んで両端の電位差を前記駆動用トランジスタの閾電圧より大きく設定し、その後前記サンプリング用トランジスタが導通している間であって該基準電位が該信号線に供給されている間に電源線の電位を該第2電位から該第1電位にして、該保持容量の他端の電位を該保持容量の一端の電位に向かって変化させる請求項3記載の画素回路。   While the reference potential is written to one end of the storage capacitor and the second potential is written to the other end, the potential difference between the two ends is set to be larger than the threshold voltage of the driving transistor, and then the sampling transistor is turned on. While the reference potential is supplied to the signal line, the potential of the power supply line is changed from the second potential to the first potential, and the potential of the other end of the storage capacitor is changed to the potential of one end of the storage capacitor. The pixel circuit according to claim 3, wherein the pixel circuit is changed toward the front. 該走査線は線順次走査され、前記電源線も該線順次走査に合わせて走査して順次電源線の電位が該第2電位から該第1電位に切り替わる請求項1記載の画素回路。   2. The pixel circuit according to claim 1, wherein the scanning lines are line-sequentially scanned, the power supply lines are also scanned in accordance with the line-sequential scanning, and the potential of the power supply lines is sequentially switched from the second potential to the first potential. 発光素子と、サンプリング用トランジスタと、駆動用トランジスタと、保持容量とを含み、
前記サンプリング用トランジスタは、そのゲートが走査線に接続し、そのソース及びドレインの一方が信号線に接続し、他方が該駆動用トランジスタのゲートに接続し、
前記駆動用トランジスタは、そのソース及びドレインの一方が該発光素子に接続し、他方が電源線に接続し、該電源線は第1電位と第2電位とで切り替わり、
前記保持容量は、該駆動用トランジスタのソースおよびドレインの一方とゲートの間に接続し、
前記駆動用トランジスタは、該保持容量に保持された信号電位に応じて駆動電流を該発光素子に流し、
前記サンプリング用トランジスタが導通している間であって、該第2電位と異なる基準電位が該信号線に供給されている間に、電源線の電位を該第2電位から該第1電位に切り換え、
前記サンプリング用トランジスタが導通している間であって、信号電位が該信号線に供給されている間に、信号電位を該保持容量に保持する画素回路の駆動方法。
Including a light emitting element, a sampling transistor, a driving transistor, and a storage capacitor;
The sampling transistor has its gate connected to the scanning line, one of its source and drain connected to the signal line, and the other connected to the gate of the driving transistor,
The driving transistor has one of a source and a drain connected to the light emitting element, the other connected to a power supply line, and the power supply line is switched between a first potential and a second potential,
The storage capacitor is connected between one of a source and a drain of the driving transistor and a gate,
The driving transistor causes a driving current to flow through the light emitting element in accordance with a signal potential held in the holding capacitor,
While the sampling transistor is conducting and a reference potential different from the second potential is supplied to the signal line, the potential of the power supply line is switched from the second potential to the first potential. ,
A driving method of a pixel circuit in which a signal potential is held in the holding capacitor while the sampling transistor is conductive and while the signal potential is supplied to the signal line.
画素アレイ部とこれを駆動する駆動部とからなり、
前記画素アレイ部は、行状の走査線と、列状の信号線と、両者が交差する部分に配された行列状の画素とを備え、
前記画素は、発光素子と、サンプリング用トランジスタと、駆動用トランジスタと、保持容量とを含み、
前記サンプリング用トランジスタは、そのゲートが該走査線に接続し、そのソース及びドレインの一方が該信号線に接続し、他方が該駆動用トランジスタのゲートに接続し、
前記駆動用トランジスタは、そのソース及びドレインの一方が該発光素子に接続し、他方が該電源線に接続し、
前記保持容量は、該ソースおよびドレインの一方と該駆動用トランジスタのゲートの間に接続しており、
前記駆動部は、基準電位又は信号電位を供給する映像信号供給回路と、該電源線に第1電位と第2電位を供給する電源スキャナとを備え、
前記駆動用トランジスタは、該電源線から電流の供給を受け該保持容量に保持された信号電位に応じて駆動電流を該発光素子に流し、
前記サンプリング用トランジスタが導通している間であって、該第2電位と異なる基準電位が該信号線に供給されている間に、該電源線の電位は該第2電位から該第1電位になり、
前記サンプリング用トランジスタが導通している間であって、該信号電位が該信号線に供給されている間に、該信号電位が該保持容量に保持される表示装置。
It consists of a pixel array part and a drive part that drives it,
The pixel array unit includes a row-shaped scanning line, a column-shaped signal line, and a matrix-shaped pixel arranged at a portion where both intersect,
The pixel includes a light emitting element, a sampling transistor, a driving transistor, and a storage capacitor.
The sampling transistor has its gate connected to the scanning line, one of its source and drain connected to the signal line, and the other connected to the gate of the driving transistor,
The driving transistor has one of a source and a drain connected to the light emitting element, and the other connected to the power supply line,
The storage capacitor is connected between one of the source and drain and the gate of the driving transistor,
The drive unit includes a video signal supply circuit that supplies a reference potential or a signal potential, and a power supply scanner that supplies a first potential and a second potential to the power supply line,
The driving transistor receives a current supplied from the power supply line, and causes a driving current to flow to the light emitting element in accordance with a signal potential held in the holding capacitor,
While the sampling transistor is conducting and a reference potential different from the second potential is supplied to the signal line, the potential of the power supply line is changed from the second potential to the first potential. Become
A display device in which the signal potential is held in the storage capacitor while the sampling transistor is conductive and the signal potential is supplied to the signal line.
前記サンプリング用トランジスタが導通している間であって、該第1電位と該第2電位の間にある基準電位が該信号線に供給されている間に、電源線の電位は該第2電位から該第1電位になる請求項7記載の表示装置。   While the sampling transistor is conducting and the reference potential between the first potential and the second potential is supplied to the signal line, the potential of the power supply line is the second potential. The display device according to claim 7, wherein the first potential is changed to the first potential. 前記保持容量の一端に該基準電位を書込み他端に該第2電位を書込み、その後前記サンプリング用トランジスタが導通している間であって該基準電位が該信号線に供給されている間に、電源線の電位を該第2電位から該第1電位にする請求項7記載の表示装置。   The reference potential is written to one end of the storage capacitor, the second potential is written to the other end, and the reference potential is supplied to the signal line while the sampling transistor is conductive. The display device according to claim 7, wherein the potential of the power supply line is changed from the second potential to the first potential. 前記保持容量の一端に該基準電位を書込み他端に該第2電位を書込んで両端の電位差を前記駆動用トランジスタの閾電圧より大きく設定し、その後前記サンプリング用トランジスタが導通している間であって該基準電位が該信号線に供給されている間に電源線の電位を該第2電位から該第1電位にして、該保持容量の他端の電位を該保持容量の一端の電位に向かって変化させる請求項9記載の表示装置。   While the reference potential is written to one end of the storage capacitor and the second potential is written to the other end, the potential difference between the two ends is set to be larger than the threshold voltage of the driving transistor, and then the sampling transistor is turned on. While the reference potential is supplied to the signal line, the potential of the power supply line is changed from the second potential to the first potential, and the potential of the other end of the storage capacitor is changed to the potential of one end of the storage capacitor. The display device according to claim 9, wherein the display device is changed toward the display. 前記電源スキャナは、各電源線を線順次走査して、順次各電源線の電位を該第2電位から該第1電位に切り替える請求項7記載の表示装置。   The display device according to claim 7, wherein the power supply scanner scans each power supply line sequentially and sequentially switches the potential of each power supply line from the second potential to the first potential. 画素アレイ部とこれを駆動する駆動部とからなり、
前記画素アレイ部は、行状の走査線と、列状の信号線と、両者が交差する部分に配された行列状の画素とを備え、
前記画素は、発光素子と、サンプリング用トランジスタと、駆動用トランジスタと、保持容量とを含み、
前記サンプリング用トランジスタは、そのゲートが該走査線に接続し、そのソース及びドレインの一方が該信号線に接続し、他方が該駆動用トランジスタのゲートに接続し、
前記駆動用トランジスタは、そのソース及びドレインの一方が該発光素子に接続し、他方が該電源線に接続し、
前記保持容量は、該ソースおよびドレインの一方と該駆動用トランジスタのゲートの間に接続し、
前記駆動部は、基準電位又は信号電位を供給する映像信号供給回路と、該電源線に第1電位と第2電位を供給する電源スキャナとを備え、
前記駆動用トランジスタは、該電源線から電流の供給を受け該保持容量に保持された信号電位に応じて駆動電流を該発光素子に流し、
前記サンプリング用トランジスタが導通している間であって、該第2電位と異なる基準電位が該信号線に供給されている間に、該電源線の電位を該第2電位から該第1電位に切り換え、
前記サンプリング用トランジスタが導通している間であって、該信号電位が該信号線に供給されている間に、該信号電位を該保持容量に保持する表示装置の駆動方法。
It consists of a pixel array part and a drive part that drives it,
The pixel array unit includes a row-shaped scanning line, a column-shaped signal line, and a matrix-shaped pixel arranged at a portion where both intersect,
The pixel includes a light emitting element, a sampling transistor, a driving transistor, and a storage capacitor.
The sampling transistor has its gate connected to the scanning line, one of its source and drain connected to the signal line, and the other connected to the gate of the driving transistor,
The driving transistor has one of a source and a drain connected to the light emitting element, and the other connected to the power supply line,
The storage capacitor is connected between one of the source and drain and the gate of the driving transistor,
The drive unit includes a video signal supply circuit that supplies a reference potential or a signal potential, and a power supply scanner that supplies a first potential and a second potential to the power supply line,
The driving transistor receives a current supplied from the power supply line, and causes a driving current to flow to the light emitting element in accordance with a signal potential held in the holding capacitor,
While the sampling transistor is conducting and while a reference potential different from the second potential is supplied to the signal line, the potential of the power supply line is changed from the second potential to the first potential. switching,
A driving method of a display device in which the signal potential is held in the holding capacitor while the sampling transistor is conductive and the signal potential is supplied to the signal line.
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