JP2009163275A - Pixel circuit, driving method for pixel circuit, display device, and driving method for display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make effective and simple a pixel circuit provided with a threshold voltage correction function. <P>SOLUTION: A sampling transistor Tr1 samples a picture signal supplied from a signal line SL by conducting electricity in accordance with a control signal supplied from a scanning line WS during a period of horizontal scanning into pixel capacity Cs, which applies input voltage Vgs to a gate G of a drive transistor Trd in accordance with the sampled picture signal. The drive transistor Trd supplies output current corresponding to the input voltage Vgs to a light emitting element EL. The output current has dependency on threshold voltage Vth of the drive transistor Trd. This pixel circuit includes correction means Tr3, Tr4 operating in a part of the period of horizontal scanning, detecting the threshold voltage Vth of the drive transistor Trd, and writing it into the pixel capacity Cs to cancel the dependency of the output current on the threshold voltage Vth. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a pixel circuit that current-drives a light emitting element arranged for each pixel. More specifically, the present invention relates to a pixel circuit applied to a so-called active matrix display device in which an amount of current supplied to a light emitting element such as an organic EL is controlled by an insulated gate field effect transistor provided in each pixel circuit.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

  In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.

JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  A conventional pixel circuit is arranged at a portion where a row scanning line for supplying a control signal and a column signal line for supplying a video signal intersect, and includes at least a sampling transistor, a capacitor, a drive transistor, and a light emitting element. . The sampling transistor conducts in response to the control signal supplied from the scanning line and samples the video signal supplied from the signal line. The capacitor unit holds an input voltage corresponding to the sampled video signal. The drive transistor supplies an output current during a predetermined light emission period in accordance with the input voltage held in the capacitor unit. In general, the output current depends on the carrier mobility and threshold voltage of the channel region of the drive transistor. The light emitting element emits light with luminance according to the video signal by the output current supplied from the drive transistor.

  The drive transistor receives the input voltage held in the capacitor portion at the gate, causes an output current to flow between the source and the drain, and energizes the light emitting element. In general, the light emission luminance of a light emitting element is proportional to the amount of current applied. Further, the output current supply amount of the drive transistor is controlled by the gate voltage, that is, the input voltage written in the capacitor. The conventional pixel circuit controls the amount of current supplied to the light emitting element by changing the input voltage applied to the gate of the drive transistor in accordance with the input video signal.

Here, the operating characteristic of the drive transistor is expressed by the following Equation 1.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ² Formula 1
In the transistor characteristic formula 1, Ids represents a drain current flowing between the source and the drain, and is an output current supplied to the light emitting element in the pixel circuit. Vgs represents a gate voltage applied to the gate with reference to the source, and is the above-described input voltage in the pixel circuit. Vth is the threshold voltage of the transistor. Μ represents the mobility of the semiconductor thin film constituting the channel of the transistor. In addition, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from the transistor characteristic equation 1, when the thin film transistor operates in the saturation region, if the gate voltage Vgs increases beyond the threshold voltage Vth, the thin film transistor is turned on and the drain current Ids flows. In principle, as shown in the above transistor characteristic equation 1, if the gate voltage Vgs is constant, the same amount of drain current Ids is always supplied to the light emitting element. Therefore, if video signals of the same level are supplied to all the pixels constituting the screen, all the pixels should emit light with the same luminance, and the uniformity of the screen should be obtained.

  However, in reality, thin film transistors (TFTs) composed of semiconductor thin films such as polysilicon have variations in individual device characteristics. In particular, the threshold voltage Vth is not constant and varies from pixel to pixel. As apparent from the transistor characteristic equation 1 described above, if the threshold voltage Vth of each drive transistor varies, even if the gate voltage Vgs is constant, the drain current Ids varies and the luminance varies from pixel to pixel. , Damage the screen uniformity. Conventionally, a pixel circuit incorporating a function for canceling variations in threshold voltages of drive transistors has been developed, and is disclosed in, for example, Patent Document 3 described above.

  However, a conventional pixel circuit incorporating a function for canceling variations in threshold voltage (threshold voltage correction function) has a complicated configuration, which has been an obstacle to pixel miniaturization or high definition. In addition, the conventional pixel circuit incorporating the threshold voltage correction function is not efficient and causes complicated circuit design. In addition, a conventional pixel circuit having a threshold voltage correction function has a relatively large number of constituent elements, which causes a decrease in yield.

  SUMMARY OF THE INVENTION In view of the above-described problems of the prior art, the present invention aims to improve the efficiency and simplification of a pixel circuit having a threshold voltage correction function, thereby achieving higher definition and improved yield of a display device. And In order to achieve this purpose, the following measures were taken. That is, according to the present invention, at least a sampling transistor, a pixel capacitor connected to the sampling transistor, and a pixel capacitor connected to the row scanning line that supplies a control signal and a column signal line that supplies a video signal are connected. And a light emitting element connected to the sampling transistor. The sampling transistor is turned on in response to a control signal supplied from the scanning line during a horizontal scanning period assigned to the scanning line and is supplied from the signal line. The captured video signal is sampled into the pixel capacitor, and the pixel capacitor applies an input voltage to the gate of the drive transistor in accordance with the sampled video signal, and the drive transistor receives the input during a predetermined light emission period. An output current corresponding to the voltage is supplied to the light emitting element, and the output current is compared with a threshold voltage of the channel region of the drive transistor. In the pixel circuit that emits light with a luminance corresponding to the video signal by the output current supplied from the drive transistor, the light emitting element is arranged horizontally to cancel the dependency of the output current on the threshold voltage. It is characterized by comprising correction means that operates during a part of the scanning period, detects the threshold voltage of the drive transistor, and writes it in the pixel capacitor.

  Preferably, the correction unit operates in a state in which the sampling transistor is turned on in a horizontal scanning period and one end of the pixel capacitor is held at a constant potential by the signal line, and the other end of the pixel capacitor The pixel capacitor is charged until the potential difference reaches the threshold voltage. The correction means detects the threshold voltage of the drive transistor in the first half of the horizontal scanning period and writes it to the pixel capacitor, while the sampling transistor is a video signal supplied from the signal line in the second half of the horizontal scanning period. Is applied to the pixel capacitor, and the pixel capacitor applies an input voltage obtained by adding the written threshold voltage to the sampled video signal between the gate and the source of the drive transistor, thereby generating an output current. Cancels the dependence of the threshold voltage on the threshold voltage. Further, the correction means is conducted before the horizontal scanning period, and is conducted during the horizontal scanning period, and a first switching transistor that is set so that a potential difference between both ends of the pixel capacitance exceeds the threshold voltage, And a second switching transistor that charges the pixel capacitor until the potential difference across the pixel capacitor reaches the threshold voltage. The first switching transistor is turned on in response to a control signal supplied from the other scanning line during a previous horizontal scanning period assigned to the other scanning line located before the scanning line. Thus, the potential difference between both ends of the pixel capacitor is set to exceed the threshold voltage. The first switching transistor is turned on in response to a control signal supplied from the other scanning line in the immediately preceding horizontal scanning period assigned to the other scanning line located immediately before the scanning line. Thus, the potential difference between both ends of the pixel capacitor is set to exceed the threshold voltage. The sampling transistor samples the video signal supplied from the signal line into the pixel capacitor during a signal supply period in which the signal line is at the potential of the video signal within a horizontal scanning period, while the correction means The threshold voltage of the drive transistor is detected and written to the pixel capacitor during a signal fixing period in which the signal line is at a constant potential within the scanning period. The correction means also operates in a signal fixing period within a horizontal scanning period assigned to another scanning line, and charges the pixel capacitor to the threshold voltage in a time division manner in each signal fixing period. The signal fixing period is a horizontal blanking period that divides each horizontal scanning period sequentially assigned to each scanning line, and the correction means sets the pixel capacity in a time-division manner in each horizontal blanking period. Charge until. When the correction means charges the pixel capacitor in each signal fixed period, the pixel transistor is electrically disconnected from the signal line by closing the sampling transistor before the signal line is switched from a constant potential to the potential of the video signal. . The drive transistor has a dependency on the carrier mobility in addition to the threshold voltage of the channel region, and the correction means cancels the dependency of the output current on the carrier mobility. It operates in a part of the horizontal scanning period, and an output current is taken out from the drive transistor in a state where the video signal is sampled, and this is negatively fed back to the pixel capacitor to correct the input voltage.

  The present invention is also arranged at a portion where a row-shaped scanning line for supplying a control signal and a column-shaped signal line for supplying a video signal intersect, and at least a sampling transistor, a pixel capacitor connected to the sampling transistor, and a connection to the sampling capacitor. And a light emitting element connected to the sampling transistor. The sampling transistor is turned on in response to a control signal supplied from the scanning line during a horizontal scanning period assigned to the scanning line and is supplied from the signal line. The captured video signal is sampled into the pixel capacitor, and the pixel capacitor applies an input voltage to the gate of the drive transistor in accordance with the sampled video signal, and the drive transistor receives the input during a predetermined light emission period. An output current corresponding to a voltage is supplied to the light emitting element, and the output current is compared with a threshold voltage of a channel region of the drive transistor. In the pixel circuit that emits light with a luminance corresponding to the video signal by the output current supplied from the drive transistor, the light emitting element is configured to cancel the dependence of the output current on the threshold voltage. Compensating means for detecting the threshold voltage of the drive transistor and writing it in the pixel capacitance, the correcting means includes a first switching transistor and a second switching transistor, and the first switching transistor , And conducts in accordance with a control signal supplied from the other scanning line during the previous horizontal scanning period assigned to the other scanning line located before the scanning line, thereby The potential difference is set so as to exceed a threshold voltage, and the second switching transistor is turned on during the horizontal scanning period so that the potential difference between both ends of the pixel capacitance is Characterized by charging the pixel capacitance until the voltage.

  Preferably, the first switching transistor is turned on in response to a control signal supplied from the other scan line in the immediately preceding horizontal scan period assigned to the other scan line located immediately before the scan line. Thus, the potential difference between both ends of the pixel capacitor is set to exceed the threshold voltage.

  The present invention further includes a row-shaped scanning line for supplying a control signal and a column-shaped signal line for supplying a video signal, and at least a sampling transistor, a pixel capacitor connected to the sampling transistor, and a connection to the sampling transistor. And a light emitting element connected to the sampling transistor. The sampling transistor is turned on in response to a control signal supplied from the scanning line during a horizontal scanning period assigned to the scanning line and is supplied from the signal line. The captured video signal is sampled into the pixel capacitor, and the pixel capacitor applies an input voltage to the gate of the drive transistor in accordance with the sampled video signal, and the drive transistor receives the input during a predetermined light emission period. An output current corresponding to the voltage is supplied to the light emitting element, and the output current is compared with a threshold voltage of the channel region of the drive transistor. In order to cancel the dependency of the output current on the threshold voltage in a pixel circuit that emits light with luminance corresponding to the video signal by the output current supplied from the drive transistor, Prior to the sampling of the video signal, a correction means for detecting a threshold voltage of the drive transistor and writing it to the pixel capacitance is provided, and the correction means includes a plurality of horizontal scans assigned to a plurality of scanning lines. It operates within a period, and the pixel capacitor is charged to the threshold voltage in a time division manner.

  Preferably, the sampling transistor samples the video signal supplied from the signal line into the pixel capacitor during a signal supply period in which the signal line becomes a video signal potential within the horizontal scanning period assigned to the scanning line. On the other hand, the correction means detects the threshold voltage of the drive transistor in a time-sharing manner in each signal fixed period in which the signal line becomes a constant potential within each horizontal scanning period assigned to the plurality of scanning lines. The pixel capacitor is charged to the threshold voltage. The signal fixing period is a horizontal blanking period that divides each horizontal scanning period sequentially assigned to each scanning line, and the correction means sets the pixel capacity in a time-division manner in each horizontal blanking period. Charge until. When the correction means charges the pixel capacitor in each signal fixed period, the pixel transistor is electrically disconnected from the signal line by closing the sampling transistor before the signal line is switched from a constant potential to the potential of the video signal. .

  The pixel circuit according to the present invention includes a correcting unit in order to cancel the dependence of the output current supplied to the light emitting element on the threshold voltage. As a feature, this correction means operates during a part of the horizontal scanning period, detects the threshold voltage of the drive transistor in advance, and writes it in the pixel capacitance. Since the threshold voltage correction operation is performed using a part of the horizontal scanning period in which the video signal is sampled with respect to the pixel capacity, the configuration of the correction means can be simplified. Specifically, the correction means according to the present invention includes a first switching transistor that conducts before the horizontal scanning period and resets the pixel capacitance in advance, and conducts the reset during the horizontal scanning period. A second switching transistor that charges the threshold voltage can be used. Therefore, the pixel circuit of the present invention can be constituted by the first and second switching transistors constituting the correcting means, the sampling transistor for sampling the video signal, and the drive transistor for driving the light emitting element. Thus, the pixel circuit of the present invention can be composed of a total of four transistors, and the number of elements can be reduced. Accordingly, the number of power supply lines and gate lines can be reduced, and the yield can be improved by reducing the wiring crossover. At the same time, high definition panels can be achieved.

  According to the present invention, the first switching transistor described above uses another scanning line positioned before the scanning line assigned to the pixel as a gate line for control. Specifically, the first switching transistor constituting the correcting means of the present invention is connected to the other scanning line during the previous horizontal scanning period assigned to the other scanning line located before the scanning line. Conduction is performed according to the supplied control signal, thereby resetting the pixel capacitance. In this way, by using the scanning line belonging to the previous row as the gate line of the first switching transistor constituting the correcting means, the total number of gate lines can be reduced, thereby reducing the wiring crossover. Leads to improved yield. At the same time, high definition panels can be achieved.

  Further, according to the present invention, the correcting means incorporated in the pixel circuit operates within a plurality of horizontal scanning periods assigned to the plurality of scanning lines, and charges the pixel capacitance to the threshold voltage in a time division manner. In this way, by dividing the threshold voltage correction operation into a plurality of horizontal scanning periods and dividing it into a plurality of times, the threshold voltage correction time per horizontal scanning period can be set short. Accordingly, a sufficient sampling time of the video signal in one horizontal scanning period can be secured. Therefore, even in a high-definition and high-frequency driving panel, the video signal potential can be sufficiently written into the pixel capacitor. Therefore, the display panel can be further refined and driven at a high frequency.

It is a block diagram which shows the display apparatus concerning this invention. FIG. 2 is a circuit diagram illustrating a first embodiment of a pixel circuit included in the display device illustrated in FIG. 1. It is the schematic diagram which took out the pixel circuit contained in the display apparatus shown in FIG. 4 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 3. FIG. 4 is a schematic diagram for explaining an operation of the pixel circuit shown in FIG. 3. It is a graph similarly provided for operation explanation. It is a schematic diagram for explaining the operation in the same manner. It is a graph which shows the operating characteristic of the drive transistor contained in the pixel circuit shown in FIG. 6 is a timing chart showing a second embodiment of the pixel circuit according to the present invention. It is a block diagram which shows the display apparatus concerning this invention. FIG. 11 is a circuit diagram illustrating a third embodiment of a pixel circuit included in the display device illustrated in FIG. 10. It is the schematic diagram which took out the pixel circuit contained in the display apparatus shown in FIG. 13 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 12. It is a block diagram which shows the display apparatus concerning a reference example. It is the schematic diagram which took out the pixel circuit contained in the display apparatus shown in FIG. 16 is a timing chart for explaining the operation of the pixel circuit shown in FIG.

  Embodiments of the present invention will be described below in detail with reference to the drawings. First, an overall configuration of an active matrix display device having a threshold voltage (Vth) correction function will be described with reference to FIG. As shown in the figure, the active matrix display device includes a pixel array 1 as a main part and a peripheral circuit part. The peripheral circuit section includes a horizontal selector 3, a write scanner 4, a drive scanner 5, a correction scanner 7, and the like. The pixel array 1 includes row-like scanning lines WS and column-like signal lines SL, and pixels R, G, and B arranged in a matrix at the intersection of the two. In order to enable color display, RGB three primary color pixels are prepared, but the present invention is not limited to this. Each pixel R, G, B is constituted by a pixel circuit 2. The signal line SL is driven by the horizontal selector 3. The horizontal selector 3 forms a signal unit and supplies a video signal to the signal line SL. The scanning line WS is scanned by the write scanner 4. In addition, other scanning lines DS and AZ are wired in parallel with the scanning line WS. The scanning line DS is scanned by the drive scanner 5. The scanning line AZ is scanned by the correction scanner 7. The write scanner 4, the drive scanner 5, and the correction scanner 7 constitute a scanner unit, which sequentially scans a row of pixels every horizontal period. Each pixel circuit 2 samples the video signal from the signal line SL when selected by the scanning line WS. Further, when selected by the scanning line DS, the light emitting element included in the pixel circuit 2 is driven according to the sampled video signal. In addition, the pixel circuit 2 performs a predetermined correction operation when scanned by the scanning line AZ.

  The pixel array 1 described above is usually formed on an insulating substrate such as glass and is a flat panel. Each pixel circuit 2 is formed of an amorphous silicon thin film transistor (TFT) or a low temperature polysilicon TFT. In the case of an amorphous silicon TFT, the scanner part is composed of TAB or the like different from the panel, and is connected to the flat panel with a flexible cable. In the case of the low-temperature polysilicon TFT, the signal portion and the scanner portion can be formed of the same low-temperature polysilicon TFT, so that the pixel array portion, the signal portion, and the scanner portion can be integrally formed on the flat panel.

  FIG. 2 is a circuit diagram showing a first embodiment of the pixel circuit 2 incorporated in the display device shown in FIG. The pixel circuit 2 includes four thin film transistors Tr1, Tr3, Tr4, Trd, one capacitor element (pixel capacitor) Cs, and one light emitting element EL. The transistors Tr1, Tr3, Trd are N channel type polysilicon TFTs. Only the transistor Tr4 is a P-channel polysilicon TFT. One capacitive element Cs constitutes a pixel capacitance of the pixel circuit 2. The light emitting element EL is, for example, a diode type organic EL element having an anode and a cathode. However, the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

  The drive transistor Trd, which is the center of the pixel circuit 2, has a gate G connected to one end of the pixel capacitor Cs, and a source S connected to the other end of the pixel capacitor Cs. The drain of the drive transistor Trd is connected to the power supply Vcc via the first switching transistor Tr4. The gate of the switching transistor Tr4 is connected to the scanning line DS. The anode of the light emitting element EL is connected to the source S of the drive transistor Trd, and the cathode is grounded. This ground potential may be represented by Vcath. A second switching transistor Tr3 is interposed between the source S of the drive transistor Trd and a predetermined reference potential Vss. The gate of the transistor Tr3 is connected to the scanning line AZ. On the other hand, the sampling transistor Tr1 is connected between the signal line SL and the gate G of the drive transistor Trd. The gate of the sampling transistor Tr1 is connected to the scanning line WS.

  In such a configuration, the sampling transistor Tr1 is turned on in response to the control signal WS supplied from the scanning line WS during the horizontal scanning period (1H) assigned to the scanning line WS, and the video signal Vsig supplied from the signal line SL is pixelated. Sampling to the capacity Cs. The pixel capacitor Cs applies the input voltage Vgs to the gate G of the drive transistor Trd in accordance with the sampled video signal Vsig. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL during a predetermined light emission period. This output current Ids is dependent on the threshold voltage Vth of the channel region of the drive transistor Trd. The light emitting element EL emits light with luminance according to the video signal Vsig by the output current Ids supplied from the drive transistor Trd.

  As a feature of the present invention, the pixel circuit 2 includes a correcting unit including a first switching transistor Tr3 and a second switching transistor Tr4. In order to cancel the dependence of the output current Ids on the threshold voltage Vth, this correction means operates during part of the horizontal scanning period (1H), detects the threshold voltage Vth of the drive transistor Trd, and writes it in the pixel capacitor Cs. . This correction means operates in a state where the sampling transistor Tr1 is turned on in the horizontal scanning period (1H) and one end of the pixel capacitor Cs is held at the constant potential Vss0 by the signal line SL, and the constant potential is applied from the other end of the pixel capacitor Cs. The pixel capacitor Cs is charged until the potential difference with respect to Vss0 reaches the threshold voltage Vth. This correction means detects the threshold voltage Vth of the drive transistor Trd in the first half of the horizontal scanning period (1H) and writes it to the pixel capacitor Cs, while the sampling transistor Tr1 is supplied from the signal line SL in the second half of the horizontal scanning period (1H). The video signal Vsig to be sampled is sampled in the pixel capacitor Cs. The pixel capacitor Cs applies an input voltage Vgs obtained by adding a threshold voltage Vth written in advance to the sampled video signal Vsig between the gate G and the source S of the drive transistor Trd, and thus the threshold voltage of the output current Ids. Cancel the dependency on Vth. The correction means includes a first switching transistor Tr3 which is turned on before the horizontal scanning period (1H) and is set (reset) so that the potential difference between both ends of the pixel capacitor Cs exceeds the threshold voltage Vth, and the horizontal scanning period ( 1H) and a second switching transistor Tr4 that charges the pixel capacitor Cs until the potential difference across the pixel capacitor Cs reaches the threshold voltage Vth. The sampling transistor Tr1 samples the video signal Vsig supplied from the signal line SL into the pixel capacitor Cs during a signal supply period in which the signal line SL is at the potential of the video signal Vsig within the horizontal scanning period (1H), while correcting means. Detects the threshold voltage Vth of the drive transistor Trd and writes it to the pixel capacitor Cs during the signal fixing period in which the signal line SL is at the constant potential Vss0 within the horizontal scanning period (1H).

  In the present embodiment, the output current Ids of the drive transistor Trd depends on the carrier mobility μ in addition to the threshold voltage Vth of the channel region. In order to cope with this, the correcting means of the present invention operates in a part of the horizontal scanning period (1H) to cancel the dependence of the output current Ids on the carrier mobility μ, and the video signal Vsig is sampled. An output current Ids is extracted from the drive transistor Trd, and this is negatively fed back to the pixel capacitor Cs to correct the input voltage Vgs.

  FIG. 3 is a schematic diagram in which a portion of the pixel circuit 2 is taken out from the display device shown in FIG. In order to facilitate understanding, the video signal Vsig sampled by the sampling transistor Tr1, the input voltage Vsig and output current Ids of the drive transistor Trd, and the capacitance component Coled of the light emitting element EL are added. In addition, scanning lines WS, DS, and AZ connected to the gates of the transistors are also written. The pixel circuit 2 performs a Vth correction operation and a video signal writing operation within the horizontal scanning period. Thus, the pixel circuit 2 can be configured with four transistors Tr1, Tr3, Tr4, Trd, one pixel capacitor Cs, and one light emitting element EL. Compared to a conventional pixel circuit incorporating a Vth correction function, at least one transistor can be reduced. As a result, one power supply line and at least one gate line (scanning line) can be reduced, leading to an improvement in panel yield. Further, high definition can be achieved by simplifying the layout of the pixel circuit.

  FIG. 4 is a timing chart of the pixel circuit shown in FIGS. The operation of the pixel circuit shown in FIGS. 2 and 3 will be described specifically and in detail with reference to FIG. FIG. 4 shows the waveforms of control signals applied to the scanning lines WS, AZ, and DS along the time axis T. In order to simplify the notation, the control signals are also denoted by the same reference numerals as the corresponding scanning lines. In addition, the waveform of the video signal Vsig applied to the signal line is also shown along the time axis T. As shown in the figure, this video signal Vsig becomes a constant potential Vss0 in the first half of each horizontal scanning period H and becomes a signal potential in the second half. Since the transistors Tr1 and Tr3 are N-channel type, the transistors Tr1 and Tr3 are turned on when the scanning lines WS and AZ are each at a high level and turned off when the scanning lines WS and AZ are at a low level. On the other hand, since the transistor Tr4 is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. This timing chart also shows the change in the potential of the gate G of the drive transistor Trd and the change in the potential of the source S, along with the waveforms of the control signals WS, AZ, DS and the waveform of the video signal Vsig.

  In the timing chart of FIG. 4, timings T1 to T8 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. The timing chart represents the waveforms of the control signals WS, AZ, DS applied to the pixels for one row.

  At the timing T0 before the field starts, all the control signals WS, AZ, DS are at the low level. Accordingly, the N-channel transistors Tr1 and Tr3 are in the off state, while only the P-channel transistor Tr4 is in the on state. Therefore, since the drive transistor Trd is connected to the power supply Vcc via the transistor Tr4 in the on state, the output current Ids is supplied to the light emitting element EL according to the predetermined input voltage Vgs. Therefore, the light emitting element EL emits light at the timing T0. At this time, the input voltage Vgs applied to the drive transistor Trd is represented by the difference between the gate potential and (G) source potential (S).

  At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. As a result, the transistor Tr4 is turned off and the drive transistor Trd is disconnected from the power supply Vcc, so that the light emission stops and the non-light emission period starts. At timing T1, all the transistors Tr1, Tr3, Tr4 are turned off.

  Subsequently, at timing T2, the control signal AZ rises from the low level to the high level, and the switching transistor Tr3 is turned on. Thereby, the reference potential Vss is written to the other end of the pixel capacitor Cs and the source S of the drive transistor Trd. At this time, since the gate potential of the drive transistor Trd is high impedance, the gate potential (G) also decreases following the decrease in the source potential (S).

  Thereafter, after the control signal AZ returns to the low level and the switching transistor Tr3 is turned off, the control signal WS becomes the high level at the timing Ta, and the sampling transistor Tr1 becomes conductive. At this time, the potential appearing on the signal line is set to a predetermined constant potential Vss0. Here, Vss0 and Vss are set so as to satisfy Vss0−Vss> Vth. Vss0-Vss is the input voltage Vgs of the drive transistor Trd. Here, by setting Vgs> Vth, preparation for the subsequent Vth correction operation is performed. In other words, both ends of the pixel capacitor Cs are set to a voltage exceeding Vgs at the timing Ta, and the pixel capacitor Cs is reset prior to the Vth correction operation. When the threshold voltage of the light emitting element EL is VthEL, a reverse bias is applied to the light emitting element EL by setting VthEL> Vss. This is necessary to perform the subsequent Vth correction operation normally.

  Subsequently, at timing T3, the control signal DS is switched to low level, the switching transistor Tr4 is turned on, and Vth correction is executed. At this time, the potential of the signal line is still held at the constant potential Vss0 in order to accurately correct Vth. When the switching transistor Tr4 is turned on, the drive transistor Trd is connected to the power supply Vcc, and the output current Ids flows. As a result, the pixel capacitor Cs is charged, and the source potential (S) connected to the other end increases. On the other hand, the potential (gate potential G) at one end of the pixel capacitor Cs is fixed at Vss0. Accordingly, the source potential (S) rises with the charging of the pixel capacitor Cs, and the drive transistor Trd is cut off when the input voltage Vgs just reaches Vth. When the drive transistor Trd is cut off, its source potential (S) becomes Vss0-Vth as shown in the timing chart.

  Thereafter, the control signal DS is returned to the high level at timing T4, and the switching transistor Tr4 is turned off to complete the Vth correction operation. By this correction operation, a voltage corresponding to the threshold voltage Vth is written in the pixel capacitor Cs.

  After Vth correction is thus performed at timings T3 to T4, half of one horizontal scanning period (1H) has elapsed, and the potential of the signal line changes from Vss0 to Vsig. As a result, the video signal Vsig is written into the pixel capacitor Cs. The pixel capacitance Cs is sufficiently smaller than the equivalent capacitance Coled of the light emitting element EL. As a result, most of the video signal Vsig is written into the pixel capacitor Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a level (Vsig + Vth) obtained by adding Vth previously detected and held and Vsig sampled this time. The gate / source voltage Vgs is Vsig + Vth as shown in the timing chart of FIG. The sampling of the video signal Vsig is performed until timing T7 when the control signal WS returns to the low level. That is, timings T5 to T7 correspond to the sampling period.

  Thus, in the present invention, the Vth correction period T3-T4 and the sampling period T5-T7 are included in one horizontal scanning period (1H). During 1H, the sampling control signal WS is at a high level. In the present invention, Vth correction and Vsig writing are performed with the sampling transistor Tr1 turned on. Thereby, the configuration of the pixel circuit 2 is simplified.

  In this embodiment, in addition to the above-described Vth correction, the mobility μ is also corrected at the same time. However, the present invention is not limited to this, and it is needless to say that the present invention can also be applied to a pixel circuit having only a simple Vth correction operation without performing mobility μ correction. In the pixel circuit 2 of the present embodiment, N-channel and P-channel transistors are mixed except for the drive transistor Trd. However, the present invention is not limited to this, and only the N-channel transistor or the P-channel transistor is used. It is also possible to configure with only a transistor.

  The mobility μ is corrected at timings T6 to T7. This point will be described in detail below. At timing T6 before the end of the sampling period T7, the control signal DS becomes low level and the switching transistor Tr4 is turned on. As a result, the drive transistor Trd is connected to the power supply Vcc, so that the pixel circuit proceeds from the non-light emitting period to the light emitting period. In this manner, the mobility correction of the drive transistor Trd is performed in the period T6-T7 in which the sampling transistor Tr1 is still on and the switching transistor Tr4 is on. That is, in the present embodiment, the mobility correction is performed in the period T6-T7 in which the latter part of the sampling period and the head part of the light emission period overlap. Note that, at the beginning of the light emission period in which the mobility correction is performed, the light emitting element EL is actually in a reverse bias state, and thus does not emit light. In the mobility correction period T6-T7, the drain current Ids flows through the drive transistor Trd while the gate G of the drive transistor Trd is fixed at the level of the video signal Vsig. Here, by setting Vss0−Vth <VthEL, the light emitting element EL is placed in a reverse bias state, and thus exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd is written into a capacitor C = Cs + Coled obtained by combining both the pixel capacitor Cs and the equivalent capacitor Coled of the light emitting element EL. As a result, the source potential (S) of the drive transistor Trd increases. In the timing chart of FIG. 4, this increase is represented by ΔV. Since this increase ΔV is eventually subtracted from the gate / source voltage Vgs held in the pixel capacitor Cs, negative feedback is applied. In this way, the mobility μ can be corrected by negatively feeding back the output current Ids of the drive transistor Trd to the input voltage Vgs of the drive transistor Trd. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T6-T7.

At timing T7, the control signal WS becomes low level and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since the application of the video signal Vsig is cancelled, the gate potential (G) of the drive transistor Trd can be increased and increases with the source potential (S). Meanwhile, the gate / source voltage Vgs held in the pixel capacitor Cs maintains a value of (Vsig−ΔV + Vth). As the source potential (S) rises, the reverse bias state of the light emitting element EL is canceled, so that the light emitting element EL actually starts to emit light by the inflow of the output current Ids. The relationship between the drain current Ids and the gate voltage Vgs at this time is given by the following equation 2 by substituting Vsig−ΔV + Vth into Vgs of the previous transistor characteristic equation 1.
Ids = kμ (Vgs−Vth) ² = kμ (Vsig−ΔV) ² Equation 2
In the above formula 2, k = (1/2) (W / L) Cox. It can be seen from the characteristic formula 2 that the term Vth is canceled and the output current Ids supplied to the light emitting element EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light emitting element EL emits light with a luminance corresponding to the video signal Vsig. At that time, Vsig is corrected by the feedback amount ΔV. This correction amount ΔV acts so as to cancel the effect of the mobility μ located in the coefficient part of the characteristic formula 2 just. Therefore, the drain current Ids substantially depends only on the video signal Vsig.

  Finally, when the timing T8 is reached, the control signal DS becomes high level, the switching transistor Tr4 is turned off, the light emission ends, and the field ends. Thereafter, the operation proceeds to the next field, and the Vth correction operation, the mobility correction operation, and the light emission operation are repeated again.

  FIG. 5 is a circuit diagram showing a state of the pixel circuit 2 in the mobility correction period T6-T7. As shown in the figure, in the mobility correction period T6-T7, the sampling transistor Tr1 and the switching transistor Tr4 are turned on, while the remaining switching transistors Tr3 are turned off. In this state, the source potential (S) of the drive transistor Tr4 is Vss0-Vth. This source potential S is also the anode potential of the light emitting element EL. As described above, by setting Vss0−Vth <VthEL, the light emitting element EL is placed in a reverse bias state and exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd flows into the combined capacitance C = Cs + Coled of the pixel capacitance Cs and the equivalent capacitance Coled of the light emitting element EL. In other words, a part of the drain current Ids is negatively fed back to the pixel capacitor Cs, and the mobility is corrected.

  FIG. 6 is a graph of the above-described transistor characteristic formula 2, in which Ids is plotted on the vertical axis and Vsig is plotted on the horizontal axis. The characteristic formula 2 is also shown below the graph. In the graph of FIG. 6, a characteristic curve is drawn in a state where the pixel 1 and the pixel 2 are compared. The mobility μ of the drive transistor of the pixel 1 is relatively large. Conversely, the mobility μ of the drive transistor included in the pixel 2 is relatively small. Thus, when the drive transistor is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels. For example, when the video signal Vsig of the same level is written in both the pixels 1 and 2, the output current Ids 1 ′ flowing in the pixel 1 having the high mobility μ is the pixel 2 having the low mobility μ unless the mobility is corrected. A large difference is generated as compared with the output current Ids2 'flowing through the current. In this way, a large difference occurs between the output currents Ids due to the variation in the mobility μ, so that the uniformity of the screen is impaired.

  Therefore, in the present invention, the variation in mobility is canceled by negatively feeding back the output current to the input voltage side. As is clear from the transistor characteristic equation, the drain current Ids increases when the mobility is large. Therefore, the negative feedback amount ΔV increases as the mobility increases. As shown in the graph of FIG. 6, the negative feedback amount ΔV1 of the pixel 1 having a high mobility μ is larger than the negative feedback amount ΔV2 of the pixel 2 having a low mobility. Therefore, the larger the mobility μ is, the more negative feedback is applied, and the variation can be suppressed. As shown in the figure, when ΔV1 is corrected in the pixel 1 having a high mobility μ, the output current greatly decreases from Ids1 ′ to Ids1. On the other hand, since the correction amount ΔV2 of the pixel 2 having the low mobility μ is small, the output current Ids2 ′ does not decrease so much to Ids2. As a result, Ids1 and Ids2 are substantially equal, and the variation in mobility is cancelled. Since the cancellation of the variation in mobility is performed in the entire range of Vsig from the black level to the white level, the uniformity of the screen becomes extremely high. In summary, when there are pixels 1 and 2 having different mobility, the correction amount ΔV1 of the pixel 1 having high mobility is smaller than the correction amount ΔV2 of the pixel 2 having low mobility. That is, as the mobility increases, ΔV increases and the decrease value of Ids increases. As a result, pixel current values having different mobilities are made uniform, and variations in mobility can be corrected.

For reference, a numerical analysis of the mobility correction described above is performed with reference to FIG. As shown in FIG. 7, the analysis is performed by taking the source potential of the drive transistor Trd as a variable V in a state where the transistors Tr1 and Tr4 are turned on. Assuming that the source potential (S) of the drive transistor Trd is V, the drain current Ids flowing through the drive transistor Trd is as shown in Equation 3 below.

Further, Ids = dQ / dt = CdV / dt is established as shown in the following Expression 4 by the relationship between the drain current Ids and the capacitance C (= Cs + Coled).

Both sides are integrated by substituting Equation 3 into Equation 4. Here, the initial state of the source voltage V is -Vth, and the mobility variation correction time (T6-T7) is t. When this differential equation is solved, the pixel current with respect to the mobility correction time t is given as shown in Equation 5 below.

  FIG. 8 is a graph of Equation 5, in which the vertical axis represents the output current Ids and the horizontal axis represents the video signal Vsig. As the parameters, mobility correction periods t = 0 us, 2.5 us, and 5 us are set. Further, when the mobility μ is a relatively large parameter, the parameter is 1.2 μ and the relatively small mobility is 0.8 μ. It can be seen that the mobility variation is sufficiently corrected at t = 2.5 us, compared to the case where the mobility correction is not substantially applied at t = 0 us. Without mobility correction, Ids with 40% variation can be reduced to 10% or less when mobility correction is applied. However, if the correction period is lengthened with t = 5 us, the variation in the output current Ids due to the difference in mobility μ is increased. Thus, in order to apply appropriate mobility correction, it is necessary to set t to an optimal value. In the graph shown in FIG. 8, the optimum value is around t = 2.5 us.

  Next, a second embodiment of the pixel circuit according to the present invention will be described. In the first embodiment described above, as shown in the timing chart of FIG. 4, Vth correction and Vsig writing are performed within one horizontal scanning period (1H). This reduces the number of circuit elements. However, in the pixel circuit of the first embodiment, when the number of pixels of the panel is increased to increase the definition or the field frequency is increased to improve the image quality, the horizontal scanning period (1H) is shortened. There is a possibility that correction cannot be applied. On the contrary, if the Vth correction period is secured to some extent, the Vsig writing time is compressed, so that it is possible that the video signal cannot be sufficiently written into the pixel capacity. The second embodiment is an improvement of the first embodiment, and can cope with higher definition and higher image quality of the panel. The pixel circuit configuration of the second embodiment is basically the same as the pixel circuit configuration of the first embodiment shown in FIG. However, the operation sequence is different and will be described in detail with reference to the timing chart of FIG. For ease of understanding, the corresponding reference numerals are used for the portions corresponding to those in the timing chart of FIG. 4 showing the operation of the first embodiment.

  As is clear from FIG. 9, in this embodiment, the Vth correction period is divided into a plurality of times. Thereby, even if the Vth correction period for each time is short, a sufficiently long Vth correction period can be ensured by performing a plurality of times. As a result, the number of circuit elements can be reduced and the panel can be made to have higher definition and higher frequency. Even if each Vth correction period is as short as several μs, Vth variation can be sufficiently corrected by summing the correction amounts over a plurality of times.

  The operation of the second embodiment will be described in detail below with reference to the timing chart of FIG. First, at timing T1, the control signal DS is set to the high level, and the switching transistor Tr4 is turned off. Thereafter, at timing T2, the control signal AZ is set to the high level to turn on the switching transistor Tr3. As a result, the reference potential Vss is written to the source potential (S) of the drive transistor Trd. At this time, since the gate potential (G) is high impedance, the gate potential (G) also decreases as the source potential (S) decreases.

  Thereafter, Vth correction is performed in a time-sharing manner in a horizontal blanking period that divides each horizontal scanning line. In each horizontal blanking period, the potential of the signal line is set to a constant potential Vss0. In the first Vth correction period, the control signal WS goes high and the sampling transistor is turned on. At this time, as described above, the potential of the signal line is set to Vss0. Here, Vss0−Vss = Vgs> Vth is satisfied, and preparation for subsequent Vth correction is performed by setting Vgs> Vth. When the threshold voltage of the light emitting element EL is VthEL, a reverse bias is applied to the light emitting element EL by setting VthEL> Vss. This is necessary to perform the subsequent Vth correction operation and mobility correction operation normally.

  Next, with the sampling transistor turned on, the control signal DS is switched to the low level at timing T31 to turn on the switching transistor Tr4. As a result, the first Vth correction is executed. At this time, the potential of the signal line is kept at a constant potential Vss0 in order to accurately perform Vth correction. In the drive transistor Trd, the output current Ids flows toward the cutoff when the switching transistor Tr4 is turned on. Thereafter, the control signal DS is returned to the high level at the timing T41, the switching transistor Tr4 is turned off, and the first Vth correction is completed. After that, it is desirable to return the control signal WS to the low level and turn off the sampling transistor while the potential of the signal line does not change. However, there is no problem in operation without doing so.

  In the present embodiment, one Vth correction period is set to be within a horizontal blanking period, for example. Therefore, in one Vth correction operation, the drive transistor Trd is not cut off, and its source potential (S) is held at an intermediate operating point.

  When the next horizontal blanking period comes and the potential of the signal line becomes Vss0 again, the second Vth correction operation is performed. That is, WS is switched to the high level to turn on the sampling transistor Tr1, and the control signal DS is switched to the low level to turn on the switching transistor Tr4, thereby performing the second Vth correction operation. This second Vth correction period is represented by T32-T42. By performing this series of Vth correction operations a plurality of times until the drive transistor is cut off, the Vth correction is completed.

  In the example shown in the timing chart of FIG. 9, after performing the third Vth correction in the horizontal blanking period positioned at the head of the horizontal scanning period (1H) assigned to the scanning line WS, the video signal Vsig is converted into a pixel. The capacitance is written, and then the mobility μ is corrected. The third Vth correction period is represented by T33-T43. When this third Vth correction is completed, the difference between the gate potential (G) and the source potential (S) is just set to Vth.

  As described above, in the present embodiment, the correction means incorporated in the pixel circuit 2 operates within a plurality of horizontal scanning periods assigned to a plurality of scanning lines, and the pixel capacitance Cs is reduced to the threshold voltage Vth in a time division manner. Charge. The sampling transistor applies the video signal supplied from the signal line SL to the pixel capacitor Cs during the signal supply period in which the signal line SL becomes the potential Vsig of the video signal within the horizontal scanning period (1H) assigned to the scanning line WS. While sampling, the correction means detects the threshold voltage Vth of the drive transistor Trd in a time-sharing manner during a signal fixing period in which the signal line SL is at a constant potential Vss0 within each horizontal scanning period assigned to the plurality of scanning lines WS. The pixel capacitor Cs is charged to the threshold voltage Vth. This signal fixing period is a horizontal blanking period that divides each horizontal scanning period sequentially assigned to each scanning line WS. The correction unit charges the pixel capacitor Cs to the threshold voltage Vth in a time division manner in each horizontal blanking period. When the correcting means charges the pixel capacitor Cs in each signal fixing period, the sampling transistor Tr1 is closed and the pixel capacitor Cs is electrically connected to the signal line SL before the signal line SL is switched from the constant potential Vss0 to the potential Vsig of the video signal. It is preferable to separate them.

  FIG. 10 is a schematic block diagram showing a display device according to the third embodiment of the present invention. For easy understanding, the parts corresponding to those of the display device according to the first embodiment shown in FIG. The difference is that the first embodiment includes three scanning lines (gate lines) WS, DS, and AZ, whereas the third embodiment includes two scanning lines WS and DS for the pixel array 1. And to further reduce the gate line. Specifically, the number of scanning lines AZ is reduced, and instead of this, the preceding scanning line WS is used as a substitute for the present scanning line AZ. As a result, one gate line can be reduced and a correction scanner is not required.

  FIG. 11 schematically shows a total of two pixel circuits included in the pixel array of the display device shown in FIG. 10, one for the previous stage and one for the current stage. The configuration of each pixel circuit 2 is basically similar to that of the first embodiment shown in FIG. 2, and corresponding portions are denoted by corresponding reference numerals. Each pixel circuit 2 includes a sampling transistor Tr1, a drive transistor Trd, a first switching transistor Tr3, a second switching transistor Tr4, a pixel capacitor Cs, and a light emitting element EL. The difference is that the scanning line WS of the previous stage is connected to the gate of the first switching transistor Tr3. However, since the pixel circuit 2 in the first stage does not have the previous scanning line WS, it needs to be supplied separately.

  FIG. 12 is a schematic diagram in which one more pixel circuit is extracted from the pixel array shown in FIG. In order to facilitate understanding, the video signal Vsig sampled by the sampling transistor Tr1, the input voltage Vgs and output current Ids of the drive transistor Trd, and the capacitance component Coled of the light emitting element EL are added. Further, the scanning line at the stage connected to the gate of the sampling transistor Tr1 is represented by WSn, the scanning line at the previous stage connected to the gate of the first switching transistor Tr3 is represented by WSn-1, and is connected to the gate of the second switching transistor Tr4. The scanning line to be performed is represented by DS.

  FIG. 13 is a timing chart showing the operation of the pixel circuit shown in FIG. In order to facilitate understanding, corresponding reference numerals are used for portions corresponding to the timing chart of the first embodiment shown in FIG. This timing chart represents the waveform of a control signal applied to each scanning line WSn, WSn-1, DS along the time axis T. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. This timing chart also represents the waveform of each control signal WSn, WSn-1, DS, as well as the potential change of the gate G and the source S of the drive transistor Trd, and the waveform of the video signal Vsig applied to the signal line. It is. As shown in the figure, the video signal Vsig is fixed at a constant potential Vss0 in the first half of each horizontal scanning period and becomes a video signal potential in the second half. At timing T1, the control signal DS becomes high level, the switching transistor Tr4 is turned off, and the pixel circuit enters a non-light emitting state. At the timing T2, the previous stage control signal WSn-1 becomes high level, and the switching transistor Tr3 is turned on. As a result, the pixel capacitance Cs is reset and Vgs> Vth is set. That is, a preparation operation for Vth correction is performed. At the timing Ta, the control signal WSn at this stage rises to a high level, and the sampling transistor Tr1 becomes conductive. Subsequently, at timing T3, the control signal DS becomes low level, and the second switching transistor Tr4 is turned on. As a result, the pixel capacitor Cs is charged with one end of the pixel capacitor Cs fixed at a constant potential Css0, and Vth is written. That is, the Vth correction operation is performed. Subsequently, the video signal Vsig is written into the pixel capacitor Cs at timing T5. Further, at the timing T6, the mobility μ is corrected and the light emission state is entered.

  As described above, the third embodiment includes correction means for detecting the threshold voltage Vth of the drive transistor Trd and writing it in the pixel capacitor Cs in order to cancel the dependence of the output current Ids on the threshold voltage Vth. Yes. This correction means includes a first switching transistor Tr3 and a second switching transistor Tr4. The first switching transistor Tr3 is a control signal supplied from the other scanning line WSn-1 in the previous horizontal scanning period assigned to the other scanning line WSn-1 positioned before the scanning line WSn of the first stage. The conduction is set according to WSn−1, so that the potential difference between both ends of the pixel capacitor Cs is set to exceed the threshold voltage Vth. The second switching transistor Tr4 is turned on during the horizontal scanning period (1H) assigned to this stage and charges the pixel capacitor Cs until the potential difference (Vgs) across the pixel capacitor Cs reaches the threshold voltage Vth. In the embodiment shown in FIG. 13, the scanning line WSn−1 positioned immediately before the scanning line WSn at this stage is used as the scanning line at the previous stage. In some cases, instead of this, the previous scanning line WSn-2 or the previous scanning line can be used as the gate line of the first switching transistor Tr3. As described above, in the present embodiment, by sharing the scanning line WS between two pixels, one gate line can be further reduced, which leads to improvement of the yield of the panel and simplification of the layout. High definition is also possible.

  FIG. 14 is a block diagram illustrating a reference example of a pixel circuit. In order to facilitate understanding, portions corresponding to those of the first embodiment shown in FIG. 2 are denoted by corresponding reference numerals. The difference is that this reference example performs the Vth correction operation before the horizontal scanning period. For this reason, one more switching transistor Tr2 is required in addition to the switching transistor Tr3 in preparation for Vth correction. One transistor Tr3 resets the source side terminal of the pixel capacitor Cs, while the additional transistor Tr2 resets the gate side terminal of the pixel capacitor Cs. In order to drive the additional switching transistor Tr2, an additional scanning line AZ1 and an additional correction scanner 71 are required. In the present invention, the transistor Tr2 is unnecessary by setting the gate side terminal of the pixel capacitor Cs within the horizontal scanning period. The transistor Tr2 writes the power supply voltage Vss1 to the gate G. In contrast, in the present invention, the fixed potential Vss0 supplied from the signal line SL is written during the horizontal scanning period.

  The operation of the reference example shown in FIG. 14 will be described below. This active matrix display device is composed of a pixel array 1 as a main part and a peripheral circuit part. The peripheral circuit section includes a horizontal selector 3, a write scanner 4, a drive scanner 5, a first correction scanner 71, a second correction scanner 72, and the like. The pixel array 1 is composed of row-like scanning lines WS and column-like signal lines SL, and pixel circuits 2 arranged in a matrix at portions where they intersect. In the figure, only one pixel circuit 2 is enlarged for easy understanding. The signal line SL is driven by the horizontal selector 3. The horizontal selector 3 forms a signal unit and supplies a video signal to the signal line SL. The scanning line WS is scanned by the write scanner 4. In addition, other scanning lines DS, AZ1, and AZ2 are also wired in parallel with the scanning line WS. The scanning line DS is scanned by the drive scanner 5. The scanning line AZ1 is scanned by the first correction scanner 71. The scanning line AZ2 is scanned by the second correction scanner 72. The write scanner 4, the drive scanner 5, the first correction scanner 71, and the second correction scanner 72 constitute a scanner unit, and sequentially scan the pixel rows every horizontal period. Each pixel circuit 2 samples a video signal from the signal line SL when selected by the scanning line WS. Further, when selected by the scanning line DS, the light emitting element EL included in the pixel circuit 2 is driven in accordance with the sampled video signal. In addition, the pixel circuit 2 performs a predetermined correction operation when scanned by the scanning lines AZ1 and AZ2.

  The pixel circuit 2 includes five thin film transistors Tr1 to Tr4 and Trd, one capacitor element (pixel capacitor) Cs, and one light emitting element EL. The transistors Tr1 to Tr3 and Trd are N channel type polysilicon TFTs. Only the transistor Tr4 is a P-channel type polysilicon TFT. One capacitive element Cs constitutes a capacitive part of the pixel circuit 2. The light emitting element EL is, for example, a diode type organic EL element having an anode and a cathode.

  The drive transistor Trd which is the center of the pixel circuit 2 has a gate G connected to one end of the pixel capacitor Cs and a source S connected to the other end of the pixel capacitor Cs. The gate G of the drive transistor Trd is connected to another reference potential Vss1 via the switching transistor Tr2. The drain of the drive transistor Trd is connected to the power source Vcc via the switching transistor Tr4. The gate of the switching transistor Tr2 is connected to the scanning line AZ1. The gate of the switching transistor Tr4 is connected to the scanning line DS. The anode of the light emitting element EL is connected to the source S of the drive transistor Trd, and the cathode is grounded. This ground potential may be represented by Vcath. Further, the switching transistor Tr3 is interposed between the source S of the drive transistor Trd and a predetermined reference potential Vss2. The gate of the transistor Tr3 is connected to the scanning line AZ2. On the other hand, the sampling transistor Tr1 is connected between the signal line SL and the gate G of the drive transistor Trd. The gate of the sampling transistor Tr1 is connected to the scanning line WS.

  In such a configuration, the sampling transistor Tr1 conducts in response to the control signal WS supplied from the scanning line WS during a predetermined sampling period, and samples the video signal Vsig supplied from the signal line SL in the capacitor unit Cs. The capacitor Cs applies the input voltage Vgs between the gate G and the source S of the drive transistor in accordance with the sampled video signal Vsig. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL during a predetermined light emission period. The output current (drain current) Ids has dependency on the carrier mobility μ and the threshold voltage Vth in the channel region of the drive transistor Trd. The light emitting element EL emits light with luminance according to the video signal Vsig by the output current Ids supplied from the drive transistor Trd.

  The pixel circuit 2 includes correction means including switching transistors Tr2 to Tr4. In order to cancel the dependency of the output current Ids on the carrier mobility μ, the input held in the capacitor Cs at the beginning of the light emission period in advance. The voltage Vgs is corrected. Specifically, the correction means (Tr2 to Tr4) operate in a part of the sampling period according to the control signals WS and DS supplied from the scanning lines WS and DS, and the video signal Vsig is sampled. Thus, the output current Ids is extracted from the drive transistor Trd and negatively fed back to the capacitor Cs to correct the input voltage Vgs. Further, the correction means (Tr2 to Tr4) detects the threshold voltage Vth of the drive transistor Trd in advance of the sampling period in order to cancel the dependence of the output current Ids on the threshold voltage Vth, and detects the detected threshold voltage Vth. Is added to the input voltage Vgs.

  The drive transistor Trd is an N-channel transistor and has a drain connected to the power supply Vcc side and a source S connected to the light emitting element EL side. In this case, the correction means described above takes out the output current Ids from the drive transistor Trd at the beginning of the light emission period that overlaps the latter part of the sampling period, and negatively feeds back to the capacitor Cs side. At this time, the present correcting means causes the output current Ids extracted from the source S side of the drive transistor Trd at the head of the light emission period to flow into the capacitance of the light emitting element EL. Specifically, the light emitting element EL is composed of a diode type light emitting element having an anode and a cathode. The anode side is connected to the source S of the drive transistor Trd, and the cathode side is grounded. With this configuration, the correction means (Tr2 to Tr4) sets the anode / cathode of the light emitting element EL in a reverse bias state in advance, and the output current Ids extracted from the source S side of the drive transistor Trd is the light emitting element EL. This diode-type light emitting element EL functions as a capacitive element. The correction means can adjust the time width t for extracting the output current Ids from the drive transistor Trd within the sampling period, and thereby optimizes the negative feedback amount of the output current Ids with respect to the capacitor Cs.

  FIG. 15 is a schematic diagram of the pixel circuit portion extracted from the display device shown in FIG. In order to facilitate understanding, the video signal Vsig sampled by the sampling transistor Tr1, the input voltage Vgs and output current Ids of the drive transistor Trd, and the capacitance component Coled of the light emitting element EL are added. The basic operation of the pixel circuit 2 will be described below with reference to FIG.

  FIG. 16 is a timing chart of the pixel circuit shown in FIG. With reference to FIG. 16, the operation of the pixel circuit shown in FIG. 15 will be described more specifically and in detail. FIG. 16 shows the waveforms of control signals applied to the scanning lines WS, AZ1, AZ2, and DS along the time axis T. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. Since the transistors Tr1, Tr2 and Tr3 are N-channel type, they are turned on when the scanning lines WS, AZ1 and AZ2 are at a high level, and turned off when the scanning lines are at a low level. On the other hand, since the transistor Tr4 is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. This timing chart also shows the change in the potential of the gate G and the change in the potential of the source S of the drive transistor Trd, along with the waveforms of the control signals WS, AZ1, AZ2, and DS.

  In the timing chart of FIG. 16, timings T1 to T8 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. The timing chart shows the waveforms of the control signals WS, AZ1, AZ2, DS applied to the pixels for one row.

  At timing T0 before the field starts, all control line numbers WS, AZ1, AZ2, DS are at a low level. Therefore, the N-channel transistors Tr1, Tr2, Tr3 are in the off state, while only the P-channel transistor Tr4 is in the on state. Therefore, since the drive transistor Trd is connected to the power supply Vcc via the transistor Tr4 in the on state, the output current Ids is supplied to the light emitting element EL according to the predetermined input voltage Vgs. Therefore, the light emitting element EL emits light at the timing T0. At this time, the input voltage Vgs applied to the drive transistor Trd is expressed by the difference between the gate potential (G) and the source potential (S).

  At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. As a result, the transistor Tr4 is turned off and the drive transistor Trd is disconnected from the power supply Vcc, so that the light emission stops and the non-light emission period starts. Therefore, at the timing T1, all the transistors Tr1 to Tr4 are turned off.

  Subsequently, at timing T2, since the control signals AZ1 and AZ2 are at a high level, the switching transistors Tr2 and Tr3 are turned on. As a result, the gate G of the drive transistor Trd is connected to the reference potential Vss1, and the source S is connected to the reference potential Vss2. Here, Vss1−Vss2> Vth is satisfied, and by setting Vss1−Vss2 = Vgs> Vth, preparation for Vth correction performed at timing T3 is performed. In other words, the period T2-T3 corresponds to a reset period of the drive transistor Trd. Further, when the threshold voltage of the light emitting element EL is VthEL, VthEL> Vss2 is set. Thereby, a minus bias is applied to the light emitting element EL, and a so-called reverse bias state is obtained. This reverse bias state is necessary for normally performing the Vth correction operation and the mobility correction operation to be performed later.

  At timing T3, the control signal AZ2 is set to the low level, and the control signal DS is also set to the low level. As a result, the transistor Tr3 is turned off while the transistor Tr4 is turned on. As a result, the drain current Ids flows into the pixel capacitor Cs, and the Vth correction operation is started. At this time, the gate G of the drive transistor Trd is held at Vss1, and the current Ids flows until the drive transistor Trd is cut off. When cut off, the source potential (S) of the drive transistor Trd becomes Vss1-Vth. At timing T4 after the drain current is cut off, the control signal DS is returned to the high level again, and the switching transistor Tr4 is turned off. Further, the control signal AZ1 is also returned to the low level, and the switching transistor Tr2 is also turned off. As a result, Vth is held and fixed in the pixel capacitor Cs. Thus, the timing T3-T4 is a period for detecting the threshold voltage Vth of the drive transistor Trd. Here, this detection period T3-T4 is called a Vth correction period.

  After performing the Vth correction in this way, the control signal WS is switched to the high level at timing T5, the sampling transistor Tr1 is turned on, and the video signal Vsig is written into the pixel capacitor Cs. The pixel capacitance Cs is sufficiently smaller than the equivalent capacitance Coled of the light emitting element EL. As a result, most of the video signal Vsig is written into the pixel capacitor Cs. To be precise, for Vss1. The difference Vsig−Vss1 of Vsig is written to the pixel capacitor Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a level (Vsig−Vss1 + Vth) obtained by adding Vth previously detected and held and Vsig−Vss1 sampled this time. Hereinafter, for simplification of description, assuming that Vss1 = 0V, the gate / source voltage Vgs becomes Vsig + Vth as shown in the timing chart of FIG. The sampling of the video signal Vsig is performed until timing T7 when the control signal WS returns to the low level. That is, the timing T5-T7 corresponds to the sampling period.

  At timing T6 before the end of the sampling period T7, the control signal DS becomes low level and the switching transistor Tr4 is turned on. As a result, the drive transistor Trd is connected to the power supply Vcc, so that the pixel circuit proceeds from the non-light emitting period to the light emitting period. In this manner, the mobility correction of the drive transistor Trd is performed in the period T6-T7 in which the sampling transistor Tr1 is still on and the switching transistor Tr4 is on. That is, in the present embodiment, the mobility correction is performed in the period T6-T7 in which the latter part of the sampling period and the head part of the light emission period overlap. Note that, at the beginning of the light emission period in which the mobility correction is performed, the light emitting element EL is actually in a reverse bias state, and thus does not emit light. In the mobility correction period T6-T7, the drain current Ids flows through the drive transistor Trd while the gate G of the drive transistor Trd is fixed at the level of the video signal Vsig. Here, by setting Vss1−Vth <VthEL, the light emitting element EL is placed in a reverse bias state, so that it exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd is written into a capacitor C = Cs + Coled obtained by combining both the pixel capacitor Cs and the equivalent capacitor Coled of the light emitting element EL. As a result, the source potential (S) of the drive transistor Trd increases. In the timing chart of FIG. 16, this rise is represented by ΔV. Since this increase ΔV is eventually subtracted from the gate / source voltage Vgs held in the pixel capacitor Cs, negative feedback is applied. In this way, the mobility μ can be corrected by negatively feeding back the output current Ids of the drive transistor Trd to the input voltage Vgs of the drive transistor Trd. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T6-T7.

At timing T7, the control signal WS becomes low level and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since the application of the video signal Vsig is cancelled, the gate potential (G) of the drive transistor Trd can be increased and increases with the source potential (S). Meanwhile, the gate / source voltage Vgs held in the pixel capacitor Cs maintains a value of (Vsig−ΔV + Vth). As the source potential (S) rises, the reverse bias state of the light emitting element EL is canceled, so that the light emitting element EL actually starts to emit light by the inflow of the output current Ids. The relationship between the drain current Ids and the gate voltage Vgs at this time is given by the following equation 2 by substituting Vsig−ΔV + Vth into Vgs of the previous transistor characteristic equation 1.
Ids = kμ (Vgs−Vth) ² = kμ (Vsig−ΔV) ² Equation 2
In the above formula 2, k = (1/2) (W / L) Cox. It can be seen from the characteristic formula 2 that the term Vth is canceled and the output current Ids supplied to the light emitting element EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light emitting element EL emits light with a luminance corresponding to the video signal Vsig. At that time, Vsig is corrected by the feedback amount ΔV. This correction amount ΔV acts so as to cancel the effect of the mobility μ located in the coefficient part of the characteristic formula 2 just. Therefore, the drain current Ids substantially depends only on the video signal Vsig.

  Finally, when the timing T8 is reached, the control signal DS becomes high level, the switching transistor Tr4 is turned off, the light emission ends, and the field ends. Thereafter, the operation proceeds to the next field, and the Vth correction operation, the mobility correction operation, and the light emission operation are repeated again.

  DESCRIPTION OF SYMBOLS 1 ... Pixel array, 2 ... Pixel circuit, 3 ... Horizontal selector, 4 ... Write scanner, 5 ... Drive scanner, 7 ... Correction scanner, Tr1 ... Sampling transistor, Tr3 ... switching transistor, Tr4 ... switching transistor, Trd ... drive transistor, EL ... light emitting element, Cs ... capacitor element

Claims (17)

A row-shaped scanning line for supplying a control signal and a column-shaped signal line for supplying a video signal are arranged at a crossing portion, at least a sampling transistor, a pixel capacitor connected thereto, a drive transistor connected thereto, Including a light emitting element connected thereto,
The sampling transistor conducts according to a control signal supplied from the scanning line during a horizontal scanning period assigned to the scanning line and samples the video signal supplied from the signal line into the pixel capacitor,
The pixel capacitor applies an input voltage to the gate of the drive transistor according to the sampled video signal,
The drive transistor supplies an output current corresponding to the input voltage to the light emitting element during a predetermined light emission period, and the output current is dependent on a threshold voltage of a channel region of the drive transistor,
In the pixel circuit that emits light with luminance according to the video signal by the output current supplied from the drive transistor,
In order to cancel the dependence of the output current on the threshold voltage, a correction unit is provided which operates in a part of a horizontal scanning period, detects the threshold voltage of the drive transistor, and writes the threshold voltage to the pixel capacitor. Pixel circuit.   The correction means operates in a state where the sampling transistor is turned on during a horizontal scanning period and one end of the pixel capacitor is held at a constant potential by the signal line, and a potential difference from the other end of the pixel capacitor with respect to the constant potential is generated. The pixel circuit according to claim 1, wherein the pixel capacitor is charged until the threshold voltage is reached. The correction means detects the threshold voltage of the drive transistor in the first half of a horizontal scanning period and writes it to the pixel capacitor,
The sampling transistor samples the video signal supplied from the signal line in the second half of the horizontal scanning period into the pixel capacitor,
The pixel capacitor applies an input voltage obtained by adding the written threshold voltage to the sampled video signal between the gate and the source of the drive transistor, thereby making the dependency of the output current on the threshold voltage. 2. The pixel circuit according to claim 1, wherein the pixel circuit is canceled out. The correction means is a first switching transistor that is turned on before a horizontal scanning period and is set so that a potential difference between both ends of the pixel capacitor exceeds the threshold voltage;
2. The pixel circuit according to claim 1, further comprising: a second switching transistor that conducts during the horizontal scanning period and charges the pixel capacitor until a potential difference between both ends of the pixel capacitor reaches the threshold voltage.   The first switching transistor is turned on in response to a control signal supplied from the other scan line during a previous horizontal scan period assigned to another scan line positioned before the scan line. 5. The pixel circuit according to claim 4, wherein a potential difference between both ends of the pixel capacitor is set to exceed the threshold voltage.   The first switching transistor is turned on in response to a control signal supplied from the other scan line in the immediately preceding horizontal scan period assigned to the other scan line located immediately before the scan line, thereby 6. The pixel circuit according to claim 5, wherein a potential difference between both ends of the pixel capacitor is set so as to exceed the threshold voltage. The sampling transistor samples the video signal supplied from the signal line into the pixel capacitor during a signal supply period in which the signal line becomes a potential of the video signal within a horizontal scanning period,
2. The pixel circuit according to claim 1, wherein the correction means detects a threshold voltage of the drive transistor and writes the threshold voltage to the pixel capacitor during a signal fixing period in which the signal line is at a constant potential within a horizontal scanning period. .   The correction means operates in a signal fixing period within a horizontal scanning period assigned to another scanning line, and charges the pixel capacitor to the threshold voltage in a time division manner in each signal fixing period. 8. The pixel circuit according to 7. The signal fixed period is a horizontal blanking period that separates each horizontal scanning period sequentially assigned to each scanning line,
9. The pixel circuit according to claim 8, wherein the correction unit charges the pixel capacitor to the threshold voltage in a time division manner in each horizontal blanking period.   When the correction unit charges the pixel capacitor in each signal fixing period, the pixel transistor is electrically disconnected from the signal line by closing the sampling transistor before the signal line is switched from a constant potential to the potential of the video signal. The pixel circuit according to claim 8. The drive transistor has an output current dependent on the carrier mobility in addition to the threshold voltage of the channel region,
The correction means operates in a part of the horizontal scanning period in order to cancel the dependency of the output current on the carrier mobility, and extracts the output current from the drive transistor in a state where the video signal is sampled. 2. The pixel circuit according to claim 1, wherein the input voltage is corrected by negatively feeding it back to the pixel capacitor. A row-shaped scanning line for supplying a control signal and a column-shaped signal line for supplying a video signal are arranged at a crossing portion, at least a sampling transistor, a pixel capacitor connected thereto, a drive transistor connected thereto, Including a light emitting element connected thereto,
The sampling transistor conducts according to a control signal supplied from the scanning line during a horizontal scanning period assigned to the scanning line and samples the video signal supplied from the signal line into the pixel capacitor,
The pixel capacitor applies an input voltage to the gate of the drive transistor according to the sampled video signal,
The drive transistor supplies an output current corresponding to the input voltage to the light emitting element during a predetermined light emission period, and the output current is dependent on a threshold voltage of a channel region of the drive transistor,
In the pixel circuit that emits light with luminance according to the video signal by the output current supplied from the drive transistor,
In order to cancel the dependence of the output current on the threshold voltage, a correction means for detecting the threshold voltage of the drive transistor and writing it to the pixel capacitor is provided.
The correction means includes a first switching transistor and a second switching transistor,
The first switching transistor is turned on in response to a control signal supplied from the other scan line during a previous horizontal scan period assigned to another scan line positioned before the scan line. Set the potential difference across the pixel capacitance to exceed the threshold voltage,
The pixel circuit, wherein the second switching transistor is turned on during the horizontal scanning period and charges the pixel capacitor until a potential difference between both ends of the pixel capacitor reaches the threshold voltage.   The first switching transistor is turned on in response to a control signal supplied from the other scan line in the immediately preceding horizontal scan period assigned to the other scan line located immediately before the scan line, thereby 13. The pixel circuit according to claim 12, wherein a potential difference between both ends of the pixel capacitor is set so as to exceed the threshold voltage. A row-shaped scanning line for supplying a control signal and a column-shaped signal line for supplying a video signal are arranged at a crossing portion, at least a sampling transistor, a pixel capacitor connected thereto, a drive transistor connected thereto, Including a light emitting element connected thereto,
The sampling transistor conducts according to a control signal supplied from the scanning line during a horizontal scanning period assigned to the scanning line and samples the video signal supplied from the signal line into the pixel capacitor,
The pixel capacitor applies an input voltage to the gate of the drive transistor according to the sampled video signal,
The drive transistor supplies an output current corresponding to the input voltage to the light emitting element during a predetermined light emission period, and the output current is dependent on a threshold voltage of a channel region of the drive transistor,
In the pixel circuit that emits light with luminance according to the video signal by the output current supplied from the drive transistor,
In order to cancel the dependence of the output current on the threshold voltage, a correction means for detecting the threshold voltage of the drive transistor and writing it in the pixel capacitor in advance of sampling the video signal is provided.
The pixel circuit operates in a plurality of horizontal scanning periods assigned to a plurality of scanning lines and charges the pixel capacitance to the threshold voltage in a time division manner. The sampling transistor samples the video signal supplied from the signal line into the pixel capacitor during a signal supply period in which the signal line becomes a video signal potential within the horizontal scanning period assigned to the scanning line. ,
The correction means detects the threshold voltage of the drive transistor in each signal fixed period in which the signal line is at a constant potential within each horizontal scanning period assigned to a plurality of scanning lines, and time-divides the pixel capacitance. The pixel circuit according to claim 14, wherein the pixel circuit is charged to the threshold voltage. The signal fixed period is a horizontal blanking period that separates each horizontal scanning period sequentially assigned to each scanning line,
16. The pixel circuit according to claim 15, wherein the correction unit charges the pixel capacitor to the threshold voltage in a time division manner in each horizontal blanking period.   When the correction unit charges the pixel capacitor in each signal fixing period, the pixel transistor is electrically disconnected from the signal line by closing the sampling transistor before the signal line is switched from a constant potential to the potential of the video signal. The pixel circuit according to claim 15.

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