JP5152094B2 - Pixel circuit, pixel circuit driving method, display device, and display device driving method - Google Patents

Description

The present invention relates to a pixel circuit that drives a light-emitting element arranged for each pixel. More specifically, the present invention relates to a pixel circuit applied to a so-called active matrix display device in which the amount of current flowing through a light emitting element such as an organic EL element is controlled by an insulated gate field effect transistor provided in each pixel circuit.

An image display device, for example, in a liquid crystal display, arranged a number of liquid crystal pixels in a matrix, by controlling the transmission intensity or the reflection intensity of the incident light for each pixel in accordance with image information to be displayed, to display an image . This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel , the organic EL element is a self-luminous element. Therefore, the organic EL display has a high image visibility than a liquid crystal display, a backlight is unnecessary, has advantages such as high response speed. Also, the brightness level of each light-emitting element (gradation) can be controlled by a current value flowing thereto, differs significantly from the voltage-controlled, such as a liquid crystal display in that a so-called current-controlled.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. The former has a simple structure, large, and, because of a problem such as it is difficult to realize a high-definition display, is currently developing an active matrix system has been popular. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.

JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

A conventional pixel circuit is arranged at a portion where a row scanning line supplying a control signal and a column signal line supplying a video signal intersect, and at least a sampling transistor, a pixel capacitor , a drive transistor, and a light emission Element. The sampling transistor conducts in response to a control signal supplied from the scanning line, and samples the video signal supplied from the signal line. The pixel capacitance holds an input voltage corresponding to the sampled video signal. The drive transistor supplies an output current during a predetermined light emission period in accordance with the input voltage held in the pixel capacitor . In general, the output current, the carrier mobility and the threshold voltage of the channel region of the drive transistor, having a dependency. The light emitting element emits light with luminance according to the video signal by the output current supplied from the drive transistor.

In the drive transistor, an output current flows between the source and the drain in accordance with the input voltage held in the pixel capacitor , and this current flows in the light emitting element. In general, the light emission luminance of a light emitting element is proportional to the amount of current . Further , the output current of the drive transistor is controlled by the gate / source voltage, that is, the input voltage written to the pixel capacitor . The conventional pixel circuit controls the amount of current supplied to the light emitting element by changing the input voltage applied between the gate / source of the drive transistor in accordance with the video signal .

Here, the operation characteristics of the drive transistor is expressed by Equation 1 below.
I _ds = (1/2) μ (W / L) C _ox ( V _gs −V _th ) ² Formula 1
In the transistor characteristic equation 1, I _ds represents a drain current flowing between the source and the drain, and is an output current supplied to the light emitting element in the pixel circuit. V _gs represents a gate-source voltage applied to the gate with reference to the source, and is the above-described input voltage in the pixel circuit. V _th is the threshold voltage of the transistor. Further, mu denotes the mobility of a semiconductor thin film constituting the channel region of the transistor. In addition , W represents the channel width, L represents the channel length, and C _ox represents the capacitance of the gate insulating film . As apparent from the transistor characteristic equation 1, when the thin film transistor operates in the saturation region, when the gate / source voltage V _gs exceeds the threshold voltage V _th , the thin film transistor is turned on and the drain current I _ds flows. . When principle view, as shown the transistor characteristic expression (1) described above, if the gate / source voltage V _gs constant, always drain current I _ds of the same amount is supplied to the light emitting element. Therefore, if video signals of the same level are supplied to all the pixels constituting the screen, all the pixels should emit light with the same luminance, and the uniformity of the screen should be obtained.

However , in reality, thin film transistors (TFTs) composed of a semiconductor thin film such as polysilicon have variations in individual device characteristics. In particular, the threshold voltage V _th is not constant and varies from pixel to pixel. As apparent from the transistor characteristic equation 1 described above, if the threshold voltage V _th of each drive transistor varies, even if the gate-source voltage V _gs is constant, the drain current I _ds varies, resulting in each pixel. since thus variations in brightness, impairing the uniformity of the screen. Conventionally , a pixel circuit incorporating a function of canceling variation in threshold voltage of a drive transistor has been developed, and for example , disclosed in Patent Document 3 described above.

However, the ability to cancel the variations in the threshold voltage (threshold voltage correction function) conventional pixel circuits incorporating the structure is complicated, has become an obstacle to miniaturization or high definition of pixels. The pixel circuits incorporating a conventional threshold voltage correction function is not efficient, has led to complication of the circuit design. In addition, the pixel circuit including a conventional threshold voltage correction function, since the number of components is relatively large, resulting in decrease in yield.

In view of the above-described problems of the conventional technology, the present invention aims to improve the efficiency and simplification of a pixel circuit having a threshold voltage correction function, thereby achieving higher definition and improved yield of a display device. Objective. In order to achieve this purpose , the following measures were taken. That is, the present invention, the control signal and a column-like signal line for supplying a scan line and the video signal of rows supplying disposed at the intersection, at least a sampling transistor, a picture element capacitance, a drive transistor , and a light emission element, the sampling transistor is rendered conductive in response to the control signal supplied from the scanning line in the horizontal scanning period assigned to the scanning lines, the video signal supplied from the signal line Sampling to a pixel capacitor, the pixel capacitor applies an input voltage to the gate of the drive transistor according to the sampled video signal, and the drive transistor outputs an output according to the input voltage during a predetermined light emission period A current is supplied to the light emitting element, and the output current has a dependence on a threshold voltage of a channel region of the drive transistor, In a pixel circuit that emits light with luminance corresponding to the video signal by an output current supplied from a live transistor, the drive transistor operates in part of a horizontal scanning period in order to cancel the dependency of the output current on the threshold voltage. And a correction means for detecting the threshold voltage and writing it in the pixel capacitance.

Preferably , the correction unit operates in a state where the sampling transistor is turned on during a horizontal scanning period and one end of the pixel capacitor is held at a constant potential by the signal line, and the constant potential is applied from the other end of the pixel capacitor. The pixel capacitor is charged until the potential difference with respect to becomes the threshold voltage. Further, the correction means, while writing the pixel capacitor in the first half of the horizontal scanning period by detecting the threshold voltage of the drive transistor, said sampling transistor, the video supplied from the signal line in the second half of the horizontal scanning period The signal is sampled into the pixel capacitor, and the pixel capacitor applies an input voltage obtained by adding the written threshold voltage to the sampled video signal between the gate and the source of the drive transistor, and thereby outputs Cancels the dependence of current on the threshold voltage. Further , the correction means is conductive before the horizontal scanning period, and is conductive during the horizontal scanning period, and a first switching transistor that is set so that a potential difference between both ends of the pixel capacitance exceeds the threshold voltage. And a second switching transistor that charges the pixel capacitor until the potential difference across the pixel capacitor reaches the threshold voltage. Further, the first switching transistor is rendered conductive in response to a control signal supplied to the horizontal scanning period before that is assigned to other scanning line located before the scanning line from the other scan lines, Accordingly, the potential difference between both ends of the pixel capacitor is set to exceed the threshold voltage. Further, the first switching transistor is rendered conductive in response to a control signal supplied from the other scan line in the horizontal scanning period immediately before assigned to other scanning line located just before the scan line, or more Thus, the potential difference between both ends of the pixel capacitor is set to exceed the threshold voltage. Further, the sampling transistor, while sampling the signal supply period signal line in the horizontal scanning period is equal to the potential of the video signal, the video signal supplied from the signal line to the pixel capacitor, the correction means, The threshold voltage of the drive transistor is detected and written to the pixel capacitor during a signal fixing period in which the signal line is at a constant potential within the horizontal scanning period. Further, the correction means may work with signals fixed period within a horizontal scanning period assigned to other scanning lines to charge the time division manner pixel capacitor in each signal a fixed period to the threshold voltage. Further, the signal fixed period is a horizontal blanking period separating each horizontal scanning periods are sequentially allocated to the respective scan lines with each other, it said correction means, said threshold a time division manner pixel capacitor in each horizontal blanking period Charge to voltage. Further, the When correcting means charges the pixel capacitor in each signal a fixed period, a pixel capacitor electrically from the signal line to close the sampling transistor before the signal line is switched to the potential of the video signal from the constant potential Separate. Further , the drive transistor has an output current dependent on the carrier mobility in addition to the threshold voltage of the channel region, and the correcting means cancels the dependence of the output current on the carrier mobility. , operating at part of the horizontal scanning period, the video signal is taken out an output current from the drive transistor in a state of being sampled, which was negatively fed back to the pixel capacitance, to correct the input voltage.

The present invention also control signal and a column-like signal line for supplying a scan line and the video signal of rows supplying disposed at the intersection, at least a sampling transistor, a picture element capacitance, a drive transistor, and a light emission element, the sampling transistor is rendered conductive in response to the control signal supplied from the scanning line in the horizontal scanning period assigned to the scanning lines, pixel a video signal supplied from the signal line The pixel capacitor applies an input voltage to the gate of the drive transistor according to the sampled video signal, and the drive transistor outputs an output current according to the input voltage during a predetermined light emission period. Is supplied to the light emitting element, and the output current depends on the threshold voltage of the channel region of the drive transistor. In a pixel circuit that emits light with a luminance corresponding to the video signal by the output current supplied from the transistor, the threshold voltage of the drive transistor is detected to cancel the dependency of the output current on the threshold voltage. The correction means includes a first switching transistor and a second switching transistor, and the first switching transistor is the other switching element positioned before the scanning line. conductive according to a control signal supplied from the other scan line in the horizontal scanning period before that is assigned to the scanning lines, than Te, the potential difference across the pixel capacitor is set to exceed the threshold voltage, the The second switching transistor conducts during the horizontal scanning period and charges the pixel capacitor until the potential difference between both ends of the pixel capacitor reaches the threshold voltage. And wherein the door.

Preferably , the first switching transistor is turned on in response to a control signal supplied from the other scanning line in the immediately preceding horizontal scanning period assigned to the other scanning line located immediately before the scanning line, Accordingly, the potential difference between both ends of the pixel capacitor is set to exceed the threshold voltage.

The present invention further control signal and a column-like signal line for supplying a scan line and the video signal of rows supplying disposed at the intersection, at least a sampling transistor, a picture element capacitance, a drive transistor , and a light emission element, the sampling transistor is rendered conductive in response to the control signal supplied from the scanning line in the horizontal scanning period assigned to the scanning lines, the video signal supplied from the signal line Sampling to a pixel capacitor, the pixel capacitor applies an input voltage to the gate of the drive transistor according to the sampled video signal, and the drive transistor outputs an output according to the input voltage during a predetermined light emission period A current is supplied to the light emitting element, and the output current has a dependence on a threshold voltage of a channel region of the drive transistor, In order to cancel the dependence of the output current on the threshold voltage in the pixel circuit that emits light with the luminance corresponding to the video signal by the output current supplied from the live transistor, the drive transistor is preliminarily sampled before the video signal is sampled. A correction means for detecting the threshold voltage of the pixel and writing it in the pixel capacity, the correction means operating within a plurality of horizontal scanning periods assigned to a plurality of scanning lines, and in time division The capacitor is charged to the threshold voltage.

Preferably , the sampling transistor supplies the video signal supplied from the signal line to the pixel capacitor during a signal supply period in which the signal line becomes a potential of a video signal within the horizontal scanning period assigned to the scanning line. while sampling, the correcting means, each signal a fixed period of the signal line in each horizontal scanning period assigned to a plurality of scan lines is constant potential, by detecting the threshold voltage of the drive transistor, time division Thus, the pixel capacitor is charged to the threshold voltage. Further, the signal fixed period is a horizontal blanking period separating each horizontal scanning periods are sequentially allocated to the respective scan lines with each other, it said correction means, said threshold a time division manner pixel capacitor in each horizontal blanking period Charge to voltage. Further, the When correcting means charges the pixel capacitor in each signal a fixed period, by closing the sampling transistor before the signal line is switched to the potential of the video signal from the fixed potential, electrical and pixel capacitor from the signal line Disconnect.

The pixel circuit according to the present invention includes a correcting unit in order to cancel the dependence of the output current supplied to the light emitting element on the threshold voltage. As a feature, this correction means operates during a part of the horizontal scanning period, detects the threshold voltage of the drive transistor in advance, and writes it in the pixel capacitance. Since the threshold voltage correction operation is performed using a part of the horizontal scanning period in which the video signal is sampled with respect to the pixel capacity, the configuration of the correction means can be simplified. Specifically, the correction means according to the present invention includes a first switching transistor that conducts before the horizontal scanning period and resets the pixel capacitance in advance, and conducts the reset during the horizontal scanning period. A second switching transistor that charges the threshold voltage can be used. Therefore, the pixel circuit of the present invention can be composed of the first and second switching transistors constituting the correcting means, the sampling transistor for sampling the video signal, and the drive transistor for driving the light emitting element. The pixel circuit of the present invention, in this manner, can be a total of four transistors, it is possible to reduce the number of elements. Accordingly, it is possible to reduce the number of power lines and the gate lines, by reducing the wire cross-over, it is possible to improve the yield. At the same time , high definition panels can be achieved.

According to the present invention, the first switching transistor described above uses another scanning line positioned before the scanning line assigned to the pixel as a gate line for control. Specifically, the first switching transistor constituting the correcting means of the present invention is connected to the other scanning line during the previous horizontal scanning period assigned to the other scanning line located before the scanning line. Conduction is performed in accordance with the supplied control signal, and thus the pixel capacitance is reset. In this way, by using the scanning line belonging to the previous row as the gate line of the first switching transistor constituting the correcting means, the total number of gate lines can be reduced, thereby reducing the wiring crossover. Leads to improved yield. At the same time , high definition panels can be achieved.

Further, according to the present invention, the correction means incorporated in the pixel circuit operates within a plurality of horizontal scanning periods assigned to the plurality of scanning lines, and charges the pixel capacitance to the threshold voltage in a time division manner. In this way, by dividing the threshold voltage correction operation into a plurality of horizontal scanning periods and dividing it into a plurality of times, the threshold voltage correction time per horizontal scanning period can be set short. Accordingly , it is possible to sufficiently secure the sampling time of the video signal in one horizontal scanning period. Accordingly, even in a high-definition and high-frequency driving panel, a signal potential can be sufficiently written into the pixel capacitor. Therefore , the display panel can be further refined and driven at a high frequency.

It is a block diagram which shows the display apparatus concerning this invention. FIG. 2 is a circuit diagram illustrating a first embodiment of a pixel circuit included in the display device illustrated in FIG. 1. It is the schematic diagram which took out the pixel circuit contained in the display apparatus shown in FIG. 4 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 3. FIG. 4 is a schematic diagram for explaining an operation of the pixel circuit shown in FIG. 3. It is a graph similarly provided for operation | movement description. It is a schematic diagram for explaining the operation in the same manner. It is a graph which shows the operating characteristic of the drive transistor contained in the pixel circuit shown in FIG. 6 is a timing chart showing a second embodiment of the pixel circuit according to the present invention. It is a block diagram which shows the display apparatus concerning this invention. FIG. 11 is a circuit diagram illustrating a third embodiment of a pixel circuit included in the display device illustrated in FIG. 10. It is the schematic diagram which took out the pixel circuit contained in the display apparatus shown in FIG. 13 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 12. It is a block diagram which shows the display apparatus concerning a reference example. It is the schematic diagram which took out the pixel circuit contained in the display apparatus shown in FIG. 16 is a timing chart for explaining the operation of the pixel circuit shown in FIG.

Hereinafter , embodiments of the present invention will be described in detail with reference to the drawings. First , an overall configuration of an active matrix display device having a threshold voltage ( V _th ) correction function will be described with reference to FIG. As shown in the figure, the active matrix display device includes a pixel array 1 as a main part and a peripheral circuit part. The peripheral circuit unit includes a horizontal selector 3, a write scanner 4, a drive scanner 5, a correction scanner 7, and the like. Pixel array 1 includes scan lines WS in rows, and a and column-like signal line SL, and the pixel arranged at the intersection of both the matrix R, G, and B. In order to enable color display, RGB three primary color pixels are prepared, but the present invention is not limited to this. Each pixel R, G, B is constituted by a pixel circuit 2. The signal line SL is driven by the horizontal selector 3. The horizontal selector 3 forms a signal unit and supplies a video signal to the signal line SL. The scanning line WS is scanned by the write scanner 4. Incidentally, in parallel with the scanning lines WS, it is also wired another scan line DS and AZ. The scanning line DS is scanned by the drive scanner 5. The scanning line AZ is scanned by the correction scanner 7. Write scanner 4, the drive scanner 5 and the correction scanner 7 constitute a scanner unit, sequentially scans the rows of pixels in each horizontal scanning period. Each pixel circuit 2, when selected by the scanning line WS, samples the video signal from the signal line SL. Further , when selected by the scanning line DS, the light emitting element included in the pixel circuit 2 is driven in accordance with the sampled video signal. In addition , the pixel circuit 2 performs a predetermined correction operation when scanned by the scanning line AZ.

Pixel array 1 described above, typically, it is formed on an insulating substrate such as glass, and has a flat panel. The transistors constituting each pixel circuit 2 are formed by amorphous silicon thin film transistors (TFTs) or low-temperature polysilicon TFTs. For amorphous silicon TFT, a scanner unit panel and is configured by a different TAB, it is connected to the flat panel by flexible cables. In the case of the low-temperature polysilicon TFT, the signal portion and the scanner portion can be formed of the same low-temperature polysilicon TFT, so that the pixel array portion, the signal portion, and the scanner portion can be integrally formed on the flat panel.

FIG. 2 is a circuit diagram showing a first embodiment of the pixel circuit 2 incorporated in the display device shown in FIG. The pixel circuit 2 includes four thin film transistors Tr ₁ , Tr ₃ , Tr ₄ , Tr _d , one capacitor element (pixel capacitor) C _s , and one light emitting element EL. Transistors Tr _1, Tr _3, Tr _d is an N-channel polysilicon TFT. Only the transistor Tr ₄ is a P-channel polysilicon TFT. One pixel capacitance C _s constitutes the pixel capacitor of the present pixel circuit 2. The light emitting element EL is , for example , a diode type organic EL element having an anode and a cathode. However , the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

Drive transistor Tr _d which is the center of the pixel circuit 2, a gate G is connected to one end of the pixel capacitor C _s, the source S is also connected to the other end of the pixel capacitor C _s. The drain of the drive transistor Tr _d via the second switching transistor Tr _4, are connected to a power supply V _cc. The gate of the switching transistor Tr ₄ is connected to the scanning line DS. The anode of the light emitting element EL is connected to the source S of the drive transistor Tr _d, the cathode is grounded. This ground potential may be expressed as V _cath . The first switching transistor Tr ₃ is interposed between the source S of the drive transistor Tr _d and a predetermined reference potential V _ss . The gate of the transistor Tr ₃ is connected to the scanning line AZ. On the other hand , the sampling transistor Tr ₁ is connected between the signal line SL and the gate G of the drive transistor Tr _d . The gate of the sampling transistor Tr ₁ is connected to the scanning line WS.

In such a configuration, the sampling transistor Tr ₁ becomes conductive in accordance with the control signal WS supplied from the scanning line WS during the horizontal scanning period (1H) assigned to the scanning line WS , and the video signal V supplied from the signal line SL. _sig is sampled to the pixel capacitance C _s . The pixel capacitor C _s applies an input voltage V _gs between the gate G and the source S of the drive transistor Tr _d in accordance with the sampled video signal V _sig . Drive transistor Tr _d during a predetermined light emission period, the output current I _ds according to the input voltage V _gs, supplied to the light emitting element EL. The output current I _ds, to the threshold voltage V _th of the channel region of the drive transistor Tr _d, having any dependency. The light emitting element EL emits light with luminance according to the video signal V _sig by the output current I _ds supplied from the drive transistor Tr _d .

As a feature of the present invention, the pixel circuit 2 includes a correcting unit including a first switching transistor Tr ₃ and a second switching transistor Tr ₄ . In order to cancel the dependence of the output current I _{ds on} the threshold voltage V _th , this correcting means operates in a part of the horizontal scanning period (1H), detects the threshold voltage V _th of the drive transistor Tr _d , and Write in the capacity C _s . The correction means operates in a state where one end by the signal line SL are held at a constant potential V _ss0 of the pixel capacitor C _s conducting the sampling transistor Tr ₁ in the horizontal scanning period (1H), the other of the pixel capacitor C _s The pixel capacitor C _s is charged until the potential difference with respect to the constant potential V _ss0 reaches the threshold voltage V _th from the end. This correction means detects the threshold voltage V _th of the drive transistor Tr _d and writes it to the pixel capacitor C _s in the _{first half} of the horizontal scanning period (1H), while the sampling transistor Tr ₁ is used for the horizontal scanning period (1H). the video signal V _sig that is supplied from the signal line SL in the second half, sampled in the pixel capacitance C _s. The pixel capacitor C _s applies an input voltage V _gs obtained by adding a threshold voltage V _th written in advance to the sampled video signal V _sig between the gate G and the source S of the drive transistor Tr _d . The dependence of the output current I _{ds on} the threshold voltage V _th is cancelled. The correction means includes a first switching transistor Tr ₃ that conducts before the horizontal scanning period (1H) and is set (reset) so that the potential difference between both ends of the pixel capacitor C _s exceeds the threshold voltage V _th , And a second switching transistor Tr ₄ that is conductive during the scanning period (1H) and charges the pixel capacitor C _s until the potential difference between both ends of the pixel capacitor C _s reaches the threshold voltage V _th . Sampling transistor Tr _1, the signal line SL in a horizontal scanning period (1H) to the signal supply period in which the potential of the video signal V _sig, sampling the video signal V _sig that is supplied from the signal line SL into the pixel capacitance C _s On the other hand, the correction means detects the threshold voltage V _th of the drive transistor Tr _d and writes it to the pixel capacitor C _s during the signal fixing period in which the signal line SL is at the constant potential V _ss0 within the horizontal scanning period (1H).

In the present embodiment, the output current I _ds of the drive transistor Tr _d depends on the carrier mobility μ in addition to the threshold voltage V _th of the channel region. In order to cope with this, the correcting means of the present invention operates in a part of the horizontal scanning period (1H) to cancel the dependence of the output current I _{ds on} the carrier mobility μ, and the video signal V _sig is sampled. In this state, the output current I _ds is taken out from the drive transistor Tr _d and negatively fed back to the pixel capacitor C _s to correct the input voltage V _gs .

FIG. 3 is a schematic diagram in which a portion of the pixel circuit 2 is taken out from the display device shown in FIG. For ease of understanding, and the video signal V _sig that is sampled by the sampling transistor Tr _1, the drive transistor Tr _d input voltage V _gs and the output current I _ds of, further, and capacitance component C _oled of the light emitting element EL has It has been added. In addition, scanning lines WS, DS, and AZ connected to the gates of the transistors are also written. The pixel circuit 2 performs a V _th correction operation and the video signal writing operation in the horizontal scanning period. Thus, the pixel circuit 2 can be configured with four transistors Tr ₁ , Tr ₃ , Tr ₄ , Tr _d , one pixel capacitor C _s, and one light emitting element EL. Compared to the pixel circuit incorporating a conventional V _th correction function is one can be reduced at least transistor. As a result, one power supply line and at least one gate line (scanning line) can be reduced, leading to an improvement in panel yield. Further, high definition can be achieved by simplifying the layout of the pixel circuit.

FIG. 4 is a timing chart of the pixel circuit shown in FIGS. Referring to FIG. 4, the operation of the pixel circuit shown in FIG. 2 and FIG. 3, specifically, and will be described in detail. 4, along the time axis T, the scanning lines WS, are a waveform of the control signal applied to the AZ and DS. In order to simplify the notation, the control signals are also denoted by the same reference numerals as the corresponding scanning lines. In addition , the waveform of the video signal V _sig applied to the signal line is also shown along the time axis T. As shown, the video signal V _sig is constant potential V _ss0 next in the first half of each horizontal scanning period H, the signal potential in the second half. Since the transistors Tr ₁ and Tr ₃ are N-channel type, they are turned on when the scanning lines WS and AZ are each at a high level, and turned off when the scanning lines WS and AZ are at a low level. On the other hand , since the transistor Tr ₄ is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. Note that this timing chart, the control signals WS, AZ, with the waveform of the waveform and the video signal V _sig of DS, is represented the potential change of the drive transistor Tr _d potential change and the source S of the gate G of the.

In the timing chart of FIG. 4 , timings T1 to T8 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. Timing diagram represents the control signal WS applied to the pixels of one row, AZ, the waveform of the DS.

At the timing T0 before the field starts, all the control signals WS, AZ, DS are at the low level. Accordingly, the N-channel transistors Tr ₁ and Tr ₃ are in the off state, while only the P-channel transistor Tr ₄ is in the on state. Therefore, the drive transistor Tr _d is because it is connected to the power source V _cc through transistor Tr ₄ in the ON state and supplies the output current I _ds to the light emitting element EL in accordance with the predetermined input voltage V _gs. Therefore, the light emitting element EL emits light at the timing T0. At this time , the input voltage V _gs applied to the drive transistor Tr _d is represented by the difference between the gate potential and (G) source potential (S).

At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. Thus, the transistor Tr ₄ is turned off and the drive transistor Tr _d is disconnected from the power supply V _cc, light emission is stopped into the non-emission period. Once in the timing T1, preparative transistors Tr _1, Tr _3, Tr ₄ are turned off.

Subsequently, at the timing T2, the control signal AZ is rising from a low level to a high level, the switching transistor Tr ₃ is turned on. As a result, the reference potential V _ss is written to the other end of the pixel capacitor C _s and the source S of the drive transistor Tr _d . At this time, since the gate potential of the drive transistor Tr _d high-impedance, following the lowering the source potential (S), the gate potential (G) also decreases.

Thereafter , after the control signal AZ returns to the low level and the switching transistor Tr ₃ is turned off, the control signal WS becomes the high level at the timing Ta, and the sampling transistor Tr ₁ becomes conductive. At this time, the potential appearing on the signal line is set to a predetermined constant potential V _ss0 . Here , V _ss0 and V _ss are set so as to satisfy V _ss0 −V _ss > V _th . V _ss0 −V _ss is the input voltage V _gs of the drive transistor Tr _d . Here, by setting V _gs > V _th , preparation for the subsequent V _th correction operation is performed. In other words, both ends of the pixel capacitor C _s are set to a voltage exceeding V _th at the timing Ta, and the pixel capacitor C _s is reset prior to the V _th correction operation. Further, when the threshold voltage of the light emitting element EL and V _thEL, by setting the V _thEL> V _ss, a reverse bias is applied to the light emitting element EL. This is necessary in order to perform the subsequent V _th correction operation normally.

Subsequently, the switching control signal DS to the low level at the timing T3, by turning on the switching transistor Tr _4, executes a V _th correction. At this time , the potential of the signal line is still held at a constant potential V _ss0 in order to accurately perform V _th correction. When the switching transistor Tr ₄ is turned on, the drive transistor Tr _d is connected to the power source V _cc and the output current I _ds flows. Accordingly, the pixel capacitor C _s is charged, and the source potential (S) connected to the other end rises. On the other hand , the potential (gate potential G) at one end of the pixel capacitor C _s is fixed to V _ss0 . Accordingly, the source potential (S) rises as the pixel capacitor C _s is charged, and the drive transistor Tr _d is cut off when the input voltage V _gs just reaches V _th . When the drive transistor Tr _d is cut off, the source potential (S), as shown in the timing chart, V _ss0 - becomes V _th.

Thereafter, returning the control signal DS to the high level at the timing T4, by turning off the switching transistor Tr _4, V _th correction operation ends. By this correction operation, the voltage of the threshold voltage V _th corresponds to the pixel capacitor C _s is written.

Thus, after the V _th correction at the timing T3 to T4, passed half of one horizontal scanning period (1H), the potential of the signal line changes from V _ss0 to V _sig. As a result , the video signal V _sig is written into the pixel capacitor C _s . Compared to the equivalent capacitance C _oled of the light-emitting device EL, pixel capacitor C _s is sufficiently small. As a result, most of the video signal V _sig is written in the pixel capacitor C _s. Therefore, the voltage V _gs between the gate G and the source S of the drive transistor Tr _d is previously detected retained V _th and the present sampled V _sig levels plus becomes (V _sig + V _th). The gate / source voltage V _gs is as shown in the timing chart of FIG. 4, the V _sig + V _th. Sampling of such video signal V _sig, the control signal WS is performed until time T7 back to low level. That is , the timings T5 to T7 correspond to the sampling period.

Thus, in the present invention, the V _th correction period T3-T4 and the sampling period T5-T7 are included in one horizontal scanning period (1H). During 1H, the sampling control signal WS is at a high level. In the present invention, V _th correction and V _sig writing are performed with the sampling transistor Tr ₁ turned on. Thereby , the configuration of the pixel circuit 2 is simplified.

In this embodiment, in addition to the above-described V _th correction, the mobility μ is also corrected at the same time. However, the present invention is not limited thereto, it is needless to say applicable to the pixel circuit of only a simple V _th correction operation is not performed the mobility μ correction. Further, the pixel circuit 2 of the present embodiment, the drive transistor Tr transistors other than _d is N-channel and P-channel type are mixed, the present invention is not limited thereto, N-channel transistors only Alternatively, it can be configured only with a P-channel transistor.

The mobility μ is corrected at timings T6 to T7. Hereinafter, this point will be described in detail. At timing T6 prior to timing T7 to the end of the sampling period, the control signal DS goes low, the switching transistor Tr ₄ are turned on. Thus, the drive transistor Tr _d is connected to the power supply V _cc, the pixel circuit goes to the light emission period from the non-emission period. Thus, the sampling transistor Tr ₁ is still turned on, and the period T6 in which the switching transistor Tr ₄ enters the on state - at T7, perform mobility correction of the drive transistor Tr _d. That is , in the present embodiment, the mobility correction is performed in the period T6 - T7 in which the rear part of the sampling period overlaps with the head part of the light emission period. In the beginning of the emission period of the mobility correction is performed, the light emitting element EL, because in fact is in a reverse bias state, are not able to emit light. The mobility correction period T6 - At T7, in a state in which the gate G of the drive transistor Tr _d is fixed at the level of the video signal V _sig, the drain current I _ds flows to the drive transistor Tr _d. Here, V _ss0 - V _th <By setting the V _thEL, the light emitting element EL to be placed in a reverse bias state, exhibits a simple capacitance characteristics, rather than diode characteristics. Therefore , the current I _ds flowing through the drive transistor Tr _d is written into a capacitance C = C _s + C _oled that combines both the pixel capacitance C _s and the equivalent capacitance C _oled of the light emitting element EL. Thus, the source potential of the drive transistor Tr _d (S) is rises. In the timing chart of FIG. 4 , this increase is represented by ΔV. The rise ΔV eventually, it means that subtracted from the voltage V _gs between the gate / source held in the pixel capacitor C _s, it will be multiplied by the negative feedback. Thus, by negatively feeding back the output current I _ds of the drive transistor Tr _d also to the input voltage V _gs of the drive transistor Tr _d, it is possible to correct the mobility mu. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T6 - T7.

At timing T7, the control signal WS becomes low level, and the sampling transistor Tr ₁ is turned off. As a result, the gate G of the drive transistor Tr _d is disconnected from the signal line SL. Since the application of the video signal V _sig is cancelled, the gate potential (G) of the drive transistor Tr _d can be increased and increases with the source potential (S). Meanwhile, the pixel capacitance C _s gate / source voltage V _gs held in maintains the value of _{(V sig -ΔV + V th)} . With increasing the source potential (S), the reverse bias state of the light emitting element EL is because it is eliminated, the inflow of the output current I _ds, the light emitting device EL actually starts emitting light. The relationship between the drain current I _{ds and the} gate / source voltage V _gs at this time is given by the following equation 2 by substituting V _sig −ΔV + V _th into V _gs of the previous transistor characteristic equation 1. .
I _ds = kμ ( V _gs −V _th ) ² = kμ ( V _sig −ΔV) ² Equation 2
In the above formula 2, k = (1/2) (W / L) C _ox . It can be seen from the characteristic formula 2 that the term V _th is canceled and the output current I _ds supplied to the light emitting element EL does not depend on the threshold voltage V _th of the drive transistor Tr _d . Basically, the drain current I _ds is determined by the voltage of the video signal V _sig. In other words, the light emitting element EL will emits light at a luminance corresponding to the video signal V _sig. At that time , the negative feedback amount ΔV is subtracted from V _sig . The negative feedback amount ΔV acts to cancel the effect of the mobility μ is located in the coefficient of characteristics equation 2. Accordingly , the drain current I _ds substantially depends only on the video signal V _sig .

Finally, the control signal DS reaches the timing T8 is at a high level, the switching transistor Tr ₄ is turned off, the light emission is finished, the field is completed. Thereafter, proceeds to the next field, again, V _th correction operation, mobility correction operation and light emitting operation will be repeated.

5, the mobility correction period T6 - is a circuit diagram showing a state of the pixel circuit 2 in the T7. As illustrated, the mobility correction period T6 - At T7, the sampling transistor Tr ₁ and the switching transistor Tr ₄ is one that is turned on, the remaining switching transistor Tr ₃ off. In this state, the source potential (S) of the drive transistor Tr ₄ is V _ss0 −V _th . This source potential S is also the anode potential of the light emitting element EL. As described above, V _ss0 - V _th <By setting the V _thEL, the light emitting element EL is placed in a reverse bias state, and to exhibit a simple capacitance characteristics, rather than diode characteristics. Therefore , the current I _ds flowing through the drive transistor Tr _d flows into the combined capacitance C = C _s + C _oled of the pixel capacitance C _s and the equivalent capacitance C _oled of the light emitting element EL. In other words, a part of the drain current I _ds is negatively fed back to the pixel capacitor C _s and the mobility is corrected.

FIG. 6 is a graph of the transistor characteristic equation 2 described above, with I _ds on the vertical axis and V _sig on the horizontal axis. The characteristic formula 2 is also shown below the graph. In the graph of FIG. 6, a characteristic curve is drawn in a state where the pixel 1 and the pixel 2 are compared. The mobility μ of the drive transistor of the pixel 1 is relatively large. Conversely, the mobility μ of the drive transistor included in the pixel 2 is relatively small. Thus, when the drive transistor is formed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels. For example , when the video signal V _sig of the same level is written to both the pixels 1 and 2, the output current I _ds1 ′ flowing through the pixel 1 having the high mobility μ is equal to that of the mobility μ without any mobility correction. A large difference occurs compared to the output current I _ds2 ′ flowing through the small pixel 2. Thus, since a large difference between the output current I _ds due to variation in the mobility μ occurs, so that the impairing the uniformity of the screen.

Therefore , in the present invention, the variation in mobility is canceled by negatively feeding back the output current to the input voltage side. As is clear from the transistor characteristic equation, the drain current I _ds increases as the mobility increases. Therefore, the negative feedback amount ΔV increases as the mobility increases. As shown in the graph of FIG. 6, the negative feedback amount ΔV1 of large pixel 1 of the mobility μ is greater than the negative feedback amount ΔV2 of small pixels 2 mobility. Accordingly , the larger the mobility μ is, the more negative feedback is applied, and the variation can be suppressed. As shown, when applying a correction of the mobility in large pixel 1 mu [Delta] V1, the output current is large drops from I _ds1 'to I _ds1. On the other hand , since the negative feedback amount ΔV2 of the pixel 2 having a small mobility μ is small, the output current I _ds2 ′ does not decrease so much to I _ds2 . Consequently, I _ds1 and I _ds2 become substantially equal, variations in mobility is canceled. Since the cancellation of the variation in mobility is performed in the entire range of V _sig from the black level to the white level , the uniformity of the screen becomes extremely high. In summary, when there mobilities of different pixels 1 and 2, the negative feedback amount ΔV1 of the larger mobility pixel 1 is increased relative to the amount of negative feedback ΔV2 of small pixels 2 mobility. That is , as the mobility increases , ΔV increases and the decrease value of I _ds increases. As a result , the current values of the pixels having different mobilities are made uniform, and variations in mobility can be corrected.

Hereinafter, for reference, with reference to FIG. 7, the numerical analysis of the mobility correction described above. As shown in FIG. 7, in a state where the transistor Tr ₁ and Tr ₄ are turned on, and analyzes by taking the source potential of the drive transistor Tr _d to the variable V. When the source potential of the drive transistor Tr _d the (S) to is V, the drain current I _ds flowing through drive transistors Tr _d, are as shown in Equation 3 below.

Further , due to the relationship between the drain current I _ds and the capacitance C (= C _s + C _oled ) , I _ds = dQ / dt = CdV / dt is established as shown in Equation 4 below.

By substituting equation 3 into equation 4, integrating both sides. Here, the initial state of the source potential V is - and V _th, the mobility correction time - the (T6 T7) and t. Solving this differential equation, the pixel current for the mobility correction time t is given by the following Equation 5.

FIG. 8 is a graph of Expression 5, in which the vertical axis represents the output current I _ds and the horizontal axis represents the video signal V _sig . As parameters , mobility correction periods t = 0 us, 2.5 us and 5 us are set. Further , the mobility μ is also taken as a parameter when the parameter is relatively large, 1.2 μ, and when it is relatively small, 0.8 μ. It can be seen that the mobility variation is sufficiently corrected at t = 2.5 us as compared to the case where the mobility correction is not substantially applied at t = 0 us. Those without mobility correction that there is variation of 40% I _ds is suppressed to less than 10% multiplied by the mobility correction. However, the longer the correction period as t = 5 us, conversely, the variation of the output current I _ds according to the difference of the mobility μ increases. Thus, in order to apply appropriate mobility correction, it is necessary to set t to an optimal value. In the graph shown in FIG. 8, the optimum value is around t = 2.5 us.

Next , a second embodiment of the pixel circuit according to the present invention will be described. In the first embodiment described above, as shown in the timing chart of FIG. 4 , V _th correction and V _sig writing are performed within one horizontal scanning period (1H). Thereby , the number of circuit elements is reduced. However, in the pixel circuit of the first embodiment, or higher definition increasing number of panels of pixels, when raising the field frequency for high image quality, since the horizontal scanning period (1H) becomes short, sufficiently There is a possibility that V _th correction cannot be applied. On the contrary, if the V _th correction period is secured to some extent, the V _sig writing time is compressed, so that it is possible that the video signal cannot be sufficiently written into the pixel capacity. The second embodiment is an improvement of the first embodiment, and can cope with higher definition and higher image quality of the panel. Pixel circuit configuration of the second embodiment is basically the same as the pixel circuit configuration of the first embodiment shown in FIG. However, the operation sequence is different, with reference to the timing chart of FIG. 9 will be described in detail. For easy understanding , the corresponding reference numerals are used for the portions corresponding to those in the timing chart of FIG. 4 showing the operation of the first embodiment.

As apparent from FIG. 9, in this embodiment , the V _th correction period is divided into a plurality of times. As a result , even if the V _th correction period for each time is short, a sufficiently long V _th correction period can be ensured by performing a plurality of times. As a result , the number of circuit elements can be reduced, and further, it is possible to cope with higher definition and higher frequency of the panel. Even if each V _th correction period is as short as several μs, the V _th variation can be sufficiently corrected by summing the correction amounts over a plurality of times.

Hereinafter , the operation of the second embodiment will be described in detail according to the timing chart of FIG. First, the control signal DS to the high level at timing T1, turning off the switching transistor Tr _4. Thereafter, the control signal AZ to the high level at timing T2, turning on the switching transistor Tr _3. As a result , the reference potential V _ss is written to the source potential (S) of the drive transistor Tr _d . At this time , since the gate potential (G) is high impedance , the gate potential (G) also decreases following the drop in the source potential (S).

Thereafter , V _th correction is performed in a time division manner in a horizontal blanking period that divides each horizontal scanning period . In each horizontal blanking period, the signal line potential is set to a constant potential V _ss0 . In the first V _th correction period, the control signal WS becomes high level and the sampling transistor is turned on. At this time , as described above , the potential of the signal line is set to V _ss0 . Here, V _ss0 - V _ss = meets the V _gs> V _th, With V _gs> V _th, to prepare for subsequent V _th correction. Further, when the threshold voltage of the light emitting element EL and V _thEL, by setting the V _thEL> V _ss, a reverse bias is applied to the light emitting element EL. This is necessary to perform the subsequent V _th correction operation and mobility correction operation normally.

Next, while the sampling transistor to the ON state, the switching control signal DS to the low level at timing T31, turns on the switching transistor Tr _4. As a result , the first V _th correction is executed. At this time, the potential of the signal line in order to perform the V _th correction accurately, holds at a constant potential V _ss0. In the drive transistor Tr _d , the output current I _ds flows toward the cutoff when the switching transistor Tr ₄ is turned on. Then, return control signal DS to the high level at timing T41, turns off the switching transistor Tr _4, and ends the first V _th correction. Thereafter , it is desirable to return the control signal WS to the low level and turn off the sampling transistor while the potential of the signal line does not change. However , even if it does not do so, there is no problem in operation.

In the present embodiment , one V _th correction period is set to be within a horizontal blanking period , for example. Therefore, the drive transistor Tr _d is in one V _th correction operation without cutoff, the source potential (S) is held in the middle of the operating point.

When the next horizontal blanking period comes and the potential of the signal line becomes V _ss0 again, the second V _th correction operation is performed. That is , WS is switched to a high level to turn on the sampling transistor Tr ₁ , and the control signal DS is switched to a low level to turn on the switching transistor Tr ₄ , thereby performing the second V _th correction operation. V _th correction period for the second time, are represented by T32-T42. This series of V _th correction operations is performed a plurality of times until the drive transistor is cut off, thereby completing the V _th correction.

In the example shown in the timing chart of FIG. 9, after performing the third V _th correction in the horizontal blanking period located at the head of the horizontal scanning period (1H) assigned to the scanning line WS, the video signal V _sig Is written in the pixel capacitance, and thereafter the mobility μ is corrected. Third V _th correction period is represented by T33-T43. This third V _th correction is completed, the difference between the gate potential (G) and the source potential (S) is set to just V _th.

As described above, in the present embodiment, the correction means incorporated in the pixel circuit 2 operates within a plurality of horizontal scanning periods assigned to a plurality of scanning lines, and the pixel capacitance C _{s is set} to the threshold voltage in a time division manner. Charge to V _th . Sampling transistor, a signal supply period in which the potential V _sig of the signal lines SL in the horizontal scanning period assigned to the scanning lines WS (IH) is a video signal, pixel capacitor a video signal supplied from the signal line SL while sampling the C _s, correction means, the signal fixed period the signal line SL in each horizontal scanning period assigned to a plurality of scan lines WS becomes a constant potential V _ss0, the threshold voltage V _th of the drive transistor Tr _d And the pixel capacitor C _s is charged to the threshold voltage V _th in a time division manner. This signal fixing period is a horizontal blanking period that divides each horizontal scanning period sequentially assigned to each scanning line WS. Correction means in each horizontal blanking period, in a time division manner, to charge the pixel capacitor C _s to the threshold voltage V _th. When the correction means charges the pixel capacitance C _s in the signal fixed period, before the signal line SL is switched to the potential V _sig of the video signal from the constant potential V _ss0, signal pixel capacitor C _s to close the sampling transistor Tr ₁ It is preferable to be electrically disconnected from the line SL.

Figure 10 is a schematic block diagram illustrating a display device according to a third embodiment of the present invention. For ease of understanding, the display device corresponding to those of the first embodiment shown in FIG. 1 are denoted by the corresponding reference number. The difference is that the first embodiment is three scan lines (gate lines) WS, DS, whereas contained AZ, the third embodiment, 2 scan line of the pixel array 1 WS, the DS This is to reduce the number of gate lines. Specifically, the number of scanning lines AZ is reduced, and instead of this, the preceding scanning line WS is used as a substitute for the present scanning line AZ. As a result , one gate line can be reduced and a correction scanner is not required.

FIG. 11 schematically shows a total of two pixel circuits , one for the previous stage and one for the current stage, included in the pixel array of the display device shown in FIG. Configuration of the individual pixel circuits 2, basically, is similar to the first embodiment shown in FIG. 2, the corresponding parts are denoted by the corresponding reference number. Each pixel circuit 2 includes a sampling transistor Tr ₁ , a drive transistor Tr _d , a first switching transistor Tr ₃ , a second switching transistor Tr ₄ , a pixel capacitor C _s , and a light emitting element EL. Difference is the first gate of the switching transistor Tr _3, is that the previous scan line WS is connected. However , since the pixel circuit 2 in the first stage does not have the previous scanning line WS, it needs to be supplied separately.

12, from the pixel array shown in FIG. 11 is a schematic view taken out a pixel circuit of one minute. For ease of understanding, the video signal V _sig sampled by the sampling transistor Tr ₁ , the input voltage V _gs and output current I _{ds of} the drive transistor Tr _d , and the capacitance component C _oled of the light emitting element EL, etc. It has been added. Further, the scanning line of the stage connected to the gate of the sampling transistor Tr ₁ is represented by WS _n , the scanning line of the previous stage connected to the gate of the first switching transistor Tr ₃ is represented by WS _n−1 , and the second switching A scanning line connected to the gate of the transistor Tr ₄ is represented by DS.

FIG. 13 is a timing chart showing the operation of the pixel circuit shown in FIG. In order to facilitate understanding , corresponding reference numerals are used for portions corresponding to the timing chart of the first embodiment shown in FIG. This timing chart along the time axis T, the scanning lines WS _n, are a waveform of the control signal applied to the WS _n-1, DS. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. Note that this timing chart, the control signals WS _n, with the waveform of WS _n-1, DS, the drive transistor Tr and the potential change of the potential change and the source S of the gate G of _d, the video signal V applied to the signal line _{The sig} waveform is also shown. As shown, the video signal V _sig is fixed to a constant potential V _ss0 in the first half of each horizontal scanning period, the signal potential in the second half. Control signal DS at timing T1 becomes a high level, the switching transistor Tr ₄ is turned off, the pixel circuit enters the non-emission state. At timing T2, the control signal WS _n-1 at the previous stage becomes high level, and the switching transistor Tr ₃ is turned on. Thereby , the pixel capacitance C _s is reset, and V _gs > V _th is set. That is , a preparatory operation for V _th correction is performed. At the timing Ta, the control signal WS _n at this stage rises to a high level, and the sampling transistor Tr ₁ becomes conductive. Subsequently, the control signal DS goes low at the timing T3, the second switching transistor Tr ₄ are turned on. Thus, to charge the pixel capacitor C _s while fixing one end of the pixel capacitor C _s to the constant potential V _ss0, writes the V _th. That is , the V _th correction operation is performed. Subsequently, writing the video signal V _sig in the pixel capacitor C _s at time T5. Further, the mobility μ is corrected at timing T6, and the light emission state is entered.

As described above, the third embodiment, in order to cancel the dependence on the threshold voltage V _th of the output current I _ds, written by detecting the threshold voltage V _th of the drive transistor Tr _d in the pixel capacitor C _s Correction means is provided. This correction means includes a first switching transistor Tr ₃ and a second switching transistor Tr ₄ . The first switching transistor Tr ₃ is a horizontal scanning period before that is assigned to other scanning lines WS _n-1 located before the scan line WS _n of the current stage, the other scan lines WS _n-1 conductive according to a control signal WS _n-1 supplied, than Te, the potential difference across the pixel capacitor C _s is set to exceed the threshold voltage V _th. The second switching transistor Tr ₄ is electrically connected to the horizontal scanning period assigned to those stages (IH), until the potential difference across the pixel capacitance C _s (V _gs) is the threshold voltage V _th, the pixel capacitance C Charge _s . In the embodiment shown in FIG. 13, as previous scan line, and a scanning line WS _n-1 located just prior to the scan line WS _n of those stages. Sometimes, instead of this, further can be used the previous scan line WS _n-2 or more previous scan line to a first gate line of the switching transistor Tr _3. As described above, in the present embodiment, by sharing the scanning line WS between two pixels , one gate line can be further reduced, which leads to improvement of the yield of the panel and simplification of the layout. This makes it possible to increase the definition of the panel.

Figure 14 is a block diagram showing a reference example of the pixel circuit. For ease of understanding, the parts corresponding to the first embodiment shown in FIG. 2 are denoted by the corresponding reference number. The difference is that this reference example performs the V _th correction operation before the horizontal scanning period. For this reason , one more switching transistor Tr ₂ is required in addition to the switching transistor Tr _{3 in} preparation for V _th correction. One transistor Tr ₃ resets the source side terminal of the pixel capacitor C _s , while the additional transistor Tr ₂ resets the gate side terminal of the pixel capacitor C _s . To drive additional switching transistor Tr _2, requires additional scanning lines AZ1 and additional correcting scanner 71. In the present invention, by performing the setting of the gate terminal of the pixel capacitor C _s in the horizontal scanning period, eliminating the need for transistor Tr _2. In the transistor Tr ₂ , the power supply voltage V _ss1 is written in the gate G. On the other hand , in the present invention, the fixed potential V _ss0 supplied from the signal line SL is written during the horizontal scanning period.

The operation of the reference example shown in FIG. 14 will be described below. The active matrix display device includes a pixel array 1 serving as a main portion, and a circuit portion of the peripheral. The peripheral circuit unit includes a horizontal selector 3, a write scanner 4, a drive scanner 5, a first correction scanner 71, a second correction scanner 72, and the like. Pixel array 1 is composed of the scanning lines WS in rows, and columns of the signal line SL, and the pixel circuits 2 arranged in a matrix form at the intersection of both. In the figure, for ease of understanding, an enlarged view of only one pixel circuit 2. The signal line SL is driven by the horizontal selector 3. The horizontal selector 3 forms a signal unit and supplies a video signal to the signal line SL. The scanning line WS is scanned by the write scanner 4. Incidentally, in parallel with the scanning lines WS, another scan line DS, AZ1 and AZ2 are also wired. The scanning line DS is scanned by the drive scanner 5. The scanning line AZ1 is scanned by the first correction scanner 71. The scanning line AZ2 is scanned by the second correction scanner 72. Write scanner 4, the drive scanner 5, a first correcting scanner 71 and a second correcting scanner 72 constitute a scanner unit, for each horizontal scanning period, and sequentially scans the rows of pixels. Each pixel circuit 2, when selected by the scanning line WS, samples the video signal from the signal line SL. Further, when selected by the scanning line DS, the light emitting element EL included in the pixel circuit 2 is driven in accordance with the sampled video signal. In addition, the pixel circuit 2, when scanned by the scanning lines AZ1, AZ2, performs predetermined correction operation.

The pixel circuit 2 includes five thin film transistors Tr ₁ to Tr ₄ and Tr _d , one capacitor element (pixel capacitor) C _s , and one light emitting element EL. Transistors Tr ₁ ~ Tr ₃ and Tr _d is an N-channel polysilicon TFT. Only the transistor Tr ₄ is a P-channel type polysilicon TFT. One pixel capacitor C _s forms a capacitor portion of the pixel circuit 2. The light emitting element EL is , for example , a diode type organic EL element having an anode and a cathode.

Drive transistor Tr _d which is the center of the pixel circuit 2, a gate G is connected to one end of the pixel capacitor C _s, the source S is also connected to the other end of the pixel capacitor C _s. The gate G of the drive transistor Tr _d via a switching transistor Tr _2, and is connected to another reference potential V _ss1. The drain of the drive transistor Tr _d via the switching transistor Tr _4, are connected to a power supply V _cc. The gate of the switching transistor Tr ₂ is connected to the scan line AZ1. The gate of the switching transistor Tr ₄ is connected to the scanning line DS. The anode of the light emitting element EL is connected to the source S of the drive transistor Tr _d, the cathode is grounded. This ground potential may be expressed as V _cath . Further , the switching transistor Tr ₃ is interposed between the source S of the drive transistor Tr _d and a predetermined reference potential V _ss2 . The gate of the transistor Tr ₃ is connected to the scanning line AZ2. On the other hand , the sampling transistor Tr ₁ is connected between the signal line SL and the gate G of the drive transistor Tr _d . The gate of the sampling transistor Tr ₁ is connected to the scanning line WS.

In such a configuration, the sampling transistor Tr ₁ conducts according to the control signal WS supplied from the scanning line WS during a predetermined sampling period, and samples the video signal V _sig supplied from the signal line SL into the pixel capacitor C _s . . The pixel capacitor C _s applies an input voltage V _gs between the gate G and the source S of the drive transistor in accordance with the sampled video signal V _sig . The drive transistor Tr _d supplies an output current I _ds corresponding to the input voltage V _gs to the light emitting element EL during a predetermined light emission period. Note that the output current (drain current) I _ds has a dependency on the carrier mobility μ and the threshold voltage V _th of the channel region of the drive transistor Tr _d. The light emitting element EL emits light with luminance according to the video signal V _sig by the output current I _ds supplied from the drive transistor Tr _d .

The pixel circuit 2 includes correction means including switching transistors Tr ₂ to Tr _{4. In} order to cancel the dependency of the output current I _{ds on} the carrier mobility μ, the pixel circuit 2 is previously set in the pixel capacitance C _s at the beginning of the light emission period. The held input voltage V _gs is corrected. Specifically, the correcting means ( Tr ₂ to Tr ₄ ) operate in a part of the sampling period according to the control signals WS and DS supplied from the scanning lines WS and DS, and the video signal V _sig is sampled. In this state, the output current I _ds is taken out from the drive transistor Tr _d and negatively fed back to the pixel capacitor C _s to correct the input voltage V _gs . Further, the correcting means ( Tr ₂ to Tr ₄ ) detects the threshold voltage V _th of the drive transistor Tr _d in advance of the sampling period in order to cancel the dependence of the output current I _{ds on} the threshold voltage V _th . In addition , the detected threshold voltage V _th is added to the input voltage V _gs .

Drive transistor Tr _d, while the drain of N-channel transistor is connected to the power supply V _cc side, the source S is connected to the light emitting element EL side. In this case, the correction means described above takes out the output current I _ds from the drive transistor Tr _d at the beginning of the light emission period that overlaps the latter part of the sampling period, and negatively feeds back to the pixel capacitor C _s side. At this time , the correcting means causes the output current I _ds extracted from the source S side of the drive transistor Tr _d at the beginning of the light emission period to flow into the capacitance of the light emitting element EL. Specifically, the light emitting element EL, a diode-type light-emitting device having an anode and a cathode, while the anode side is connected to the source S of the drive transistor Tr _d, cathode side is grounded. With this configuration, the correcting means ( Tr ₂ to Tr ₄ ) sets the anode / cathode of the light emitting element EL in a reverse bias state in advance, and outputs the output current I _ds extracted from the source S side of the drive transistor Tr _d. When the LED flows into the light emitting element EL, the diode type light emitting element EL is caused to function as a capacitive element. Incidentally, the correcting means can adjust the time width t extracting an output current I _ds of the drive transistor Tr _d within the sampling period, thereby to optimize the negative feedback amount of the output current I _ds to the pixel capacitor C _s ing.

FIG. 15 is a schematic diagram of the pixel circuit portion extracted from the display device shown in FIG. For ease of understanding, and the video signal V _sig that is sampled by the sampling transistor Tr _1, the drive transistor Tr _d input voltage V _gs and the output current I _ds of, further, and capacitance component C _oled of the light emitting element EL has It has been added. Hereinafter , the basic operation of the pixel circuit 2 will be described with reference to FIG.

FIG. 16 is a timing chart of the pixel circuit shown in FIG. Referring to FIG. 16, the operation of the pixel circuit shown in FIG. 15, more specifically, and will be described in detail. 16, along the time axis T, are a waveform of the control signals applied to the scanning lines WS, AZ1, AZ2 and DS. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. Since the transistors Tr ₁ , Tr ₂ , and Tr ₃ are N-channel type, they are turned on when the scanning lines WS, AZ 1, and AZ 2 are at a high level and turned off when they are at a low level. On the other hand , since the transistor Tr ₄ is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. Note that this timing chart, with the control signals WS, AZ1, AZ2, DS waveform is represented the potential change of the drive transistor Tr _d potential change and the source S of the gate G of the.

In the timing chart of FIG. 16 , timings T1 to T8 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. The timing chart shows the waveforms of the control signals WS, AZ1, AZ2, DS applied to the pixels for one row.

At timing T0 before the field starts, all control line numbers WS, AZ1, AZ2, DS are at a low level. Accordingly, the N-channel transistors Tr ₁ , Tr ₂ , Tr ₃ are in the off state, while only the P-channel transistor Tr ₄ is in the on state. Therefore, the drive transistor Tr _d, via the transistor Tr ₄ in the ON state, because it is connected to the power source V _cc, and supplies the output current I _ds to the light emitting element EL in accordance with the predetermined input voltage V _gs . Therefore, the light emitting element EL emits light at the timing T0. At this time , the input voltage V _gs applied to the drive transistor Tr _d is represented by the difference between the gate potential (G) and the source potential (S).

At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. Thus, the transistor Tr ₄ is turned off and the drive transistor Tr _d is disconnected from the power supply V _cc, light emission is stopped into the non-emission period. Therefore, at the timing T1, all the transistors Tr ₁ to Tr ₄ are turned off.

Subsequently , at timing T2, since the control signals AZ1 and AZ2 are at a high level, the switching transistors Tr ₂ and Tr ₃ are turned on. As a result, the gate G of the drive transistor Tr _d is connected to the reference potential V _ss1 , and the source S is connected to the reference potential V _ss2 . Here, V _ss1 - V _ss2> meets the V _th, V _ss1 - the V _ss2 = V _gs> V _th to it, to prepare for the place is V _th correction in the subsequent timing T3. In other words, the period T2 - T3 corresponds to a reset period of the drive transistor Tr _d. Further, when the threshold voltage of the light emitting element EL is V _thEL , V _thEL > V _ss2 is set. Thereby, a minus bias is applied to the light emitting element EL, and a so-called reverse bias state is obtained. This reverse bias state is necessary for normal V _th correction operation and mobility correction operation to be performed later.

Timing was T3, the control signal AZ2 at low level, and, and the control signal DS is also low immediately. Thereby , the transistor Tr ₃ is turned off, while the transistor Tr ₄ is turned on. As a result , the drain current I _ds flows into the pixel capacitor C _s and the V _th correction operation is started. At this time, the gate G of the drive transistor Tr _d is held in V _ss1, flows current I _ds to the drive transistor Tr _d is cut off. When cut off , the source potential (S) of the drive transistor Tr _d becomes V _ss1 −V _th . Drain current returned to the high level again a control signal DS at the timing T4 after the cut-off and turns off the switching transistor Tr _4. Furthermore, the control signal AZ1 is also returned to the low level, the switching transistor Tr ₂ is also turned off. As a result, V _th is held and fixed in the pixel capacitor C _s . Thus, the timing T3 - T4 is a period for detecting the threshold voltage V _th of the drive transistor Tr _d. Here, this detection period T3 - are the T4, it is referred to as V _th correction period.

Thus, after the V _th correction switches the control signal WS to the high level at a timing T5, writing the video signal V _sig in the pixel capacitor C _s to turn on the sampling transistor Tr _1. Compared to the equivalent capacitance C _oled of the light-emitting device EL, pixel capacitor C _s is sufficiently small. As a result, most of the video signal V _sig is written in the pixel capacitor C _s. To be precise, the difference V _sig of V _sig against the V _ss1 - V _ss1 is written to the pixel capacitor C _s. Accordingly, the voltage V _gs between the gate G and the source S of the drive transistor Tr _d is a level _obtained by adding V _th previously detected and held to V _sig −V _ss1 sampled this time , ( V _sig −V _ss1 + V _th ). Since, for purposes of explanation simplicity, when V _ss1 = 0 volts, the gate / source voltage V _gs is as shown in the timing chart of FIG. 7, a V _sig + V _th. Sampling of such video signal V _sig, the control signal WS is performed until time T7 back to low level. That is, the timing T5 - T7 corresponds to the sampling period.

At timing T6 prior to timing T7 to the end of the sampling period, the control signal DS goes low, the switching transistor Tr ₄ are turned on. Thus, the drive transistor Tr _d is connected to the power supply V _cc, the pixel circuit goes to the light emission period from the non-emission period. Thus, the sampling transistor Tr ₁ is still turned on, and the period T6 in which the switching transistor Tr ₄ enters the on state - at T7, perform mobility correction of the drive transistor Tr _d. That is , in the present embodiment, the mobility correction is performed in the period T6 - T7 in which the rear part of the sampling period overlaps with the head part of the light emission period. In the beginning of the emission period of the mobility correction is performed, the light emitting element EL, because in fact is in a reverse bias state, are not able to emit light. The mobility correction period T6 - At T7, in a state in which the gate G of the drive transistor Tr _d is fixed at the level of the video signal V _sig, the drain current I _ds flows to the drive transistor Tr _d. Here, V _ss1 - V _th <By setting the V _thEL, the light emitting element EL to be placed in a reverse bias state, exhibits a simple capacitance characteristics, rather than diode characteristics. Therefore , the current I _ds flowing through the drive transistor Tr _d is written into a capacitance C = C _s + C _oled that combines both the pixel capacitance C _s and the equivalent capacitance C _oled of the light emitting element EL. Thus, the source potential of the drive transistor Tr _d (S) is rises. In the timing chart of FIG. 16 , this increase is represented by ΔV. The rise ΔV eventually, it means that subtracted from the voltage V _gs between the gate / source held in the pixel capacitor C _s, it will be multiplied by the negative feedback. Thus, by negatively feeding back the output current I _ds of the drive transistor Tr _d also to the input voltage V _gs of the drive transistor Tr _d, it is possible to correct the mobility mu. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T6 - T7.

At timing T7, the control signal WS becomes low level, and the sampling transistor Tr ₁ is turned off. As a result, the gate G of the drive transistor Tr _d is disconnected from the signal line SL. Since the application of the video signal V _sig is cancelled, the gate potential (G) of the drive transistor Tr _d can be increased and increases with the source potential (S). Meanwhile, the pixel capacitance C _s gate / source voltage V _gs held in maintains the value of _{(V sig -ΔV + V th)} . With increasing the source potential (S), the reverse bias state of the light emitting element EL is because it is eliminated, the inflow of the output current I _ds, the light emitting device EL actually starts emitting light. The relationship between the drain current I _{ds and the} gate / source voltage V _gs at this time is given by the following equation 2 by substituting V _sig −ΔV + V _th into V _gs of the previous transistor characteristic equation 1. .
I _ds = kμ ( V _gs −V _th ) ² = kμ ( V _sig −ΔV) ² Equation 2
In the above formula 2, k = (1/2) (W / L) C _ox . It can be seen from the characteristic formula 2 that the term V _th is canceled and the output current I _ds supplied to the light emitting element EL does not depend on the threshold voltage V _th of the drive transistor Tr _d . Basically, the drain current I _ds is determined by the voltage of the video signal V _sig. In other words, the light emitting element EL will emits light at a luminance corresponding to the video signal V _sig. At that time , the negative feedback amount ΔV is subtracted from V _sig . The negative feedback amount ΔV acts to cancel the effect of the mobility μ is located in the coefficient of characteristics equation 2. Accordingly , the drain current I _ds substantially depends only on the video signal V _sig .

Finally, the control signal DS reaches the timing T8 is at a high level, the switching transistor Tr ₄ is turned off, the light emission is finished, the field is completed. Thereafter, proceeds to the next field, again, V _th correction operation, mobility correction operation and light emitting operation will be repeated.

1 ... pixel array, 2 ... pixel circuit, 3 ... horizontal selector, 4 ... write scanner, 5 ... drive scanner, 7 ... correction scanner, Tr ₁ ... sampling transistor , Tr ₃ · · · switching transistor, Tr ₄ · · · switching transistor, Tr _d · · · drive transistor, EL · · · emitting element, C _s · · · capacitive element (pixel capacitor)

Claims (8)

Including at least a sampling transistor, a drive transistor, a pixel capacitor, and a light emitting element;
In the sampling transistor, the gate is connected to the scanning line, one of the source and the drain is connected to the signal line, and the other of the source and the drain is connected to the gate of the drive transistor,
In the drive transistor, one of the source and the drain is connected to one end of the light emitting element,
The pixel capacitance is a pixel circuit connected between the gate of the drive transistor and one of the source and drain,
After the other of the source and the drain of the drive transistor is disconnected from the power supply, the difference between the reference potential is supplied to the gate threshold voltage is greater than a predetermined potential signal line or rads live transistors of the drive transistor, and, of the drive transistor A reference potential is supplied to one of the source and the drain ,
After that, in a state where the constant potential is supplied from the signal line to the gate of the drive transistor, one of the source and the drain of the drive transistor is caused by a current flowing through the drive transistor connected to the power source. Bring the potential closer to the constant potential,
Next, a pixel circuit in which a signal potential is supplied from the signal line to the gate of the drive transistor.   While the signal potential is supplied from the signal line to the gate of the drive transistor, the current flowing through the drive transistor having the other of the source and the drain connected to the power source causes the potential of one of the source and the drain of the drive transistor to be The pixel circuit according to claim 1, wherein the pixel circuit is brought close to a signal potential. It has scanning lines arranged in rows, signal lines arranged in columns, and pixel circuits arranged in a matrix,
The pixel circuit includes at least a sampling transistor, a drive transistor, a pixel capacitor, and a light emitting element,
In the sampling transistor, the gate is connected to the scanning line, one of the source and the drain is connected to the signal line, and the other of the source and the drain is connected to the gate of the drive transistor,
In the drive transistor, one of the source and the drain is connected to one end of the light emitting element,
The pixel capacitance is a display device connected between the gate of the drive transistor and one of the source and drain,
After the other of the source and the drain of the drive transistor is disconnected from the power supply, the difference between the reference potential is supplied to the gate threshold voltage is greater than a predetermined potential signal line or rads live transistors of the drive transistor, and, of the drive transistor A reference potential is supplied to one of the source and the drain ,
After that, in a state where the constant potential is supplied from the signal line to the gate of the drive transistor, one of the source and the drain of the drive transistor is caused by a current flowing through the drive transistor connected to the power source. Bring the potential closer to the constant potential,
Next, a display device in which a signal potential is supplied from a signal line to the gate of the drive transistor.   While the signal potential is supplied from the signal line to the gate of the drive transistor, the current flowing through the drive transistor having the other of the source and the drain connected to the power source causes the potential of one of the source and the drain of the drive transistor to be The display device according to claim 3, wherein the display device is brought close to a signal potential. Including at least a sampling transistor, a drive transistor, a pixel capacitor, and a light emitting element;
In the sampling transistor, the gate is connected to the scanning line, one of the source and the drain is connected to the signal line, and the other of the source and the drain is connected to the gate of the drive transistor,
In the drive transistor, one of the source and the drain is connected to one end of the light emitting element,
The pixel capacitance is a driving method of a pixel circuit connected between a gate of a drive transistor and one of a source and a drain,
After disconnecting the other of the source and the drain of the drive transistor from a power source, a difference between the reference potential supplying a threshold voltage greater than a predetermined potential of the drive transistor to the gate signal line or rads live transistor, and a source of the drive transistor And supply a reference potential to one of the drain ,
After that, in a state where the constant potential is supplied from the signal line to the gate of the drive transistor, one of the source and the drain of the drive transistor is caused by a current flowing through the drive transistor connected to the power source. Bring the potential closer to the constant potential,
Next, a driving method of a pixel circuit in which a signal potential is supplied from a signal line to a gate of a drive transistor.   While the signal potential is supplied from the signal line to the gate of the drive transistor, the potential of one of the source and drain of the drive transistor is changed by the current flowing through the drive transistor connected to the power source. The pixel circuit driving method according to claim 5, wherein the pixel circuit is brought close to a signal potential. It has scanning lines arranged in rows, signal lines arranged in columns, and pixel circuits arranged in a matrix,
The pixel circuit includes at least a sampling transistor, a drive transistor, a pixel capacitor, and a light emitting element,
In the sampling transistor, the gate is connected to the scanning line, one of the source and the drain is connected to the signal line, and the other of the source and the drain is connected to the gate of the drive transistor,
In the drive transistor, one of the source and the drain is connected to one end of the light emitting element,
The pixel capacitance is a driving method of a display device connected between a gate of a drive transistor and one of a source and a drain,
After disconnecting the other of the source and the drain of the drive transistor from a power source, a difference between the reference potential supplying a threshold voltage greater than a predetermined potential of the drive transistor to the gate signal line or rads live transistor, and a source of the drive transistor And supply a reference potential to one of the drain ,
After that, in a state where the constant potential is supplied from the signal line to the gate of the drive transistor, one of the source and the drain of the drive transistor is caused by a current flowing through the drive transistor connected to the power source. Bring the potential closer to the constant potential,
Next, a method for driving a display device, in which a signal potential is supplied from a signal line to a gate of a drive transistor.   While the signal potential is supplied from the signal line to the gate of the drive transistor, the potential of one of the source and drain of the drive transistor is changed by the current flowing through the drive transistor connected to the power source. The method for driving a display device according to claim 7, wherein the display device is brought close to a signal potential.

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