JP2003271095A - Driving circuit for current control element and image display device - Google Patents

Driving circuit for current control element and image display device

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Publication number
JP2003271095A
JP2003271095A JP2002070730A JP2002070730A JP2003271095A JP 2003271095 A JP2003271095 A JP 2003271095A JP 2002070730 A JP2002070730 A JP 2002070730A JP 2002070730 A JP2002070730 A JP 2002070730A JP 2003271095 A JP2003271095 A JP 2003271095A
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JP
Japan
Prior art keywords
transistor
current control
drive
drive circuit
gate
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002070730A
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Japanese (ja)
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JP3613253B2 (en
Inventor
Koichi Iguchi
Isao Sasaki
康一 井口
勇男 佐々木
Original Assignee
Nec Corp
日本電気株式会社
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Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP2002070730A priority Critical patent/JP3613253B2/en
Priority claimed from PCT/JP2003/002578 external-priority patent/WO2003075256A1/en
Publication of JP2003271095A publication Critical patent/JP2003271095A/en
Application granted granted Critical
Publication of JP3613253B2 publication Critical patent/JP3613253B2/en
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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0847Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements

Abstract

[PROBLEMS] To eliminate the influence of variations in threshold characteristics of drive transistors in a drive circuit of a current control element. A driving circuit for a disclosed current control element includes:
A drive transistor 6 and a current control element 7 connected in series between the power supply line 1 and the ground line 2, and a connection point between the drive transistor 6 and the current control element 7 and a gate electrode of the drive transistor 6. And a selection gate transistor 4 connected between the signal line 3 and the gate electrode of the driving transistor 6, and the selection gate transistor 4 is turned on during the selection period from the signal line 3 to the first After the signal voltage is input and the signal charge written in the storage capacitor 5 is discharged through the driving transistor 6, the second signal is supplied from the signal line 3.
The signal voltage is input and held in the holding capacitor 5, and the selection gate transistor 4 is turned off and a current is passed through the drive transistor 6 to the current control element 7 during the non-selection period.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an organic EL (Elec
The present invention relates to a current control element drive circuit for causing a current control element such as a tro Luminescence) element to emit light, and an image display device using the same.

[0002]

2. Description of the Related Art In an image display device such as an organic EL display in which a large number of drive circuits for light emitting elements (current control elements) driven by current control are arranged in a plane, each current control is performed. The current flowing through the element is controlled so that the current corresponding to the display brightness of the current control element flows from the signal line to the storage capacitor between the gate and source of the drive transistor through the selection gate transistor in the drive circuit. This is performed by writing programmed signal charges and holding the signal charges during the display period.

FIG. 15 shows the configuration of a drive circuit for a current control element of the first conventional example, which is disclosed in Japanese Patent Laid-Open No. 8-23.
It is disclosed in Japanese Patent No. 4683. As shown in FIG. 15, the drive circuit of the current control element of this conventional example is as follows.
A select gate transistor 14 connected between the power supply line 11, the ground line 12 and the signal line 13, a storage capacitor 15;
It is composed of a drive transistor 16, a current control element 17, and a parasitic capacitance 18. Select gate transistor 14
Is an N-channel field effect transistor, the gate electrode is connected to a selection line (not shown), the drain electrode is connected to the signal line 13, and the source electrode is connected to the drive transistor 1.
6 gate electrodes. The storage capacitor 15 is connected between the gate electrode of the drive transistor 16 and the power supply line 11. The drive transistor 16 is composed of a P-channel field effect transistor, has a gate electrode connected to the source electrode of the selection gate transistor 14 and one end of the storage capacitor 15, a source electrode connected to the power supply line 11, and a drain electrode connected to the current control element 17. Connected to the anode of. The current control element 17 is connected between the drain electrode of the drive transistor 16 and the ground line 12, and emits light with a brightness corresponding to the current IL of the drive transistor 16. The parasitic capacitance 18 is a parasitic capacitance at both ends of the current control element 17.

In the conventional drive circuit of the current control element shown in FIG. 15, the selection signal output from the selection gate driver (not shown) in the row direction during the selection period is applied to the selected row. A signal voltage output from a drive driver (not shown) in the column direction by being applied to the gate electrode of the select gate transistor 14 of each drive circuit and turning on the select gate transistor 14 of the corresponding row. VDATA is applied between the gate and source of the drive transistor 16 via the selected signal line 13. When the drive circuit is switched from the selected period to the non-selected period,
The selection gate transistor 14 changes from the conductive state to the non-conductive state. At this time, since the gate-source voltage VGS of the driving transistor 16 is held by the holding capacitor 15, the driving transistor 16 keeps the current IDS corresponding to the written signal voltage even during the non-selection period (holding period).
Is continuously supplied to the current control element 17.

FIG. 16 shows the IDS-VGS characteristics when the characteristics of the drive transistor vary. The IDS-VGS characteristics of the drive transistor vary depending on the individual transistor, and the threshold variation in particular is large. Therefore, the same signal voltage VDA is used as the gate-source voltage VGS of the driving transistor.
Even when TA is applied, the output current IDS of the drive transistor is IL1, I
It varies like L2 or IL3. Since the drain-source current IDS flows through the current control element 17 as it is, even if the same signal voltage VDATA is input to each drive circuit, the current flowing through the current control element 17 varies. Further, even during the non-selection period, the gate-source voltage VGS of the drive transistor 16 remains at the storage capacitor 15
Therefore, even if the signal voltage VDATA is the same,
Different currents continue to flow in the current control element 17 depending on the drive circuit. Therefore, even if the same signal voltage is written, there is a problem in that the emission brightness of each current control element varies.

As a method for preventing such a variation in the drive current caused by a variation in the threshold value of the drive transistor, the method described in the following documents has been proposed. SID '99, pp.11-14; A Polysilicon Active Matrix Org
anic Light Emitting Diode Display with Integrated D
rivers, R.dawson et al

FIG. 17 shows the configuration of a drive circuit for the current control element of the second conventional example. As shown in FIG. 17, the drive circuit of the current control element of this conventional example has a power supply line 1 as shown in FIG.
1, the selection gate transistor 14A, the storage capacitor 15, the drive transistor 16, the current control element 17, and the parasitic capacitance 18 which are connected between the ground line 12, the ground line 12, and the signal line 13.
And a decoupling capacitor 19 and switching transistors 20 and 21. The selection gate transistor 14A is formed of a P-channel field effect transistor, has a gate electrode connected to a selection line (not shown), a source electrode connected to the signal line 13, and a drain electrode connected to one end of the decoupling capacitor 19. There is. Storage capacity 15
Are connected between the gate electrode of the drive transistor 16 and the power supply line 11. The drive transistor 16 is a P-channel field effect transistor, and has a gate electrode connected to the other end of the decoupling capacitor 19 and one end of the storage capacitor 15, a source electrode connected to the power supply line 11, and a drain electrode connected to the switching transistor 21. It is connected to the source electrode.

The current control element 17 is connected between the drain electrode of the switching transistor 21 and the ground line 12, and emits light with a brightness corresponding to the current of the drive transistor 16. The parasitic capacitance 18 is a parasitic capacitance at both ends of the current control element 17. The decoupling capacitor 19 is connected between the drain electrode of the selection gate transistor 14A and the gate electrode of the drive transistor 16 and separates them from each other in terms of direct current. The switch transistor 20 includes a P-channel field effect transistor, a gate electrode thereof is connected to a reset line (not shown), a source electrode thereof is connected to a gate electrode of the driving transistor 16, and a drain electrode thereof is connected to a drain electrode of the driving transistor 16. Has been done. The switching transistor 21 is composed of a P-channel field effect transistor, has a gate electrode connected to the reset line, a source electrode connected to the drain electrode of the drive transistor 16, and a drain electrode connected to one end of the current control element 17.

FIG. 18 is a timing chart for explaining the operation of the drive circuit for the second conventional current control element. The operation of the drive circuit for the current control element of the second conventional example will be described below with reference to FIGS. 17 and 18. In the drive circuit of the current control element of this conventional example, it is necessary to discharge the parasitic capacitance 18 of the current control element 17 and set the drain voltage VD of the drive transistor 16 to the ground line potential before the selection period starts. In addition, the voltage of the signal line 13 is set to the voltage VD of the power line 11.
Leave it as D. When the selection period is started, a selection signal in the row direction is applied to the selection line to turn on the selection gate transistor 14A, and a reset signal is applied from the reset driver (not shown) to the reset line to turn on the switching transistor 20. When the switching transistor 21 is turned on and the switching transistor 21 is turned off, discharge of the charge accumulated in the storage capacitor 15 is started in a state where the gate electrode and the drain electrode of the drive transistor 16 are electrically connected. In this state, when a sufficient time has passed, the gate voltage VG of the drive transistor 16 drops to the threshold value VT. After that, the switching transistor 20 is turned off and the gate electrode of the drive transistor 16 is floated.

Next, when the input voltage from the signal line 13 is switched from the voltage VDD of the power supply line 11 to the write voltage VDATA, the gate-drain voltage VGS of the drive transistor 16 changes to the capacitance value C of the decoupling capacitance 19.
By the capacitance division of D and the capacitance value CS of the storage capacitor 15, it is given by the following equation. VGS = VG-VDD = VT + CD * (VDATA-VDD) / (CS + CD) (1) Generally, the drain-source current value of a transistor is
It is expressed by the function of (VGS-VT), but as can be seen from the above equation, (VGS-VT) is determined by VDATA, so
Even if the threshold value of the driving transistor 16 varies, it is corrected.

However, in this conventional example, not only four transistors are required for one pixel, but also decoupling capacitance is required in addition to the storage capacitance. Therefore, there is a problem in that the aperture ratio of the pixel is lowered and it becomes difficult in the manufacturing process. Further, when the value of the decoupling capacitance CD is small, the write voltage VDATA must be made larger, so it is desirable that CD> CS, but for that purpose, the decoupling capacitance C
There is also a problem that the chip area for forming D becomes large. Furthermore, there is a drawback in that it takes time to discharge the parasitic capacitance of the current control element before the selection period, and the operation of discharging the parasitic capacitance becomes complicated.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances and has a minimum element configuration,
An object of the present invention is to provide a drive circuit for a current control element and an image display device capable of correcting the threshold variation of the drive transistor.

[0013]

In order to solve the above-mentioned problems, the invention according to claim 1 relates to a drive circuit for a current control element, which is connected in series between a first power supply line and a second power supply line. Between the drive transistor and the current control element, the storage capacitor connected between the connection point of the drive transistor and the current control element and the gate electrode of the drive transistor, and the signal line and the gate electrode of the drive transistor. And a selection gate transistor connected to the selection circuit, the selection gate transistor is turned on during the selection period of the drive circuit to input a first signal voltage from the signal line, and the signal charge written in the storage capacitor is supplied to the storage capacitor. After discharging through the drive transistor, the second signal voltage is input from the signal line and held in the storage capacitor, and the selection gate transistor is held in the non-selection period of the drive circuit. Clear the data through the driving transistor is characterized by supplying a current to said current control element.

The invention according to claim 2 relates to the drive circuit for the current control element according to claim 1, wherein the reset signal voltage is input to the signal line at the beginning of the selection period of the drive circuit. It is characterized in that the electric charge accumulated in the storage capacitor and the parasitic capacitance of the current control element is reset.

The invention according to claim 3 relates to the drive circuit for the current control element according to claim 1, wherein the drive transistor is turned on at the beginning of the selection period of the drive circuit, and the first power supply line is turned on. Is used as a reset signal voltage to reset the charges accumulated in the storage capacitor and the parasitic capacitance of the current control element.

The invention according to claim 4 relates to the drive circuit of the current control element according to any one of claims 1 to 3, wherein the select gate transistor and the drive transistor are N-channel field effect transistors. It is characterized by becoming.

The invention according to claim 5 relates to the drive circuit for the current control element according to any one of claims 1 to 3, wherein the select gate transistor and the drive transistor are P-channel field effect transistors. It is characterized by becoming.

According to a sixth aspect of the present invention, there is provided a drive circuit for a current control element according to the first aspect, wherein a switching transistor is provided between a gate electrode and a source electrode of the drive transistor, and the drive circuit is not connected. It is characterized in that the charge accumulated in the storage capacitor and the parasitic capacitance of the current control element is reset by turning on the switching transistor at the selection period or at the beginning of the selection period.

The invention according to claim 7 relates to the drive circuit of the current control element according to claim 1, further comprising a switching transistor between the gate electrode of the drive transistor and the other power supply line, The electric charge accumulated in the storage capacitor and the parasitic capacitance of the current control element is reset by turning on the switching transistor at the beginning of the non-selection period or the selection period of the circuit.

The invention according to claim 8 relates to the drive circuit for the current control element according to claim 6 or 7, wherein the select gate transistor, the drive transistor and the switching transistor are N-channel field effect transistors. It has a feature.

The present invention according to claim 9 relates to the drive circuit for the current control element according to claim 6 or 7, wherein the select gate transistor, the drive transistor and the switching transistor are P-channel field effect transistors. Is characterized by.

The invention according to claim 10 relates to an image display device, wherein a plurality of drive circuits for driving the current control element according to any one of claims 1 to 9 are arranged in a plane and arranged in rows and columns. It is characterized in that it can be driven in any direction.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using the embodiments. First Embodiment FIG. 1 is a circuit diagram showing the configuration of a drive circuit for a current control element according to the first embodiment of the present invention, and FIG. 2 illustrates the operation of the drive circuit for a current control element according to the present embodiment. Timing chart,
FIG. 3 shows the IDS- of the drive transistor in this embodiment.
FIG. 4 is a graph showing VGS characteristics, FIG. 4 is a graph showing IL-VL characteristics of the current control element in the present embodiment, FIG. 5 is a graph showing IDS-VGS characteristics when the characteristics of the drive transistor are variable, and FIG. FIG. 6 is a diagram showing VGS transient characteristics when the characteristics of the drive transistor vary.

The drive circuit of the current control element of this example is shown in FIG.
As shown in FIG. 3, the select gate transistor 4 and the storage capacitor 5 connected between the power line 1, the ground line 2 and the signal line 3 are connected.
, A drive transistor 6, a current control element 7, and a parasitic capacitance 8. The selection gate transistor 4 is composed of an N-channel field effect transistor, has a gate electrode connected to a selection line (not shown), a drain electrode connected to the signal line 3, and a source electrode connected to the gate electrode of the drive transistor 6. There is. The storage capacitor 5 is connected between the gate electrode and the source electrode of the drive transistor 6. The drive transistor 6 is composed of an N-channel field effect transistor, and has a gate electrode connected to the source electrode of the selection gate transistor 4 and one end of the storage capacitor 5, a drain electrode connected to the power supply line 1, and a source electrode connected to the current control element 7. Connected to the anode of. Current control element 7
Is connected between the source electrode of the drive transistor 6 and the ground line 2, and emits light with a brightness corresponding to the current IL of the drive transistor 6. The parasitic capacitance 8 is a parasitic capacitance at both ends of the current control element 7.

Next, the operation of the drive circuit of the current control element of this example will be described with reference to FIGS. As shown in FIG. 2, when the selection period of the drive circuit is started, the selection gate transistor 4 is switched from the cutoff state to the conduction state. At this time, the voltage VDATA input to the signal line 3
Is at 0 V, which is the same potential as the ground line 2. In this state, since the selection gate transistor 4 is in the conductive state, the electric charge of the storage capacitor 5 is started to be discharged through the signal line 3. At the same time, the electric charge of the parasitic capacitance 8 of the current control element 7 is discharged through the current control element 7. When a sufficient time has passed since the start of the selection period, both the gate voltage VG and the source voltage VS of the drive transistor 6 become 0V. Since the gate-source voltage VGS of the drive transistor 6 is zero, no current flows between the drain-source of the drive transistor 6.

Next, the input voltage of the signal line 3 changes from 0V to VA.
Can be switched to. Immediately after the signal line 3 is switched from 0V to VA, the gate-source voltage VGS of the drive transistor 6 is calculated from the capacitance value CS of the storage capacitor 5 and the capacitance value CL of the parasitic capacitance 8 of the current control element 7. It becomes like the following formula. VGS = VA × CL / (CS + CL) (2) On the other hand, the source voltage VS of the drive transistor 6 is expressed by the following equation. VS = VA × CS / (CS + CL) (3)

At this time, however, the gate-source voltage VGS of the driving transistor 6 is the threshold voltage VGS in the IDS-VGS characteristics of the driving transistor shown in FIG.
It must be greater than T. Further, the voltage VL between the terminals of the current control element 7, that is, the source voltage VS of the drive transistor 6 is the voltage − of the current control element 7 shown in FIG.
In the current characteristic, it is necessary that it is smaller than the forward rising voltage VOFF. That is, VGS> VT (4) VS <VOFF (5)

Since the gate-source voltage VGS of the drive transistor 6 is higher than the threshold voltage VT, a current flows between the drain-source of the drive transistor 6.
The drain-source current of the drive transistor 6 charges the parasitic capacitance 8 of the current control element 7 to increase the terminal voltage VL of the current control element 7, that is, the source voltage VS of the drive transistor 6. At the same time, since the gate voltage VG of the drive transistor 6 is a constant value VA, the gate-source voltage VG of the drive transistor 6 is
S approaches the threshold voltage VT while decreasing, and the source voltage VS of the drive transistor 6 approaches (VA-VT).

At this time, since the drive transistor 6 is a thin film transistor or the like formed on the glass substrate, the drive transistor 6 shown in FIG.
As shown in, the IDS-VGS indicating the relationship between the drain-source current IDS and the gate-source voltage VGS.
The characteristics are that for the same drain-source current IDS,
Depending on the characteristics of the individual transistors 6a, 6b and 6c, VGS greatly varies as shown by VTa, VTb and VTc. Therefore, as shown in FIG. 6, the gate-source voltage V of the drive transistors 6a, 6b and 6c is
After a sufficient time has elapsed, GS becomes the threshold values VTa, VTb, and VTc of the individual transistors from the value VA × CL / (CS + CL) immediately after the signal voltage VA is input,
The time until then is also different like Ta, Tb and Tc.

When a sufficient time has passed, no current flows between the drain and source of the drive transistor 6, and the gate-source voltage VGS of the drive transistor 6 becomes the threshold voltage VT. VGS = VT (6) On the other hand, the source voltage VS of the drive transistor 6 is expressed by the following equation. VS = VA-VT (7) However, at this time, the source voltage V of the drive transistor 6
S is the forward rising voltage VO of the current control element 7 in the IL-VL characteristic of the current control element 7 shown in FIG.
It is necessary to select the capacitance values CS and CL so as to be smaller than FF. VS <VOFF (8)

Next, the voltage VDATA input to the signal line 3
Is switched from VA to VB. Where VB is VA
Value (non-light emitting state) or a value larger than VA (light emitting state). The voltage difference (VB-VA) when switching from VA to VB is divided into the capacitance value CS of the gate-source holding capacitance 5 of the drive transistor 6 and the capacitance value CL of the parasitic capacitance 8 of the current control element 7. And then applied. Therefore, the gate-source voltage VGS of the drive transistor 6 and the source voltage VS of the drive transistor 6 at this time are respectively expressed by the following equations. VGS = VT + (1-CS / CL). (VB-VA) (9) VS = VA-VT + (VB-VA) CS / CL (10)

As can be seen from the above equation, (VGS-VT)
Is determined by (VB-VA), even if there is a variation in the threshold value of the drive transistor 6, this variation is corrected. Therefore, by setting VB and VA to appropriate values, the current control element 7 can be set. The flowing current value is controlled.

Next, the non-selection period is started by switching the selection gate transistor 4 from the conductive state to the cutoff state. In the non-selection period, the gate-source voltage VGS of the drive transistor 6 comes to be held by the holding capacitor 5. Source voltage V of drive transistor 6
S rises in response to the charging of the parasitic capacitance 8 of the current control element 7 via the driving transistor 6, and the gate voltage VG of the driving transistor 6 also passes through the holding capacitor 5 and the gate-source voltage. While maintaining VGS constant, it rises at the same time. The current control element 7 is the drive transistor 6
When the source voltage VS of the current control element 7 exceeds the forward-direction rising voltage VOFF of the current control element 7, light emission starts, and thereafter, light emission continues until the non-selection period ends. The voltage VL between the terminals of the current control element 7 is
When a voltage sufficient to flow the current IL determined by the source-to-source voltage VGS is reached, the rise of the gate voltage VG and the source voltage VS of the drive transistor 6 stops and becomes constant. After that, since the gate-source voltage VGS of the drive transistor 6 is held by the holding capacitor 5, the constant current IL continues to flow in the current control element 7.

As described above, in the drive circuit for the current control element of this example, the drive transistor 6 has the minimum element configuration including the two transistors of the selection gate transistor 4 and the drive transistor 6 and the storage capacitor 5. Can be corrected so that it is not affected by the change. According to the present embodiment, the number of elements forming the pixel circuit is 1/2 as compared with the drive circuit of the current control element of the conventional example.
Therefore, the aperture ratio of the pixel can be increased and the manufacturing process is facilitated. Further, generally, the capacitance value CL of the parasitic capacitance 8 of the current control element 7 is the capacitance value C of the storage capacitor 5.
Since it is larger than S, the drive circuit can be written with a smaller write voltage, which is also advantageous in terms of power consumption.

In the drive circuit of the first embodiment shown in FIG. 1, different operations can be performed by changing the control method. An example in this case will be described below.

Second Embodiment FIG. 7 is a timing chart for explaining the operation of the drive circuit for the current control element according to the second embodiment of the present invention. The configuration of the drive circuit of the current control element of this example is the same as that of the first embodiment shown in FIG. 1, but the operation is different because the control method is different.

The operation of the drive circuit for the current control element of this example will be described below with reference to FIG. When the selection period of the drive circuit is started, the selection gate transistor 4 is switched from the cutoff state to the conduction state. At this time, the voltage input to the signal line 3 is set to a voltage large enough to turn on the drive transistor 6. At the same time, the potential of the power supply line 1 is set to 0V. Since the drive transistor 6 is turned on, the electric charge of the parasitic capacitance 8 of the current control element 7 is discharged through the drive transistor 6. After the source voltage VS of the drive transistor 6 becomes zero, the voltage of the signal line 3 is set to the ground potential 0V. Select gate transistor 4
Are in a conductive state, the electric charge of the storage capacitor 5 is discharged, and the gate voltage VG of the drive transistor 6 becomes 0V.

After that, the voltage of the power supply line 1 is returned to the original power supply line voltage level. Since the gate-source voltage VGS of the driving transistor 6 is zero, the driving transistor 6
No current flows between the drain and source of the. Next, the input voltage of the signal line 3 is switched from 0V to VA. Subsequent operations are performed in the same manner as in the first embodiment.

As described above, in the current control element drive circuit of this example, as in the case of the first embodiment, the two transistors of the selection gate transistor 4 and the drive transistor 6 and the storage capacitor 5 are provided. The threshold of the drive transistor 6 can be corrected with a minimum element configuration so that it is not affected by the change, and the drive transistor is turned on at the beginning of the selection period to reduce the potential of the power supply line 1. Is set to 0V, the electric charge of the parasitic capacitance 8 of the current control element 7 can be discharged to the power supply line 1 through the driving transistor 6, and therefore the source voltage of the driving transistor 6 drops quickly, so that the selection period is shortened. It becomes possible to do.

Third Embodiment FIG. 8 is a circuit diagram showing the configuration of a drive circuit for a current control element according to a third embodiment of the present invention, and FIG. 9 is an operation of the drive circuit for a current control element according to the present embodiment. 3 is a timing chart for explaining the above. As shown in FIG. 8, the drive circuit of the current control element of this example includes a select gate transistor 4, a storage capacitor 5, and a drive transistor connected between a power line 1, a ground line 2 and a signal line 3. 6, current control element 7, and parasitic capacitance 8
And a switching transistor 9.

In the current control element drive circuit of this example, the power supply line 1, the ground line 2, the signal line 3, the selection gate transistor 4, the storage capacitor 5, the drive transistor 6, the current control device 7, and the parasitic capacitance 8 are configured. Is similar to the case of the first embodiment shown in FIG. 1, but is different from the case of the first embodiment in that a switching transistor 9 shown in FIG. 8 is additionally provided. Switching transistor 9
Is an N-channel field effect transistor, the gate electrode is connected to the select line, the drain electrode is connected to the source electrode of the drive transistor 6 and one end of the storage capacitor 5,
The source electrode is connected to the ground line 2.

The operation of the drive circuit for the current control element of this example will be described below with reference to FIGS. When the selection period of the drive circuit is started, the selection gate transistor 4 and the switching transistor 9 are controlled by the selection line.
Is switched from the cutoff state to the conduction state. At this time, the voltage input to the signal line 3 is 0 V which is the same as that of the ground line 2.
And Since the selection gate transistor 4 and the switching transistor 9 are brought into conduction, the electric charge of the storage capacitor 5 and the electric charge of the parasitic capacitance 8 of the current control element 7 are discharged, so that the gate voltage VG and the source of the drive transistor 6 The voltage VS becomes 0V. At this time, since the gate-source voltage VGS of the drive transistor 6 is 0 V, no current flows between the drain-source of the drive transistor 6. Next, the switching transistor 9 is turned off by the control from the select line, and the signal line 3
Input voltage is switched from 0V to VA. The subsequent operation is similar to that of the first embodiment.

As described above, according to the drive circuit for the current control element of this example, the threshold value of the drive transistor 6 is corrected in the same manner as in the first embodiment so that it is not affected by the change. can do. At this time, the switching transistor 9 is additionally required as compared with the case of the first embodiment, but the resetting of the storage capacitor 5 and the parasitic capacitance 8 of the current control element 7 by the switching transistor 9 is performed by the selection gate transistor 4. Since the writing can be performed independently of the storage capacitor 5, the storage capacitor 5 and the parasitic capacitance 8 can be reset more reliably by selecting the reset time.

Fourth Embodiment FIG. 10 is a circuit diagram showing the configuration of the drive circuit for the current control element according to the fourth embodiment of the present invention, and FIG. 11 is the operation of the drive circuit for the current control element according to the present embodiment. 3 is a timing chart for explaining the above. The drive circuit of the current control element of this example is shown in FIG.
As shown in FIG. 3, the select gate transistor 4 and the storage capacitor 5 connected between the power line 1, the ground line 2 and the signal line 3 are connected.
, A drive transistor 6, a current control element 7, a parasitic capacitance 8, and a switching transistor 10.

In the current control element drive circuit of this example, the power supply line 1, the ground line 2, the signal line 3, the selection gate transistor 4, the storage capacitor 5, the drive transistor 6, the current control device 7, and the parasitic capacitance 8 are configured. Is similar to the case of the first embodiment shown in FIG. 1, except that the first embodiment has a switching transistor 10 shown in FIG.
This is different from the case of the embodiment. The switching transistor 10 is composed of an N-channel field effect transistor,
The gate electrode is connected to the selection line, the drain electrode is connected to the gate electrode of the drive transistor 6 and one end of the storage capacitor 5, and the source electrode is connected to the ground line 2.

The operation of the drive circuit for the current control element of this example will be described below with reference to FIGS. The switching transistor 10 is made conductive by the control from the selection line for a certain period before the selection period of the drive circuit is started. Since the switching transistor 10 is in the conductive state, the gate voltage VG of the drive transistor 6 becomes zero, and the gate-source voltage VGS of the drive transistor 6 becomes a negative voltage, so that the drive transistor 6 is cut off. At this time, the electric charge accumulated in the parasitic capacitance 8 of the current control element 7 is discharged to the ground line 2 via the current control element 7. When a sufficiently long time has passed since the switching transistor 10 was turned on, all the charges accumulated in the parasitic capacitance 8 of the current control element 7 are discharged, and the source voltage VS of the drive transistor 6 becomes 0V. During this period, the selection gate transistor 4 is in the cutoff state by the control from the selection line.

Next, when the selection period of the drive circuit is started, the switching transistor 10 is switched from the conductive state to the cutoff state by the control from the selection line.
Next, the selection gate transistor 4 is switched from the cutoff state to the conduction state by the control from the selection line. At this time, VA is input as the input voltage VDATA of the signal line 3. The subsequent operation is similar to that of the first embodiment.

As described above, according to the drive circuit of the current control element of this example, the threshold value of the drive transistor 6 is corrected in the same manner as in the first embodiment so that it is not affected by the change. can do. At this time, although the switching transistor 10 is additionally required as compared with the case of the first embodiment, the resetting of the holding capacitance 5 and the parasitic capacitance 8 of the current control element 7 by the switching transistor 10
Since it can be performed independently of the writing of the storage capacitor 5 by the selection gate transistor 4, the storage capacitor 5 and the parasitic capacitance 8 can be reset more reliably by selecting the reset time.

In each of the above embodiments, the drive circuit for the current control element is entirely composed of N-channel field effect transistors, but the drive circuit may be composed of P-channel field effect transistors. An example in this case will be described below.

Fifth Embodiment FIG. 12 is a circuit diagram showing the configuration of the drive circuit for the current control element according to the fifth embodiment of the present invention. As shown in FIG. 12, the drive circuit of the current control element of this example has a selection gate transistor 4A, a storage capacitor 5A, and a drive transistor connected between a power supply line 1, a ground line 2, and a signal line 3. 6A
And a current control element 7A and a parasitic capacitance 8A. The selection gate transistor 4A is composed of a P-channel field effect transistor, has a gate electrode connected to a selection line (not shown), a source electrode connected to the signal line 3, and a drain electrode connected to the gate electrode of the drive transistor 6A. There is. The storage capacitor 5A is connected between the gate electrode and the source electrode of the drive transistor 6A. The drive transistor 6A is composed of a P-channel field effect transistor, the gate electrode is connected to the drain electrode of the selection gate transistor 4 and one end of the storage capacitor 5A, the source electrode is connected to the cathode of the current control element 7A, and the drain electrode is grounded. Connected to line 2. Current control element 7A
Is connected between the power supply line 1 and the source electrode of the drive transistor 6A, and emits light with a brightness corresponding to the current IL of the drive transistor 6A. The parasitic capacitance 8A is the current control element 7A.
It is the parasitic capacitance at both ends of.

The drive circuit of the current control element of this example is shown in FIG.
The selection gate transistor 4 and the driving transistor 6 which are the N-channel field effect transistors in the case of the first embodiment shown in FIG. This is a replacement, and therefore, compared with the case of the first embodiment shown in FIG. 1, since the relationship of the voltage is reversed, the direction of the current is reversed, but the operation is the same as that of the first embodiment. Since the timing chart shown in FIG. 2 can be applied in the same manner as in the case of the embodiment, detailed description will be omitted below.

As described above, in the drive circuit of the current control element of this example, the drive transistor 6A has the minimum element configuration including the two transistors of the selection gate transistor 4A and the drive transistor 6A and the storage capacitor 5A. Can be corrected so that it is not affected by the change. According to the present embodiment, as in the case of the first embodiment, the number of elements forming the pixel circuit can be gradually reduced and the aperture ratio of the pixel can be increased as compared with the conventional current control element drive circuit. At the same time, there is an advantage that the manufacturing process becomes easy and the power consumption is small.

Sixth Embodiment The configuration of the drive circuit for the current control element of this example is the same as that of the fifth embodiment shown in FIG. 12, but the operation is also different because the control method is different. Is different. The drive circuit of the current control element of this example includes the select gate transistor 4 and the drive transistor 6 which are N-channel field effect transistors in the case of the second embodiment, and the select gate transistor 4A and the drive transistor 6A which are P-channel field effect transistors. Replaced by
Therefore, as compared with the case of the second embodiment, the relationship of the voltage is reversed and the direction of the current is reversed, but the operation is the same as that of the second embodiment.
The timing chart shown in FIG. 7 can be applied as in the case of the embodiment, and therefore detailed description thereof will be omitted below.

As described above, in the drive circuit for the current control element of this example, as in the case of the fifth embodiment, the two transistors of the selection gate transistor 4A and the drive transistor 6A and the storage capacitor 5A are included. The threshold of the drive transistor 6A can be corrected with the minimum element configuration so that it is not affected by the change, and the source voltage of the drive transistor 6A drops quickly, so that the selection period is shortened. can do.

Seventh Embodiment FIG. 13 is a circuit diagram showing the configuration of the drive circuit for the current control element according to the seventh embodiment of the present invention. As shown in FIG. 13, the drive circuit of the current control element of this example has a selection gate transistor 4A, a storage capacitor 5A, and a drive transistor connected between a power supply line 1, a ground line 2, and a signal line 3. 6A
, A current control element 7A, a parasitic capacitance 8A, and a switching transistor 9A.

In the current control element drive circuit of this example, the power supply line 1, the ground line 2, the signal line 3, the selection gate transistor 4A, the storage capacitor 5A, the drive transistor 6A, the current control element 7A and the parasitic capacitance 8A are configured. Is the same as the case of the fifth embodiment shown in FIG. 12, but is different from the case of the fifth embodiment in that it has a switching transistor 9A shown in FIG. 13 in addition to these. The switching transistor 9A is composed of a P-channel field effect transistor, the gate electrode is connected to the selection line, the source electrode is connected to the power supply line 1, and the drain electrode is connected to the source electrode of the drive transistor 6A and one end of the storage capacitor 5A. ing.

The drive circuit for the current control element of this example is shown in FIG.
In the case of the third embodiment shown in FIG. 3, the selection gate transistor 4, the driving transistor 6 and the switching transistor 9 which are N-channel field effect transistors, the selection gate transistor 4A which is a P-channel field effect transistor, the driving transistor 6A and the switching transistor 9A, and therefore the voltage relationship is reversed and the current direction is reversed compared to the case of the third embodiment shown in FIG. 8, but the operation is Since the timing chart shown in FIG. 9 can be applied in the same manner as in the case of the third embodiment, detailed description will be omitted below.

As described above, according to the drive circuit for the current control element of this example, the threshold value of the drive transistor 6A is adjusted so as not to be affected by the change, as in the case of the fifth embodiment. can do. At this time, an extra switching transistor 9A is required as compared with the case of the fifth embodiment, but reset of the storage capacitor 5A and the parasitic capacitance 8 of the current control element 7 by the switching transistor 9A is performed by the selection gate transistor 4A. Since the writing can be performed independently of the storage capacitor 5A, the storage capacitor 5A and the parasitic capacitance 8A can be reset more reliably by selecting the reset time.

Eighth Embodiment FIG. 14 is a circuit diagram showing the configuration of the drive circuit for the current control element according to the eighth embodiment of the present invention. As shown in FIG. 13, the drive circuit of the current control element of this example has a selection gate transistor 4A, a storage capacitor 5A, and a drive transistor connected between a power supply line 1, a ground line 2, and a signal line 3. 6A
, A current control element 7A, a parasitic capacitance 8A, and a switching transistor 10A.

In the drive circuit of the current control element of this example, the power supply line 1, the ground line 2, the signal line 3, the selection gate transistor 4A, the storage capacitor 5A, the drive transistor 6A, the current control element 7A and the parasitic capacitance 8A. Is the same as the case of the fifth embodiment shown in FIG. 12, but is different from the case of the fifth embodiment in that it has a switching transistor 10A shown in FIG. 14 in addition to these. The switching transistor 10A is composed of a P-channel field effect transistor, the gate electrode is connected to the selection line, the source electrode is connected to the power supply line 1, and the drain electrode is connected to the gate electrode of the drive transistor 6A and one end of the storage capacitor 5A. ing.

The drive circuit for the current control element of this example is shown in FIG.
The selection gate transistor 4, the driving transistor 6 and the switching transistor 10 which are N-channel field effect transistors in the case of the fourth embodiment shown in FIG.
A selection gate transistor 4A which is a channel field effect transistor, a driving transistor 6A and a switching transistor 10A are replaced.
Therefore, as compared with the case of the fourth embodiment shown in FIG.
Since the relationship of voltage is reversed, the direction of current is reversed,
The operation is the same as in the case of the fourth embodiment.
Since the timing chart shown in FIG. 7 can be applied, detailed description will be omitted below.

As described above, according to the drive circuit for the current control element of this example, the threshold value of the drive transistor 6A is corrected in the same manner as in the fifth embodiment so that it is not affected by the change. can do. At this time, an extra switching transistor 10A is required as compared with the case of the fifth embodiment, but the resetting of the storage capacitor 5A and the parasitic capacitance 8 of the current control element 7 by the switching transistor 10A is performed by the selection gate transistor 4A. Storage capacity 5
Since the data can be written independently of A, the storage capacitor 5A and the parasitic capacitance 8A can be reset more reliably by selecting the reset time.

Although the embodiment of the present invention has been described in detail above with reference to the drawings, the specific structure is not limited to this embodiment, and there are design changes and the like within a range not departing from the gist of the present invention. However, it is included in this invention. For example, in the third, fourth, seventh and eighth embodiments,
The discharge of the storage capacitor 5 and the parasitic capacitance 8 by the switching transistor may be performed in the non-selection period or in the initial stage of the selection period. In the case of the non-selected period, it can be performed at any timing, not limited to the end thereof. At the beginning of the selection period, it is necessary to turn off the selection gate transistor. In each embodiment, when the drive transistor is the N-channel field effect transistor or the P-channel field effect transistor, the other selection gate transistors and the switching transistors are not limited to the N-channel field effect transistor or the P-channel field effect transistor, N-channel field effect transistor and P
It is possible to arbitrarily mix the channel field effect transistor. Furthermore, the drive circuit of the current control element of the present invention is an image display device in which a large number of current control elements are arranged in a plane, in a matrix in the row direction and the column direction,
It is also applicable to the drive circuit of the current control element, and in this case, it is obvious that the effects of the above-described embodiments can be obtained. Further, in the third and fourth embodiments, the source electrode of the switching transistor 9 is connected to the ground line 2, but it is connected to another power supply line having a voltage different from that of the ground line 2 to drive at the time of reset. The source voltage VS of the transistor 6 is 0V
By setting the voltage to other than, it is possible to widen the tolerance of the circuit design. Similar changes can be made to the seventh and eighth embodiments.

[0064]

As described above, according to the drive circuit of the current control element and the image display device of the present invention, even if the threshold characteristic of the drive transistor for driving the current control element varies, it is not affected. In addition, the number of elements forming the pixel circuit can be reduced as compared with the conventional similar current control element drive circuit, so that the aperture ratio of the pixel can be increased and the manufacturing process can be improved. Will be easier. Further, since the driving circuit can be written with a small writing voltage, it is advantageous in terms of power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a drive circuit for a current control element that is a first embodiment of the present invention.

FIG. 2 is a timing chart explaining the operation of the drive circuit of the current control element of the same embodiment.

FIG. 3 is an IDS- of a drive transistor in the same embodiment.
It is a figure which shows a VGS characteristic.

FIG. 4 is a diagram showing an IL-VL characteristic of the current control element in the example.

FIG. 5 is a diagram showing IDS-VGS characteristics when the characteristics of drive transistors vary.

FIG. 6 is a diagram showing transient characteristics of VGS when the characteristics of drive transistors vary.

FIG. 7 is a timing chart for explaining the operation of the drive circuit for the current control element according to the second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a drive circuit for a current control element that is a third embodiment of the present invention.

FIG. 9 is a timing chart for explaining the operation of the drive circuit for the current control element of the same example.

FIG. 10 is a circuit diagram showing a configuration of a drive circuit for a current control element that is a fourth embodiment of the present invention.

FIG. 11 is a timing chart for explaining the operation of the drive circuit for the current control element of the same example.

FIG. 12 is a circuit diagram showing a configuration of a drive circuit for a current control element that is a fifth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a configuration of a drive circuit for a current control element that is a seventh embodiment of the present invention.

FIG. 14 is a circuit diagram showing a configuration of a drive circuit for a current control element that is an eighth embodiment of the present invention.

FIG. 15 is a diagram showing a configuration of a drive circuit of a current control element of a first conventional example.

FIG. 16 is a diagram showing the IDS-VGS characteristics when the characteristics of the drive transistor vary.

FIG. 17 is a diagram showing a configuration of a drive circuit of a current control element of a second conventional example.

FIG. 18 is a timing chart explaining the operation of the drive circuit of the current control element of the second conventional example.

[Explanation of symbols]

1 power line (first power line) 2 Ground wire (second power line) 3 signal lines 4, 4A select gate transistor 5,5A holding capacity 6,6A drive transistor 7,7A current control element 8.8A parasitic capacitance 9,9A switching transistor 10,10A switching transistor

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H03K 17/687 H05B 33/14 A H05B 33/14 H03K 17/687 HF term (reference) 3K007 AB02 AB06 AB17 AB18 BA06 BB07 DB03 GA04 5C080 AA06 BB05 DD05 DD22 DD26 DD28 EE28 FF11 JJ03 JJ04 JJ05 5J055 AX04 AX49 BX16 CX29 DX13 DX14 DX53 DX55 EX01 EX07 EX21 EY00 EY10 EY21 EY29 FX12 FX17 FX24 FX35 GX06 GX06 GX00 GX00

Claims (10)

[Claims]
1. A drive transistor and a current control element connected in series between a first power supply line and a second power supply line, a connection point between the drive transistor and the current control element, and a gate electrode of the drive transistor. And a select gate transistor connected between a signal line and a gate electrode of the drive transistor, the select gate transistor being turned on during a select period of the drive circuit. A first signal voltage is input from a signal line, the signal charge written in the storage capacitor is discharged through the drive transistor, and then a second signal voltage is input from the signal line and stored in the storage capacitor. During the non-selection period of the drive circuit, the selection gate transistor is turned off, and a current is caused to flow through the drive transistor to the current control element. Drive circuit of the control element.
2. A reset signal voltage is input to the signal line at the beginning of the selection period of the drive circuit to reset the charges accumulated in the storage capacitor and the parasitic capacitance of the current control element. The drive circuit for the current control element according to claim 1, wherein the drive circuit is for a current control element.
3. The storage capacitor and the parasitic capacitance of the current control element are accumulated by turning on the drive transistor and setting the first power supply line to a reset signal voltage in the initial stage of the selection period of the drive circuit. 2. The drive circuit for a current control element according to claim 1, wherein the electric charge that has been stored is reset.
4. The drive circuit for a current control element according to claim 1, wherein the select gate transistor and the drive transistor are N-channel field effect transistors.
5. The drive circuit for a current control element according to claim 1, wherein the select gate transistor and the drive transistor are P-channel field effect transistors.
6. A storage transistor is provided between a gate electrode and a source electrode of the drive transistor, and the storage capacitor is turned on by turning on the switching transistor at the beginning of a non-selection period or a selection period of the drive circuit. 2. The drive circuit for the current control element according to claim 1, wherein the electric charge accumulated in the parasitic capacitance of the current control element is reset.
7. A switching transistor is provided between the gate electrode of the drive transistor and the other power supply line, and at the beginning of a non-selection period or a selection period of the drive circuit,
The drive circuit for the current control element according to claim 1, wherein the charge accumulated in the storage capacitor and the parasitic capacitance of the current control element is reset by turning on the switching transistor.
8. The drive circuit for a current control element according to claim 6, wherein the select gate transistor, the drive transistor, and the switching transistor are N-channel field effect transistors.
9. The drive circuit for the current control element according to claim 6, wherein the select gate transistor, the drive transistor, and the switching transistor are P-channel field effect transistors.
10. A plurality of drive circuits for the current control element according to claim 1 are arranged in a plane so as to be driven in a row direction and a column direction. Characteristic image display device.
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PCT/JP2003/002578 WO2003075256A1 (en) 2002-03-05 2003-03-05 Image display and its control method
US10/506,371 US7876294B2 (en) 2002-03-05 2003-03-05 Image display and its control method
US12/877,068 US20100328294A1 (en) 2002-03-05 2010-09-07 Image display apparatus and control method therefor
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