JP2003271095A - Driving circuit for current control element and image display device - Google Patents

Driving circuit for current control element and image display device

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JP2003271095A
JP2003271095A JP2002070730A JP2002070730A JP2003271095A JP 2003271095 A JP2003271095 A JP 2003271095A JP 2002070730 A JP2002070730 A JP 2002070730A JP 2002070730 A JP2002070730 A JP 2002070730A JP 2003271095 A JP2003271095 A JP 2003271095A
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transistor
current control
driving
control element
driving circuit
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JP3613253B2 (en
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Koichi Iguchi
Isao Sasaki
康一 井口
勇男 佐々木
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Nec Corp
日本電気株式会社
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Priority claimed from PCT/JP2003/002578 external-priority patent/WO2003075256A1/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0847Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the influence of variance in the threshold characteristic of a driving transistor. <P>SOLUTION: The disclosed driving circuit for the current control element has the driving transistor 6 and current control element 7 which are connected in series between a power line 1 and a ground line 2, a hold capacitor 5 which is connected between the connection point between the driving transistor 6 and current control element 7 and the gate electrode of the driving transistor 6, and a select gate transistor 4 which is connected between a signal line 3 and the gate electrode of the driving transistor 6. Then the driving circuit turns on the select gate transistor 4 in a selection period to input a 1st signal voltage from the signal line 3, inputs and holds a 2nd signal voltage from the signal line 3 in the hold capacitor 5 after discharging signal charges written to the hold capacitor 5 through the driving transistor 6, and turns off the select gate transistor 4 in a non-selection period to supply a current to the current control element 7 through the driving transistor 6. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】この発明は、有機EL(Elec Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, an organic EL (Elec
tro Luminescence) 素子等の電流制御素子を発光させるための電流制御素子の駆動回路及びこれを用いた画像表示装置に関する。 tro Luminescence) an image display apparatus using a driving circuit and this current control element for emitting a current control element such as the element. 【0002】 【従来の技術】有機ELディスプレイ等のように、電流制御によって駆動される発光素子(電流制御素子)の駆動回路を、平面状に多数配置して形成されている画像表示装置では、各電流制御素子に流れる電流の制御は、駆動回路において、駆動トランジスタのゲート−ソース間の保持容量に対して、信号線から選択ゲートトランジスタを介して、電流制御素子の表示輝度に応じた電流が流れるようにプログラムされた信号電荷を書き込んで、その信号電荷を表示期間中、保持することによって行われる。 [0002] As such the Related Art Organic EL display, a driving circuit of a light emitting element (current controlling element) driven by a current control, an image display device which is formed by arranging a large number in a planar shape, the control of the current flowing in each current control element, the driving circuit, a gate of the driving transistor - with respect to the holding capacitance between the source, through the selection gate transistor from the signal line, the current corresponding to the display luminance of the current control element writing a program signal charges to flow, during the display period the signal charges is carried out by holding. 【0003】図15は、第1の従来例の電流制御素子の駆動回路の構成を示したものであって、特開平8−23 [0003] Figure 15 is a shows a configuration of a driving circuit of the current control device of the first conventional example, JP-A-8-23
4683号公報に開示されているものである。 4683 No. those disclosed in Japanese. この従来例の電流制御素子の駆動回路は、図15に示すように、 Driving circuit of the current control device of the conventional example, as shown in FIG. 15,
電源線11と接地線12と信号線13との間に接続された、選択ゲートトランジスタ14と、保持容量15と、 The power supply line 11 is connected between the ground line 12 and the signal line 13, a select gate transistor 14, a storage capacitor 15,
駆動トランジスタ16と、電流制御素子17と、寄生容量18とからなっている。 A driving transistor 16, a current control element 17 consists of a parasitic capacitance 18.. 選択ゲートトランジスタ14 Select gate transistor 14
は、Nチャネル電界効果トランジスタからなり、ゲート電極を選択線(不図示)に接続され、ドレイン電極を信号線13に接続され、ソース電極を駆動トランジスタ1 Is an N-channel field effect transistor, the gate electrode of which is connected to the selection line (not shown), is connected to the drain electrode to the signal line 13, drives the source electrode transistor 1
6のゲート電極に接続されている。 6 is connected to the gate electrode of. 保持容量15は、駆動トランジスタ16のゲート電極と電源線11との間に接続されている。 Storage capacitor 15 is connected between the gate electrode and the power supply line 11 of the driving transistor 16. 駆動トランジスタ16は、Pチャネル電界効果トランジスタからなり、ゲート電極を選択ゲートトランジスタ14のソース電極と保持容量15の一端に接続され、ソース電極を電源線11に接続され、ドレイン電極を電流制御素子17のアノードに接続されている。 The driving transistor 16 is a P-channel field effect transistor, the gate electrode of which is connected to one end of the source electrode and the storage capacitor 15 of the select gate transistor 14 is connected to the source electrode to the power supply line 11, the drain electrode current control element 17 and it is connected to the anode. 電流制御素子17は、駆動トランジスタ16のドレイン電極と接地線12との間に接続され、駆動トランジスタ16の電流ILに応じた輝度で発光する。 Current control element 17 is connected between the drain electrode of the driving transistor 16 and the ground line 12, it emits light at a luminance corresponding to the current IL of the driving transistor 16. 寄生容量18は、電流制御素子17の両端の寄生容量である。 Parasitic capacitance 18 is the parasitic capacitance across the current control device 17. 【0004】図15に示された従来の電流制御素子の駆動回路では、選択期間中に、選択ゲートドライバ(不図示)からロウ(行)方向に出力された選択信号が、選択された行の各駆動回路の選択ゲートトランジスタ14のゲート電極に与えられて、該当する行の選択ゲートトランジスタ14が導通状態になることによって、駆動ドライバ(不図示)からカラム(列)方向に出力された信号電圧VDATAが、選択された信号線13を経て、駆動トランジスタ16のゲート−ソース間に印加される。 [0004] In the driving circuit of a conventional current control device shown in Figure 15, during the selection period, the selection gate driver selection signal outputted from the (not shown) row (row) in the direction, of the selected row given to the gate electrode of the select gate transistor 14 of each driver circuit, when the select gate transistors 14 for that row is turned on, driver (not shown) from the column (column) direction to output the signal voltage VDATA is, through the signal line 13 selected, the gate of the driving transistor 16 - is applied between the source. 駆動回路が選択期間から非選択期間に切り替えられると、 When the drive circuit is switched from the selection period to the non-selection period,
選択ゲートトランジスタ14が導通状態から非導通状態になる。 Selection gate transistors 14 is made of a conductive state to a non-conductive state. このとき、駆動トランジスタ16のゲート−ソース間電圧VGSは、保持容量15によって保持されているため、非選択期間(保持期間)中も、駆動トランジスタ16は、書き込まれた信号電圧に応じた電流IDS At this time, the gate of the driving transistor 16 - source voltage VGS, because they are held by the storage capacitor 15, also in the non-selection period (retention period), the driving transistor 16, a current IDS corresponding to the written signal voltage
を、電流制御素子17に供給し続ける。 The continues to supply the current control element 17. 【0005】図16は、駆動トランジスタの特性がばらついているときのIDS−VGS特性を示したものである。 [0005] Figure 16 is a graph showing the IDS-VGS characteristics when the characteristics of the driving transistor is varied. 駆動トランジスタのIDS−VGS特性は、個々のトランジスタによってばらつきがあり、特にしきい値のばらつきが大きい。 IDS-VGS characteristic of the driving transistor, there is a variation by the individual transistors, in particular a large variation in the threshold. そのため、駆動トランジスタのゲート−ソース間電圧VGSとして、同一の信号電圧VDA Therefore, the gate of the driving transistor - as source voltage VGS, the same signal voltage VDA
TAが与えられた場合でも、駆動トランジスタの出力電流IDSは、個々のトランジスタによって、IL1,I Even if the TA is given, the output current IDS of the driving transistor, the individual transistors, IL1, I
L2又はIL3のようにばらつく。 It varies as L2 or IL3. ドレイン−ソース間電流IDSは、そのまま電流制御素子17に流れるため、各駆動回路に同じ信号電圧VDATAを入力しても、電流制御素子17に流れる電流にばらつきが生じることになる。 Drain - source current IDS is to flow directly to the current control element 17, entering the same signal voltage VDATA to the driving circuit, so that the variations in the current flowing through the current control device 17. さらに、非選択期間中も、駆動トランジスタ16のゲート−ソース間電圧VGSは、保持容量15 Moreover, even during the non-selection period, the gate of the driving transistor 16 - source voltage VGS is holding capacitor 15
によって保持されるため、信号電圧VDATAが同じ場合でも、駆動トランジスタ16のばらつきに基づいて、 To be held by, even if the signal voltage VDATA is the same, based on the variation of the drive transistor 16,
駆動回路によって異なる電流が電流制御素子17に流れ続ける。 Different current by the drive circuit continues to flow in the current control element 17. このため、同一信号電圧を書き込んでも、各電流制御素子の発光輝度にばらつきが発生するという問題があった。 Therefore, a write of the same signal voltage, the variation is disadvantageously generated in the light-emitting luminance of each current control element. 【0006】このような、駆動トランジスタのしきい値ばらつきによって生じる駆動電流のばらつきを防止するための方法として、下記の文献に記載されたものが提案されている。 As a method for preventing a variation in driving current caused by variation in threshold values ​​of such, the driving transistor has been proposed those described in the literature below. SID' 99,pp.11-14 ; A Polysilicon Active Matrix Org SID '99, pp.11-14; A Polysilicon Active Matrix Org
anic Light EmittingDiode Display with Integrated D anic Light EmittingDiode Display with Integrated D
rivers, R.dawson et al 【0007】図17は、第2の従来例の電流制御素子の駆動回路の構成を示したものである。 rivers, R.dawson et al [0007] Figure 17 is a diagram showing a configuration of a drive circuit of the current control element of the second conventional example. この従来例の電流制御素子の駆動回路は、図17に示すように、電源線1 Driving circuit of the current control device of the conventional example, as shown in FIG. 17, the power supply line 1
1と接地線12と信号線13との間に接続された、選択ゲートトランジスタ14Aと、保持容量15と、駆動トランジスタ16と、電流制御素子17と、寄生容量18 1 and connected between the ground line 12 and the signal line 13, a select gate transistor 14A, a storage capacitor 15, a driving transistor 16, a current control element 17, the parasitic capacitance 18
と、デカップリング容量19と、スイッチングトランジスタ20,21とからなっている。 And, the decoupling capacitance 19, is made up of the switching transistors 20 and 21. 選択ゲートトランジスタ14Aは、Pチャネル電界効果トランジスタからなり、ゲート電極を選択線(不図示)に接続され、ソース電極を信号線13に接続され、ドレイン電極をデカップリング容量19の一端に接続されている。 Selection gate transistors 14A is a P-channel field effect transistor, the gate electrode of which is connected to the selection line (not shown), is connected to the source electrode to the signal line 13 is connected to the drain electrode at one end of the decoupling capacitance 19 there. 保持容量15 The storage capacitor 15
は、駆動トランジスタ16のゲート電極と電源線11との間に接続されている。 It is connected between the gate electrode and the power supply line 11 of the driving transistor 16. 駆動トランジスタ16は、Pチャネル電界効果トランジスタからなり、ゲート電極をデカップリング容量19の他端と保持容量15の一端に接続され、ソース電極を電源線11に接続され、ドレイン電極をスイッチングトランジスタ21のソース電極に接続されている。 The driving transistor 16 is a P-channel field effect transistor, the gate electrode of which is connected to one end of the other end the storage capacitor 15 of the decoupling capacitor 19, is connected to the source electrode to the power supply line 11, the drain electrode of the switching transistor 21 It is connected to the source electrode. 【0008】電流制御素子17は、スイッチングトランジスタ21のドレイン電極と接地線12との間に接続されていて、駆動トランジスタ16の電流に応じた輝度で発光する。 [0008] The current control element 17, which is connected between the drain electrode of the switching transistor 21 and the ground line 12, emits light at a luminance corresponding to the current of the driving transistor 16. 寄生容量18は、電流制御素子17の両端の寄生容量である。 Parasitic capacitance 18 is the parasitic capacitance across the current control device 17. デカップリング容量19は、選択ゲートトランジスタ14Aのドレイン電極と駆動トランジスタ16のゲート電極間に接続されていて、これらの間を直流的に分離する。 Decoupling capacitor 19, selection gate transistors 14A be connected between the gate electrode of the drain electrode and the driving transistor 16, to separate between the direct current manner. スイッチトランジスタ20は、Pチャネル電界効果トランジスタからなり、ゲート電極をリセット線(不図示)に接続され、ソース電極を駆動トランジスタ16のゲート電極に接続され、ドレイン電極を駆動トランジスタ16のドレイン電極に接続されている。 Switch transistor 20 is a P-channel field effect transistor, the gate electrode of which is connected to the reset line (not shown), is connected to the source electrode to the gate electrode of the driving transistor 16, the drain electrode connected to the drain electrode of the driving transistor 16 It is. スイッチングトランジスタ21は、Pチャネル電界効果トランジスタからなり、ゲート電極をリセット線に接続され、ソース電極を駆動トランジスタ16のドレイン電極に接続され、ドレイン電極を電流制御素子17の一端に接続されている。 The switching transistor 21 is a P-channel field effect transistor, the gate electrode of which is connected to the reset line, a source connected to electrode to the drain electrode of the driving transistor 16 is connected to the drain electrode to one end of the current control element 17. 【0009】図18は、第2の従来の電流制御素子の駆動回路の動作を説明するタイミングチャートである。 [0009] Figure 18 is a timing chart for explaining the operation of the driving circuit of the second conventional current control element. 以下、図17,図18を用いて、第2の従来例の電流制御素子の駆動回路の動作を説明する。 Hereinafter, FIG. 17, with reference to FIG. 18, the operation of the driving circuit of the current control element of the second conventional example. この従来例の電流制御素子の駆動回路では、選択期間が始まる前に、電流制御素子17の寄生容量18を放電し、駆動トランジスタ16のドレイン電圧VDを接地線電位にしておく必要がある。 In the driving circuit of the current control element in the conventional example, before the selection period starts, and discharge the parasitic capacitance 18 of the current control element 17, it is necessary to the ground line potential drain voltage VD of the driving transistor 16. また、信号線13の電圧を電源線11の電圧VD Further, the voltage of the power supply line 11 a voltage of the signal line 13 VD
Dにしておく。 Keep the D. 選択期間が開始されたとき、ロウ方向の選択信号を選択線に与えることによって、選択ゲートトランジスタ14Aをオンにし、リセットドライバ(不図示)からリセット信号をリセット線に与えることによって、スイッチングトランジスタ20をオンにし、スイッチングトランジスタ21をオフにすると、駆動トランジスタ16のゲート電極とドレイン電極とを電気的に接続した状態で、保持容量15に蓄積された電荷の放電が開始される。 When the selection period is started by giving the row direction of the selection signal to the selection line, to turn on the select gate transistor 14A, by providing a reset signal to the reset line from the reset driver (not shown), the switching transistor 20 Turn on and turn off the switching transistor 21, while electrically connecting the gate electrode and the drain electrode of the driving transistor 16, the discharge of the accumulated in the storage capacitor 15 charges is started. この状態で、充分、時間が経過すると、駆動トランジスタ16のゲート電圧VGがしきい値VTまで降下する。 In this state, sufficient, over time, the gate voltage VG of the driving transistor 16 drops to the threshold value VT. その後、スイッチングトランジスタ20をオフにして、駆動トランジスタ16のゲート電極をフローティングにする。 Then, turn off the switching transistor 20, the gate electrode of the driving transistor 16 to the floating. 【0010】次に、信号線13からの入力電圧が、電源線11の電圧VDDから書き込み電圧VDATAに切り替えられると、駆動トランジスタ16のゲート−ドレイン間電圧VGSは、デカップリング容量19の容量値C [0010] Then, the input voltage from the signal line 13, when switched to the write voltage VDATA from the voltage VDD of the power supply line 11, the gate of the driving transistor 16 - drain voltage VGS, the capacitance value C of the decoupling capacitor 19
Dと、保持容量15の容量値CSとの容量分割によって、下式で与えられるようになる。 And D, the capacitance division between the capacitance value CS of the storage capacitor 15, so that given by the following equation. VGS=VG−VDD =VT+CD・(VDATA−VDD)/(CS+CD) …(1) トランジスタのドレイン−ソース間電流値は、一般に、 VGS = VG-VDD = VT + CD · (VDATA-VDD) / (CS + CD) ... (1) the drain of the transistor - between the source current value is, in general,
(VGS−VT)の関数で表されるが、上式からわかるように、(VGS−VT)がVDATAで決まるので、 Is represented by a function of (VGS-VT), as can be seen from the above equation, since determined by (VGS-VT) is VDATA,
駆動トランジスタ16のしきい値にばらつきがあっても、それが補正される。 Even if there are variations in the threshold of the driving transistor 16, it is corrected. 【0011】しかしながら、この従来例では、1画素に対して4個のトランジスタが必要になるだけでなく、保持容量のほかに、デカップリング容量が必要になる。 [0011] However, in this conventional example, not only requires four transistors per pixel, in addition to the storage capacitor, a decoupling capacitor is required. 従って、画素の開口率が低下して、製造プロセス的にも困難になるという問題がある。 Therefore, decreases the aperture ratio of the pixel, there is a problem that it becomes difficult to manufacture process manner. また、デカッップリング容量CDの値が小さいと、書き込み電圧VDATAをより大きくしなければならないので、CD>CSにすることが望ましいが、そのためには、デカッップリング容量C If the value of Deka' Tsu pulling capacity CD is small, since they must be larger write voltage VDATA, it is desirable to CD> CS, For that purpose, Deka' Tsu pulling capacity C
Dを形成するためのチップ面積が大きくなるという問題もある。 There is also a problem that the chip area for forming a D increases. さらに、選択期間前における電流制御素子の寄生容量の放電に時間がかかり、寄生容量放電の操作が複雑になるという欠点も持っている。 Furthermore, it takes time to discharge the parasitic capacitance of the current control element in the pre-selection, operation of the parasitic capacitance discharge also has disadvantage that complicated. 【0012】 【発明が解決しようとする課題】この発明は上述の事情に鑑みてなされたものであって、最小限の素子構成で、 [0012] [Problems that the Invention is to Solve The present invention was made in view of the above circumstances, with minimal device structure,
駆動トランジスタのしきい値ばらつきを補正することが可能な、電流制御素子の駆動回路及び画像表示装置を提供することを目的としている。 Capable of correcting the threshold voltage variation of the driving transistor, and its object is to provide a driving circuit and an image display apparatus of the current control element. 【0013】 【課題を解決するための手段】上記課題を解決するため、請求項1記載の発明は電流制御素子の駆動回路に係り、第1の電源線と第2の電源線との間に直列に接続された駆動トランジスタと電流制御素子と、上記駆動トランジスタと電流制御素子の接続点と上記駆動トランジスタのゲート電極との間に接続された保持容量と、信号線と上記駆動トランジスタのゲート電極との間に接続された選択ゲートトランジスタとを備え、上記駆動回路の選択期間に、選択ゲートトランジスタをオンにして上記信号線から第1の信号電圧を入力し、上記保持容量に書き込まれた信号電荷を上記駆動トランジスタを経て放電したのち、上記信号線から第2の信号電圧を入力して上記保持容量に保持し、上記駆動回路の非選択期間に、上記選択ゲ [0013] In order to solve the above object, according to an aspect of, the invention of claim 1, wherein relates to a driving circuit of the current control element, between a first power supply line and the second power supply line a drive transistor and a current control element connected in series, and connected storage capacitor between the gate electrode of the connection point between the driving transistor of the driving transistor and the current control element, the gate electrode of the signal line and the driving transistor and a connected selection gate transistors between, the selection period of the drive circuit receives a first signal voltage from the signal line to turn on the select gate transistor, written in the storage capacitor signal After a charge has been discharged through the driving transistor, and enter the second signal voltage from the signal line held in the holding capacitor, the non-selection period of the drive circuit, the select gates ートトランジスタをオフにして上記駆動トランジスタを経て上記電流制御素子に電流を流すことを特徴としている。 Turn off the over phototransistor through the driving transistor is characterized by supplying a current to said current control element. 【0014】また、請求項2記載の発明は、請求項1記載の電流制御素子の駆動回路に係り、上記駆動回路の選択期間の初期に、上記信号線にリセット信号電圧を入力することによって、上記保持容量及び上記電流制御素子の寄生容量に蓄積されている電荷をリセットすることを特徴としている。 [0014] According to a second aspect of the invention relates to a driving circuit of the current control device according to claim 1, early in the selection period of the driving circuit, by inputting a reset signal voltage to the signal line, It is characterized by resetting the charge stored in the parasitic capacitance of the storage capacitor and the current control element. 【0015】また、請求項3記載の発明は、請求項1記載の電流制御素子の駆動回路に係り、上記駆動回路の選択期間の初期に、上記駆動トランジスタをオンにし、上記第1の電源線をリセット信号電圧とすることによって、上記保持容量及び上記電流制御素子の寄生容量に蓄積されている電荷をリセットすることを特徴としている。 [0015] According to a third aspect of the invention relates to a driving circuit of the current control device according to claim 1, early in the selection period of the driving circuit, to turn on the drive transistor, the first power supply line by the reset signal voltage is characterized by resetting the charge stored in the parasitic capacitance of the storage capacitor and the current control element. 【0016】また、請求項4記載の発明は、請求項1乃至3のいずれか一に記載の電流制御素子の駆動回路に係り、上記選択ゲートトランジスタと駆動トランジスタとが、Nチャネル電界効果トランジスタからなることを特徴としている。 Further, an invention according to claim 4, wherein, relates to a driving circuit of the current control device according to any one of claims 1 to 3, the selection gate transistor and the driving transistor, the N-channel field-effect transistor It is characterized in that it comprises. 【0017】また、請求項5記載の発明は、請求項1乃至3のいずれか一に記載の電流制御素子の駆動回路に係り、上記選択ゲートトランジスタと駆動トランジスタとが、Pチャネル電界効果トランジスタからなることを特徴としている。 Further, an invention according to claim 5, relates to a driving circuit of the current control device according to any one of claims 1 to 3, the selection gate transistor and the driving transistor, a P-channel field effect transistor It is characterized in that it comprises. 【0018】また、請求項6記載の発明は、請求項1記載の電流制御素子の駆動回路に係り、上記駆動トランジスタのゲート電極とソース電極との間にスイッチングトランジスタを備え、上記駆動回路の非選択期間又は選択期間の初期に、上記スイッチングトランジスタをオンにすることによって、上記保持容量及び上記電流制御素子の寄生容量に蓄積されている電荷をリセットすることを特徴としている。 Further, an invention according to claim 6, it relates to a driving circuit of the current control device according to claim 1, further comprising a switching transistor between the gate electrode and the source electrode of the driving transistor, non of the driving circuit the beginning of the selection period or selection period, by turning on the switching transistor, is characterized by resetting the charge stored in the parasitic capacitance of the storage capacitor and the current control element. 【0019】また、請求項7記載の発明は、請求項1記載の電流制御素子の駆動回路に係り、上記駆動トランジスタのゲート電極と上記他方の電源線との間にスイッチングトランジスタを備え、上記駆動回路の非選択期間又は選択期間の初期に、上記スイッチングトランジスタをオンにすることによって、上記保持容量及び上記電流制御素子の寄生容量に蓄積されている電荷をリセットすることを特徴としている。 Further, an invention according to claim 7, it relates to a driving circuit of the current control device according to claim 1, further comprising a switching transistor between the gate electrode and the other power supply line of the driving transistor, the driving the beginning of the non-selection period or selection period of the circuit, by turning on the switching transistor, is characterized by resetting the charge stored in the parasitic capacitance of the storage capacitor and the current control element. 【0020】また、請求項8記載の発明は、請求項6又は7記載の電流制御素子の駆動回路に係り、選択ゲートトランジスタと駆動トランジスタとスイッチングトランジスタとが、Nチャネル電界効果トランジスタからなることを特徴としている。 Further, an invention according to claim 8, relates to a driving circuit of the current control device according to claim 6 or 7, wherein that the selection gate transistor and the driving transistor and the switching transistor is composed of N-channel field-effect transistor It is characterized. 【0021】また、請求項9記載の発明は、請求項6又は7記載の電流制御素子の駆動回路に係り、上記選択ゲートトランジスタと駆動トランジスタとスイッチングトランジスタとが、Pチャネル電界効果トランジスタからなることを特徴としている。 Further, an invention according to claim 9, relates to a driving circuit of the current control device according to claim 6 or 7, wherein the selection gate transistor and the driving transistor and the switching transistor, to consist of P-channel field effect transistor It is characterized in. 【0022】また、請求項10記載の発明は、画像表示装置に係り、請求項1乃至9のいずれか一記載の電流制御素子の駆動回路を複数個平面状に配列して、行方向と列方向とに駆動可能なように構成してなることを特徴としている。 Further, an invention according claim 10, relates to an image display device, by arranging the drive circuit of the current control element according to any one of claims 1 to 9 into a plurality planar rows and columns It is characterized by being configured to be driven in the direction. 【0023】 【発明の実施の形態】以下、図面を参照して、この発明の実施の形態について説明する。 DETAILED DESCRIPTION OF THE INVENTION Hereinafter, with reference to the drawings will be described embodiments of the present invention. 説明は、実施例を用いて具体的に行う。 Description will be specifically carried out using examples. ◇第1実施例図1は、本発明の第1実施例である電流制御素子の駆動回路の構成を示す回路図、図2は、本実施例の電流制御素子の駆動回路の動作を説明するタイミングチャート、 First Embodiment FIG. 1 ◇ is a circuit diagram showing a configuration of a drive circuit of the first an embodiment current control device of the present invention, FIG. 2 illustrates the operation of the driving circuit of the current control element of this example Timing chart,
図3は、本実施例における駆動トランジスタのIDS− 3, the driving transistor in this embodiment IDS-
VGS特性を示す図、図4は、本実施例における電流制御素子のIL−VL特性を示す図、図5は、駆動トランジスタの特性がばらついているときのIDS−VGS特性を示す図、図6は、駆動トランジスタの特性がばらついているときのVGSの過渡特性を示す図である。 Illustrates the VGS characteristic, FIG. 4 is a diagram showing the IL-VL characteristic of the current control element of the present example, FIG. 5 is a diagram showing a IDS-VGS characteristics when the characteristics of the driving transistor is varied, FIG. 6 is a diagram showing the transient characteristics of the VGS when the characteristics of the driving transistor is varied. 【0024】この例の電流制御素子の駆動回路は、図1 The driving circuit of the current control element in this example, FIG. 1
に示すように、電源線1と接地線2と信号線3との間に接続された、選択ゲートトランジスタ4と、保持容量5 As shown in, connected between the power supply line 1 and ground line 2 and the signal line 3, and the select gate transistor 4, storage capacitor 5
と、駆動トランジスタ6と、電流制御素子7と、寄生容量8とから概略構成されている。 When, a driving transistor 6, a current control element 7, it is schematically composed of the parasitic capacitance 8. 選択ゲートトランジスタ4は、Nチャネル電界効果トランジスタからなり、ゲート電極を選択線(不図示)に接続され、ドレイン電極を信号線3に接続され、ソース電極を駆動トランジスタ6のゲート電極に接続されている。 Select gate transistor 4 is an N-channel field effect transistor, the gate electrode of which is connected to the selection line (not shown), it is connected to the drain electrode to the signal line 3 is connected to the source electrode to the gate electrode of the driving transistor 6 there. 保持容量5は、駆動トランジスタ6のゲート電極とソース電極の間に接続されてる。 Storage capacitor 5 is connected between the gate electrode and the source electrode of the driving transistor 6. 駆動トランジスタ6は、Nチャネル電界効果トランジスタからなり、ゲート電極を選択ゲートトランジスタ4のソース電極と保持容量5の一端に接続され、ドレイン電極を電源線1に接続され、ソース電極を電流制御素子7のアノードに接続されている。 The driving transistor 6 is an N-channel field effect transistor, the gate electrode of which is connected to one end of the source electrode and the storage capacitor 5 of the select gate transistor 4 is connected to the drain electrode to the power source line 1, the current control element 7 to the source electrode and it is connected to the anode. 電流制御素子7 Current steering element 7
は、駆動トランジスタ6のソース電極と接地線2との間に接続され、駆動トランジスタ6の電流ILに応じた輝度で発光する。 Is connected between the source electrode of the driving transistor 6 and the ground line 2, it emits light at a luminance corresponding to the current IL of the driving transistor 6. 寄生容量8は、電流制御素子7の両端の寄生容量である。 Parasitic capacitance 8 is a parasitic capacitance across the current control device 7. 【0025】次に、図1〜図6を参照して、この例の電流制御素子の駆動回路の動作を説明する。 Next, with reference to FIGS. 1 to 6, the operation of the driving circuit of the current control element of this example. 図2に示すように、駆動回路の選択期間が開始されると、選択ゲートトランジスタ4が遮断状態から導通状態に切り替えられる。 As shown in FIG. 2, when the selection period of the driving circuit is started, the selection gate transistor 4 is switched to a conductive state from the cutoff state. このとき、信号線3に入力される電圧VDATA At this time, voltage is input to the signal line 3 VDATA
は、接地線2と同電位の0Vとする。 It is set to 0V and the ground line 2 the same potential. この状態では、選択ゲートトランジスタ4が導通状態であるため、保持容量5の電荷は、信号線3を介して放電が開始される。 In this state, since the selection gate transistor 4 is conductive, the charge storage capacitor 5, discharge is started via the signal line 3. 同時に、電流制御素子7の寄生容量8の電荷が、電流制御素子7を経て放電される。 At the same time, the charge of the parasitic capacitance 8 of the current control element 7 is discharged through the current control device 7. 選択期間が開始されてから充分な時間が経過すると、駆動トランジスタ6のゲート電圧VGとソース電圧VSがともに0Vとなる。 When sufficient time has elapsed since the selection period is started, the gate voltage VG and source voltage VS of the driving transistor 6 all are 0V. 駆動トランジスタ6のゲート−ソース間電圧VGSはゼロであるため、駆動トランジスタ6のドレイン−ソース間には電流が流れない。 The gate of the driving transistor 6 - source voltage VGS is because it is zero, the drain of the driving transistor 6 - no current flows between the source. 【0026】次に、信号線3の入力電圧が0VからVA [0026] Next, the input voltage of the signal line 3 from 0V VA
に切り替えられる。 It is switched on. 信号線3が0VからVAに切り替えられた直後には、駆動トランジスタ6のゲート−ソース間電圧VGSは、保持容量5の容量値CSと電流制御素子7の寄生容量8の容量値CLとから、次式のようになる。 The source voltage VGS is the capacitance value CL of the parasitic capacitance 8 of the capacitance CS and the current control element 7 of the storage capacitor 5, - the signal line 3 is the immediately switched to VA from 0V, the gate of the driving transistor 6 It expressed by the following equation. VGS=VA×CL/(CS+CL) …(2) 一方、駆動トランジスタ6のソース電圧VSは、次式のようになる。 VGS = VA × CL / (CS + CL) ... (2) On the other hand, the source voltage VS of the driving transistor 6 is expressed by the following equation. VS=VA×CS/(CS+CL) …(3) 【0027】ただし、このとき、駆動トランジスタ6のゲート−ソース間電圧VGSは、図3に示す駆動トランジスタのIDS−VGS特性において、しきい値電圧V VS = VA × CS / (CS + CL) ... (3) [0027] However, this time, the gate of the driving transistor 6 - source voltage VGS is the IDS-VGS characteristic of the driving transistor shown in FIG. 3, the threshold voltage V
Tよりも大きいことが必要である。 It needs to be larger than T. また、電流制御素子7の端子間電圧VL、すなわち、駆動トランジスタ6のソース電圧VSは、図4に示す電流制御素子7の電圧− Further, the inter-terminal voltage VL of the current control element 7, i.e., the source voltage VS of the driving transistor 6, the voltage of the current control device 7 shown in FIG. 4 -
電流特性において、順方向の立ち上がり電圧VOFFよりも小さいことが必要である。 In current characteristic, it is necessary that less than the forward rise voltage VOFF. すなわち、 VGS>VT …(4) VS<VOFF …(5) 【0028】駆動トランジスタ6のゲート−ソース間電圧VGSは、しきい値電圧VTよりも大きいため、駆動トランジスタ6のドレイン−ソース間に電流が流れる。 That, VGS> VT ... (4) VS <VOFF ... (5) [0028] The gate of the driving transistor 6 - source voltage VGS is larger than the threshold voltage VT, the drain of the driving transistor 6 - between the source current flows.
この駆動トランジスタ6のドレイン−ソース間電流によって、電流制御素子7の寄生容量8に電荷が充電されて、電流制御素子7の端子間電圧VL、すなわち駆動トランジスタ6のソース電圧VSが上昇する。 Drain of the driving transistor 6 - by source current, and charge the parasitic capacitance 8 of the current control element 7 is charged, the inter-terminal voltage VL of the current control element 7, that is, the source voltage VS of the driving transistor 6 is increased. 同時に、駆動トランジスタ6のゲート電圧VGが一定値VAであるため、駆動トランジスタ6のゲート−ソース間電圧VG At the same time, since the gate voltage VG of the driving transistor 6 is constant value VA, the gate of the driving transistor 6 - source voltage VG
Sは、減少しながらしきい値電圧VTに近づき、駆動トランジスタ6のソース電圧VSは、(VA−VT)に近づく。 S approaches the threshold voltage VT while reducing, the source voltage VS of the driving transistor 6 is closer to (VA-VT). 【0029】この際、駆動トランジスタ6は、ガラス基板上に形成された薄膜トランジスタ等であるため、図5 [0029] In this case, the driving transistor 6 is a thin film transistor or the like formed on a glass substrate, FIG. 5
に示すように、ドレイン−ソース間電流IDSと、ゲート−ソース間電圧VGSとの関係を示すIDS−VGS As shown in, the drain - a source current IDS, gate - IDS-VGS showing the relationship between the source voltage VGS
特性は、同じドレイン−ソース間電流IDSに対して、 Characteristics, same drain - relative source current IDS,
個々のトランジスタ6a,6b及び6cの特性に応じて、VGSがVTa,VTb及びVTcで示されるように大きくばらつく。 Individual transistors 6a, depending on the characteristics of 6b and 6c, VGS is VTa, greatly varies as shown by VTb and VTc. そこで図6に示すように、駆動トランジスタ6a,6b及び6cのゲート−ソース間電圧V Therefore, as shown in FIG. 6, the driving transistor 6a, and 6b and 6c gate - source voltage V
GSは、充分な時間が経過すると、信号電圧VAの入力直後の値VA×CL/(CS+CL)から、個々のトランジスタのしきい値VTa,VTb及びVTcとなり、 GS, when sufficient time has elapsed, the signal voltage VA of the immediately input value VA × CL / (CS + CL), of the individual transistors threshold VTa, VTb and VTc next,
それまでの時間も、Ta,Tb及びTcのように異なっている。 The time until then, Ta, are different in as Tb and Tc. 【0030】そして、充分な時間が経過したとき、駆動トランジスタ6のドレイン−ソース間には電流が流れないようになり、駆動トランジスタ6のゲート−ソース間電圧VGSはしきい値電圧VTとなる。 [0030] Then, when sufficient time has elapsed, the drain of the driving transistor 6 - now no current flows between the source and the gate of the driving transistor 6 - source voltage VGS becomes a threshold voltage VT. VGS=VT …(6) 一方、駆動トランジスタ6のソース電圧VSは、次式のようになる。 VGS = VT ... (6) On the other hand, the source voltage VS of the driving transistor 6 is expressed by the following equation. VS=VA−VT …(7) ただし、このとき、駆動トランジスタ6のソース電圧V VS = VA-VT ... (7) However, this time, the source voltage V of the drive transistor 6
Sは、図4に示された電流制御素子7のIL−VL特性において、電流制御素子7の順方向立ち上がり電圧VO S, in the IL-VL characteristic of the current control element 7 shown in FIG. 4, the forward rise voltage VO of the current control element 7
FFよりも小さくなるように、容量値CS,CLを選定することが必要である。 To be smaller than FF, it is necessary to select a capacitance value CS, CL. VS<VOFF …(8) 【0031】次に、信号線3に入力する電圧VDATA VS <VOFF ... (8) [0031] Next, a voltage is input to the signal line 3 VDATA
がVAからVBに切り替えられる。 There is switched from the VA to VB. ここで、VBはVA Here, VB is VA
と同じ値(非発光状態)、又はVAより大きい値(発光状態)である。 Same value as (non-emitting state), or a VA greater than (light emission state). VAからVBに切り替えたときの電圧差(VB−VA)は、駆動トランジスタ6のゲート−ソース間保持容量5の容量値CSと、電流制御素子7の寄生容量8の容量値CLとに容量分割して印加される。 Voltage difference when switched to VB from VA (VB-VA), the gate of the driving transistor 6 - and the capacitance value CS of the source storage capacitor 5, the capacity divided into a capacitance value CL of the parasitic capacitance 8 of the current control element 7 It is applied to. 従って、このときの駆動トランジスタ6のゲート−ソース間電圧VGSと、駆動トランジスタ6のソース電圧VSとは、それぞれ次式のようになる。 Therefore, the gate of the driving transistor 6 at this time - the source voltage VGS, and the source voltage VS of the driving transistor 6, respectively expressed as follows. VGS=VT+(1−CS/CL)・(VB−VA) …(9) VS=VA−VT+(VB−VA)CS/CL …(10) 【0032】上式からわかるように、(VGS−VT) VGS = VT + As can be seen from (1-CS / CL) · (VB-VA) ... (9) VS = VA-VT + (VB-VA) CS / CL ... (10) [0032] the above equation, (VGS- VT)
が(VB−VA)で決まるので、駆動トランジスタ6のしきい値にばらつきがあっても、このばらつきが補正されるので、VBとVAを適正な値に設定することによって、電流制御素子7に流れる電流値が制御される。 There therefore determined by (VB-VA), even if there are variations in the threshold of the driving transistor 6, so this variation is corrected by setting the VB and VA to a proper value, the current control element 7 current flowing is controlled. 【0033】次に、選択ゲートトランジスタ4を導通状態から遮断状態に切り替えることによって、非選択期間に入る。 Next, by switching the shut-off state the selection gate transistor 4 from a conductive state, into the non-selection period. 非選択期間に入ると、駆動トランジスタ6のゲート−ソース間電圧VGSは、保持容量5によって保持されるようになる。 Once in the non-selection period, the gate of the driving transistor 6 - source voltage VGS will be held by the storage capacitor 5. 駆動トランジスタ6のソース電圧V Source voltage V of the drive transistor 6
Sは、駆動トランジスタ6を介して電流制御素子7の寄生容量8に電荷が充電されるのに応じて上昇し、駆動トランジスタ6のゲート電圧VGも、保持容量5を介してゲート−ソース間電圧VGSを一定に維持したまま、同時に上昇する。 S is raised in response to the charge in the parasitic capacitance 8 of the current control element 7 is charged through the driving transistor 6, the gate voltage VG of the driving transistor 6 is also the gate through the storage capacitor 5 - source voltage while maintaining the VGS constant, to rise at the same time. 電流制御素子7は、駆動トランジスタ6 The current control element 7, the driving transistor 6
のソース電圧VSが、電流制御素子7の順方向の立ち上がり電圧VOFFを超えたとき発光を開始し、以後、非選択期間が終了するまで、発光し続ける。 The source voltage VS of starts emission when it exceeds a forward rise voltage VOFF of the current control element 7, hereinafter, to the non-selection period is completed, it continues to emit light. 電流制御素子7の端子間電圧VLが、駆動トランジスタ6のゲート− Terminal voltage VL of the current control element 7, the gate of the driving transistor 6 -
ソース間電圧VGSによって定まる電流ILを流すのに充分な電圧に到達すると、駆動トランジスタ6のゲート電圧VGとソース電圧VSの上昇は停止して一定となる。 Upon reaching a sufficient voltage to flow a current IL determined by the source voltage VGS, increase in the gate voltage VG and source voltage VS of the driving transistor 6 is constant stopped. その後は、駆動トランジスタ6のゲート−ソース間電圧VGSが保持容量5によって保持されるため、電流制御素子7に一定電流ILが流れ続ける。 Thereafter, the gate of the driving transistor 6 - to-source voltage VGS is held by the storage capacitor 5, a constant current IL continues to flow through the current control device 7. 【0034】このように、この例の電流制御素子の駆動回路では、選択ゲートトランジスタ4と駆動トランジスタ6との2個のトランジスタと、保持容量5とからなる最小限の素子構成で、駆動トランジスタ6のしきい値を補正して、その変化の影響を受けないようにすることができる。 [0034] Thus, in the driving circuit of the current control element in this example, a minimum element configuration consisting of the two transistors of the selection gate transistor 4 and the driving transistor 6, the holding capacitor 5 which, the driving transistor 6 threshold corrected, it is possible to prevent the influence of the change. 本実施例によれば、従来例の電流制御素子の駆動回路と比較して、画素回路を構成する素子数が1/2 According to this embodiment, as compared with the driving circuit of the current control element in the conventional example, the number of elements constituting the pixel circuit 1/2
となるので、画素の開口率を大きくできるとともに、製造プロセスが容易になる。 Since the, it is possible to increase the aperture ratio of the pixel, thereby facilitating the manufacturing process. また、一般に、電流制御素子7の寄生容量8の容量値CLは、保持容量5の容量値C In general, the capacitance value CL of the parasitic capacitance 8 of the current control element 7, the storage capacitor 5 the capacitance C
Sより大きいので、より小さな書き込み電圧で、駆動回路の書き込みを行うことができ、消費電力の点からも有利である。 Is greater than S, a smaller write voltage, it is possible to write drive circuit, which is advantageous from the power point. 【0035】図1に示された第1実施例の駆動回路では、制御方法を変えることによって、異なる動作を行わせることができる。 [0035] In the driving circuit of the first embodiment shown in FIG. 1, by changing the control method, it is possible to perform different operations. 以下においては、この場合の実施例について説明する。 In the following, a description will be given of an embodiment of this case. 【0036】◇第2実施例図7は、本発明の第2実施例である電流制御素子の駆動回路の動作を説明するタイミングチャートである。 [0036] ◇ Second Embodiment FIG. 7 is a timing chart for explaining the operation of the driving circuit of the current control device according to a second embodiment of the present invention. この例の電流制御素子の駆動回路の構成は、図1に示された第1実施例の場合と同様であるが、制御方法が異なっているため、その動作も異なっている。 Configuration of the driving circuit of the current control element of this example is the same as in the first embodiment shown in FIG. 1, since the control method are different, are also different operation. 【0037】以下、図7を参照して、この例の電流制御素子の駆動回路の動作を説明する。 [0037] Hereinafter, with reference to FIG. 7, the operation of the driving circuit of the current control element of this example. 駆動回路の選択期間が開始されると、選択ゲートトランジスタ4が遮断状態から導通状態に切り替えられる。 When the selection period of the drive circuit is started, the selection gate transistor 4 is switched to a conductive state from the cutoff state. このとき、信号線3に入力される電圧は、駆動トランジスタ6がオンするのに充分な大きさの電圧とする。 At this time, the voltage input to the signal line 3, the driving transistor 6 is a large enough voltage to turn on. また、これと同時に、電源線1の電位を0Vとする。 At the same time, the potential of the power supply line 1 and 0V. 駆動トランジスタ6がオンしているため、電流制御素子7の寄生容量8の電荷が、駆動トランジスタ6を介して放電される。 Since the driving transistor 6 is turned on, the charge of the parasitic capacitance 8 of the current control element 7 is discharged via the driving transistor 6. 駆動トランジスタ6のソース電圧VSがゼロになってから、信号線3の電圧を接地電位0Vにする。 The source voltage VS of the driving transistor 6 from becoming zero, the voltage of the signal line 3 to the ground potential 0V. 選択ゲートトランジスタ4 Select gate transistor 4
が導通状態になっているため、保持容量5の電荷が放電されて、駆動トランジスタ6のゲート電圧VGが0Vになる。 Since There are in a conducting state, the charge storage capacitor 5 is discharged, the gate voltage VG of the driving transistor 6 is 0V. 【0038】このあと、電源線1の電圧をもとの電源線電圧レベルに戻す。 [0038] return After this, the voltage of the power supply line 1 to the original power line voltage level. 駆動トランジスタ6のゲート−ソース間電圧VGSはゼロであるため、駆動トランジスタ6 The gate of the driving transistor 6 - for source voltage VGS is zero, the driving transistor 6
のドレイン−ソース間に電流は流れない。 Current does not flow between the source - of the drain. 次に、信号線3の入力電圧を0VからVAに切り替える。 Next, switch the input voltage of the signal line 3 from 0V to VA. 以降の動作は、第1実施例の場合と同様に行われる。 The subsequent operations are performed in the same manner as in the first embodiment. 【0039】このように、この例の電流制御素子の駆動回路では、第1実施例の場合と同様に、選択ゲートトランジスタ4と駆動トランジスタ6との2個のトランジスタと、保持容量5とからなる最小限の素子構成で、駆動トランジスタ6のしきい値を補正して、その変化の影響を受けないようにすることができるとともに、選択期間の初期に駆動トランジスタをオンにし、電源線1の電位を0Vにするので、電流制御素子7の寄生容量8の電荷を駆動トランジスタ6を経て電源線1に放電することができ、従って、駆動トランジスタ6のソース電圧の降下が速いので、選択期間を短縮することが可能になる。 [0039] Thus, in the driving circuit of the current control element in this example, as in the case of the first embodiment, consists of two transistors of a selection gate transistor 4 and the driving transistor 6, the holding capacitor 5 which with minimal element structure, by correcting the threshold value of the driving transistor 6, it is possible to prevent the influence of the change, turn on initially driving transistor of the selection period, the potential of the power supply line 1 the since to 0V, and it is possible to discharge the parasitic capacitance 8 of the current control element 7 to the power supply line 1 via the driving transistor 6, therefore, the drop of the source voltage of the driving transistor 6 is high, shorter selection period it becomes possible to. 【0040】◇第3実施例図8は、本発明の第3実施例である電流制御素子の駆動回路の構成を示す回路図、図9は、本実施例の電流制御素子の駆動回路の動作を説明するタイミングチャートである。 [0040] ◇ Third Embodiment FIG. 8, a third circuit diagram showing a configuration of a drive circuit of the current control device according to an embodiment of the present invention, FIG. 9, the operation of the driving circuit of the current control element of this example is a timing chart to explain. この例の電流制御素子の駆動回路は、図8に示すように、電源線1と接地線2と信号線3との間に接続された、選択ゲートトランジスタ4と、保持容量5と、駆動トランジスタ6と、電流制御素子7と、寄生容量8 Driving circuit of the current control element of this example, as shown in FIG. 8, which is connected between the power supply line 1 and ground line 2 and the signal line 3, and the select gate transistor 4, and the storage capacitor 5, the driving transistor 6, a current control element 7, the parasitic capacitance 8
と、スイッチングトランジスタ9とから概略構成されている。 When, it is schematically a switching transistor 9. 【0041】この例の電流制御素子の駆動回路においては、電源線1,接地線2,信号線3,選択ゲートトランジスタ4,保持容量5,駆動トランジスタ6,電流制御素子7及び寄生容量8の構成は、図1に示された第1実施例の場合と同様であるが、これらに加えて、図8に示すスイッチングトランジスタ9を有する点が、第1実施例の場合と異なっている。 [0041] In the driving circuit of the current control element in this example, the power line 1, the ground line 2, the signal lines 3, the structure of the selection gate transistor 4, storage capacitor 5, the driving transistor 6, the current control element 7 and the parasitic capacitance 8 is the same as in the first embodiment shown in FIG. 1, in addition to these, it is that it has a switching transistor 9 shown in FIG. 8 is different from the case of the first embodiment. スイッチングトランジスタ9 Switching transistor 9
は、Nチャネル電界効果トランジスタからなり、ゲート電極を選択線に接続され、ドレイン電極を駆動トランジスタ6のソース電極及び保持容量5の一端に接続され、 Is an N-channel field effect transistor, the gate electrode of which is connected to the selection line is connected to the drain electrode to the source electrode and the one end of the storage capacitor 5 of the driving transistor 6,
ソース電極を接地線2に接続されている。 The source electrode is connected to the ground line 2. 【0042】以下、図8,図9を参照して、この例の電流制御素子の駆動回路の動作を説明する。 [0042] Hereinafter, with reference to FIGS. 8 and 9, the operation of the driving circuit of the current control element of this example. 駆動回路の選択期間が開始されると、選択線からの制御によって、選択ゲートトランジスタ4とスイッチングトランジスタ9 When the selection period of the drive circuit is started, the control of the selection lines, select gate transistor 4 and the switching transistor 9
が、遮断状態から導通状態に切り替えられる。 But it is switched from the disconnected state to the conduction state. このとき、信号線3に入力される電圧は、接地線2と同じ0V At this time, the voltage input to the signal line 3, the same 0V and the ground line 2
とする。 To. 選択ゲートトランジスタ4とスイッチングトランジスタ9が導通状態になったことによって、保持容量5の電荷と、電流制御素子7の寄生容量8の電荷とが放電されるので、駆動トランジスタ6のゲート電圧VGとソース電圧VSが0Vとなる。 By selecting gate transistor 4 and the switching transistor 9 becomes conductive, and the charge storage capacitor 5, since the charge of the parasitic capacitance 8 of the current control element 7 is discharged, the gate voltage VG and the source of the driving transistor 6 the voltage VS becomes 0V. このとき、駆動トランジスタ6のゲート−ソース間電圧VGSは0Vなので、駆動トランジスタ6のドレイン−ソース間には電流が流れない。 At this time, the gate of the driving transistor 6 - source voltage VGS is because 0V, the drain of the driving transistor 6 - no current flows between the source. 次に、選択線からの制御によって、スイッチングトランジスタ9が遮断状態とされるとともに、信号線3 Next, the control of the selection line, the switching transistor 9 is a cut-off state, the signal lines 3
の入力電圧が、0VからVAに切り替えられる。 Input voltage of is switched from 0V to VA. これ以降の動作は、第1実施例の場合と同様である。 The subsequent operation is the same as in the first embodiment. 【0043】このように、この例の電流制御素子の駆動回路によれば、第1実施例の場合と同様に駆動トランジスタ6のしきい値を補正して、その変化の影響を受けないようにすることができる。 [0043] Thus, according to the driving circuit of the current control element of this example, similarly to the case the threshold of the driving transistor 6 of the first embodiment is corrected so as not to be affected by the change can do. この際、第1実施例の場合と比較して、スイッチングトランジスタ9が余分に必要となるが、スイッチングトランジスタ9による保持容量5及び電流制御素子7の寄生容量8のリセットを、選択ゲートトランジスタ4による保持容量5の書き込みと独立に行うことができるので、リセットの時期を選択することによって、保持容量5及び寄生容量8のリセットをより確実に行うことができるようになる。 In this case, as compared with the case of the first embodiment, the switching transistor 9 is additionally required, the resetting of the parasitic capacitance 8 of the storage capacitor 5 and a current control device 7 by the switching transistor 9, by selective gate transistor 4 can be performed independently of the write of the storage capacitor 5, by selecting the timing of reset, it is possible to perform the reset of the storage capacitor 5 and the parasitic capacitance 8 more reliably. 【0044】◇第4実施例図10は、本発明の第4実施例である電流制御素子の駆動回路の構成を示す回路図、図11は、本実施例の電流制御素子の駆動回路の動作を説明するタイミングチャートである。 [0044] ◇ Fourth Embodiment FIG. 10 is a fourth circuit diagram showing a configuration of a drive circuit of the current control device according to an embodiment of the present invention, FIG. 11, the operation of the driving circuit of the current control element of this example is a timing chart to explain. この例の電流制御素子の駆動回路は、図10 Driving circuit of the current control element in this example, FIG. 10
に示すように、電源線1と接地線2と信号線3との間に接続された、選択ゲートトランジスタ4と、保持容量5 As shown in, connected between the power supply line 1 and ground line 2 and the signal line 3, and the select gate transistor 4, storage capacitor 5
と、駆動トランジスタ6と、電流制御素子7と、寄生容量8と、スイッチングトランジスタ10とから概略構成されている。 When, a driving transistor 6, a current control element 7, the parasitic capacitance 8 is a schematic configuration of a switching transistor 10. 【0045】この例の電流制御素子の駆動回路においては、電源線1,接地線2,信号線3,選択ゲートトランジスタ4,保持容量5,駆動トランジスタ6,電流制御素子7及び寄生容量8の構成は、図1に示された第1実施例の場合と同様であるが、これらに加えて、図10に示すスイッチングトランジスタ10を有する点が、第1 [0045] In the driving circuit of the current control element in this example, the power line 1, the ground line 2, the signal lines 3, the structure of the selection gate transistor 4, storage capacitor 5, the driving transistor 6, the current control element 7 and the parasitic capacitance 8 is the same as in the first embodiment shown in FIG. 1, in addition to these, it is that it has a switching transistor 10 shown in FIG. 10, the first
実施例の場合と異なっている。 It is different from the case of Example. スイッチングトランジスタ10は、Nチャネル電界効果トランジスタからなり、 The switching transistor 10 is an N-channel field-effect transistor,
ゲート電極を選択線に接続され、ドレイン電極を駆動トランジスタ6のゲート電極及び保持容量5の一端に接続され、ソース電極を接地線2に接続されている。 The gate electrode of which is connected to the selection line is connected to the drain electrode at one end of the gate electrode and the storage capacitor 5 of the driving transistor 6 is connected to the source electrode to the ground line 2. 【0046】以下、図10,図11を参照して、この例の電流制御素子の駆動回路の動作を説明する。 [0046] Hereinafter, FIG. 10, with reference to FIG. 11, the operation of the driving circuit of the current control element of this example. 駆動回路の選択期間が開始される前の一定期間、選択線からの制御によって、スイッチングトランジスタ10を導通状態にする。 Certain period before the selection period of the driving circuit is started, the control of the selection line, the switching transistor 10 conductive. スイッチングトランジスタ10が導通状態なので、駆動トランジスタ6のゲート電圧VGはゼロとなり、これによって、駆動トランジスタ6のゲート−ソース間電圧VGSは負の電圧となるため、駆動トランジスタ6は遮断状態となる。 Since the switching transistor 10 is conductive, the gate voltage VG of the driving transistor 6 becomes zero, thereby, the gate of the driving transistor 6 - source voltage VGS since a negative voltage, the driving transistor 6 is a cut-off state. このとき、電流制御素子7の寄生容量8に蓄積されている電荷は、電流制御素子7を介して接地線2に放電される。 At this time, charges accumulated in the parasitic capacitance 8 of the current control element 7 is discharged to the ground line 2 via a current control element 7. スイッチングトランジスタ10が導通状態になってから、充分長い時間が経過すると、電流制御素子7の寄生容量8に蓄積されていた電荷はすべて放電されて、駆動トランジスタ6のソース電圧VSは0Vとなる。 After the switching transistor 10 becomes conductive, the long enough time has elapsed, all the charges accumulated in the parasitic capacitance 8 of the current control element 7 is discharged, the source voltage VS of the driving transistor 6 becomes 0V. この期間中、選択ゲートトランジスタ4は、選択線からの制御によって、遮断状態とされている。 During this period, a selection gate transistor 4, the control of the selection line, there is a cut-off state. 【0047】次に、駆動回路の選択期間が開始されると、選択線からの制御によって、スイッチングトランジスタ10が、導通状態から遮断状態に切り替えられる。 Next, the selection period of the driving circuit is started, the control of the selection line, the switching transistor 10 is switched from the conduction state to the cutoff state.
次に、選択ゲートトランジスタ4が、選択線からの制御によって、遮断状態から導通状態に切り替えられる。 Next, the select gate transistor 4, the control of the selection line is switched from the disconnected state to the conduction state. このとき、信号線3の入力電圧VDATAとして、VAが入力されている。 At this time, as the input voltage VDATA of the signal line 3, VA is input. これ以降の動作は、第1実施例の場合と同様である。 The subsequent operation is the same as in the first embodiment. 【0048】このように、この例の電流制御素子の駆動回路によれば、第1実施例の場合と同様に駆動トランジスタ6のしきい値を補正して、その変化の影響を受けないようにすることができる。 [0048] Thus, according to the driving circuit of the current control element of this example, similarly to the case the threshold of the driving transistor 6 of the first embodiment is corrected so as not to be affected by the change can do. この際、第1実施例の場合と比較して、スイッチングトランジスタ10が余分に必要となるが、スイッチングトランジスタ10による保持容量5及び電流制御素子7の寄生容量8のリセットを、 In this case, as compared with the case of the first embodiment, the switching transistor 10 is additionally required, the resetting of the parasitic capacitance 8 of the storage capacitor 5 and a current control device 7 by the switching transistor 10,
選択ゲートトランジスタ4による保持容量5の書き込みと独立に行うことができるので、リセットの時期を選択することによって、保持容量5及び寄生容量8のリセットをより確実に行うことができるようになる。 Can be performed independently of the write of the storage capacitor 5 by the selection gate transistor 4, by selecting the timing of reset, it is possible to perform the reset of the storage capacitor 5 and the parasitic capacitance 8 more reliably. 【0049】以上の各実施例においては,電流制御素子の駆動回路をすべてNチャネル電界効果トランジスタによって構成したが、駆動回路をPチャネル電界効果トランジスタによって構成することも可能である。 [0049] In each embodiment described above, is constituted by all N-channel field-effect transistor driving circuit of the current control element, it is also possible to constitute the driving circuit by the P-channel field effect transistor. 以下においては、この場合の実施例について説明する。 In the following, a description will be given of an embodiment of this case. 【0050】◇第5実施例図12は、本発明の第5実施例である電流制御素子の駆動回路の構成を示す回路図である。 [0050] ◇ Fifth Embodiment FIG. 12 is a circuit diagram showing a configuration of a drive circuit of the current control device of a fifth embodiment of the present invention. この例の電流制御素子の駆動回路は、図12に示すように、電源線1と接地線2と信号線3との間に接続された、選択ゲートトランジスタ4Aと、保持容量5Aと、駆動トランジスタ6A Driving circuit of the current control element of this example, as shown in FIG. 12, which is connected between the power supply line 1 and ground line 2 and the signal line 3, and the selection gate transistors 4A, a storage capacitor 5A, the driving transistor 6A
と、電流制御素子7Aと、寄生容量8Aとから概略構成されている。 When a current control element 7A, is schematically composed of a parasitic capacitance 8A. 選択ゲートトランジスタ4Aは、Pチャネル電界効果トランジスタからなり、ゲート電極を選択線(不図示)に接続され、ソース電極を信号線3に接続され、ドレイン電極を駆動トランジスタ6Aのゲート電極に接続されている。 Selection gate transistors 4A is a P-channel field effect transistor, the gate electrode of which is connected to the selection line (not shown), is connected to the source electrode to the signal line 3 is connected to the drain electrode to the gate electrode of the driving transistor 6A there. 保持容量5Aは、駆動トランジスタ6Aのゲート電極とソース電極の間に接続されてる。 Storage capacitor 5A is connected between the gate electrode and the source electrode of the driving transistor 6A. 駆動トランジスタ6Aは、Pチャネル電界効果トランジスタからなり、ゲート電極を選択ゲートトランジスタ4のドレイン電極と保持容量5Aの一端に接続され、ソース電極を電流制御素子7Aのカソードに接続され、ドレイン電極を接地線2に接続されている。 Driving transistor 6A is a P-channel field effect transistor, the gate electrode of which is connected to one end of the drain electrode and the storage capacitor 5A of the select gate transistor 4 is connected to the source electrode to the cathode current control device 7A, grounded drain electrode It is connected to the line 2. 電流制御素子7A Current control element 7A
は、電源線1と、駆動トランジスタ6Aのソース電極の間に接続され、駆動トランジスタ6Aの電流ILに応じた輝度で発光する。 Includes a power supply line 1 is connected between the source electrode of the driving transistor 6A, it emits light at a luminance corresponding to the current IL of the driving transistor 6A. 寄生容量8Aは、電流制御素子7A Parasitic capacitance 8A, the current control element 7A
の両端の寄生容量である。 It is a parasitic capacitance of the both ends of. 【0051】この例の電流制御素子の駆動回路は、図1 The driving circuit of the current control element in this example, FIG. 1
に示された第1実施例の場合のNチャネル電界効果トランジスタからなる選択ゲートトランジスタ4及び駆動トランジスタ6を、Pチャネル電界効果トランジスタからなる選択ゲートトランジスタ4A及び駆動トランジスタ6AにPチャネル電界効果トランジスタによって置き替えたものであって、従って、図1に示された第1実施例の場合と比べて、電圧の関係が逆になるので、電流の向きが逆になるが、その動作は、第1実施例の場合と同様であって、図2に示されたタイミングチャートを適用することができるので、以下においては、詳細な説明を省略する。 The selection gate transistor 4 and the driving transistor 6 formed of an N-channel field effect transistor in the case of the first embodiment shown in, by the P-channel field-effect transistor to the selection gate transistors 4A and the driving transistor 6A composed of the P-channel field effect transistor be those which replaced, therefore, as compared with the case of the first embodiment shown in FIG. 1, the relationship of the voltage is reversed, the direction of current is reversed, the operation is first a as in the embodiment, it is possible to apply the timing chart shown in FIG. 2, in the following, a detailed description thereof will be omitted. 【0052】このように、この例の電流制御素子の駆動回路では、選択ゲートトランジスタ4Aと駆動トランジスタ6Aとの2個のトランジスタと、保持容量5Aとからなる最小限の素子構成で、駆動トランジスタ6Aのしきい値を補正して、その変化の影響を受けないようにすることができる。 [0052] Thus, in the driving circuit of the current control element in this example, a minimum element configuration consisting of the two transistors of the selection gate transistors 4A and the driving transistor 6A, the storage capacitor 5A, the driving transistor 6A threshold corrected, it is possible to prevent the influence of the change. 本実施例によれば、第1実施例の場合と同様に、従来例の電流制御素子の駆動回路と比較して、画素回路を構成する素子数を逓減して、画素の開口率を大きくできるとともに、製造プロセスが容易になり、さらに、消費電力が少ない利点がある。 According to this embodiment, as in the case of the first embodiment, as compared with the driving circuit of the current control element in the conventional example, by decreasing the number of elements that constitute the pixel circuit can increase the aperture ratio of the pixel together, it simplifies the manufacturing process, further, the advantage low power consumption. 【0053】◇第6実施例この例の電流制御素子の駆動回路の構成は、図12に示された第5実施例の場合と同様であるが、制御方法が異なっているため、その動作も異なっている。 [0053] ◇ configuration of the driving circuit of the current control element of the sixth embodiment This example is the same as in the fifth embodiment shown in FIG. 12, since the control method is different, also the operation It is different. この例の電流制御素子の駆動回路は、第2実施例の場合のNチャネル電界効果トランジスタからなる選択ゲートトランジスタ4及び駆動トランジスタ6を、Pチャネル電界効果トランジスタからなる選択ゲートトランジスタ4A及び駆動トランジスタ6Aによって置き替えたものであって、 Driving circuit of the current control element in this example, N a selection gate transistor 4 and the driving transistor 6 consisting channel field effect transistor, the selection gate composed of a P-channel field effect transistor transistor 4A and the driving transistor 6A in the case of the second embodiment be one that was replaced by,
従って、第2実施例の場合と比べて、電圧の関係が逆になるので、電流の向きが逆になるが、その動作は、第2 Therefore, as compared with the case of the second embodiment, since the relationship between the voltage is reversed, the direction of current is reversed, the operation is the second
実施例の場合と同様であって、図7に示されたタイミングチャートを適用することができるので、以下においては、詳細な説明を省略する。 A as in the embodiment, it is possible to apply the timing chart shown in FIG. 7, in the following, a detailed description thereof will be omitted. 【0054】このように、この例の電流制御素子の駆動回路では、第5実施例の場合と同様に、選択ゲートトランジスタ4Aと駆動トランジスタ6Aとの2個のトランジスタと、保持容量5Aとからなる最小限の素子構成で、駆動トランジスタ6Aのしきい値を補正して、その変化の影響を受けないようにすることができるとともに、駆動トランジスタ6Aのソース電圧の降下が速いので、選択期間を短縮することができる。 [0054] Thus, in the driving circuit of the current control element in this example, as in the case of the fifth embodiment consists of a two transistors of the selection gate transistors 4A and the driving transistor 6A, the storage capacitor 5A with minimal element structure, by correcting the threshold value of the driving transistor 6A, it is possible to prevent the influence of the change, because the drop in the source voltage of the driving transistor 6A is fast, shorter selection period can do. 【0055】◇第7実施例図13は、本発明の第7実施例である電流制御素子の駆動回路の構成を示す回路図である。 [0055] ◇ Seventh Embodiment FIG. 13 is a circuit diagram showing a configuration of a drive circuit of the current control device according to a seventh embodiment of the present invention. この例の電流制御素子の駆動回路は、図13に示すように、電源線1と接地線2と信号線3との間に接続された、選択ゲートトランジスタ4Aと、保持容量5Aと、駆動トランジスタ6A Driving circuit of the current control element of this example, as shown in FIG. 13, which is connected between the power supply line 1 and ground line 2 and the signal line 3, and the selection gate transistors 4A, a storage capacitor 5A, the driving transistor 6A
と、電流制御素子7Aと、寄生容量8Aと、スイッチングトランジスタ9Aとから概略構成されている。 When a current control element 7A, the parasitic capacitance 8A, is schematically composed of a switching transistor 9A. 【0056】この例の電流制御素子の駆動回路においては、電源線1,接地線2,信号線3,選択ゲートトランジスタ4A,保持容量5A,駆動トランジスタ6A,電流制御素子7A及び寄生容量8Aの構成は、図12に示された第5実施例の場合と同様であるが、これらに加えて、図13に示すスイッチングトランジスタ9Aを有する点が、第5実施例の場合と異なっている。 [0056] In the driving circuit of the current control element in this example, the power line 1, the ground line 2, the signal lines 3, the selection gate transistors 4A, storage capacitor 5A, the driving transistor 6A, the configuration of the current control element 7A and the parasitic capacitance 8A is the same as in the fifth embodiment shown in FIG. 12, in addition to these, it is that it has a switching transistor 9A shown in FIG. 13 are different from those of the fifth embodiment. スイッチングトランジスタ9Aは、Pチャネル電界効果トランジスタからなり、ゲート電極を選択線に接続され、ソース電極を電源線1に接続され、ドレイン電極を駆動トランジスタ6Aのソース電極及び保持容量5Aの一端に接続されている。 The switching transistor 9A is a P-channel field effect transistor, the gate electrode of which is connected to the selection line is connected to the source electrode to the power supply line 1 is connected to the drain electrode to the one end of the source electrode and the storage capacitor 5A of the driving transistor 6A ing. 【0057】この例の電流制御素子の駆動回路は、図8 The drive circuit of the current control element in this example, FIG. 8
に示された第3実施例の場合のNチャネル電界効果トランジスタからなる選択ゲートトランジスタ4,駆動トランジスタ6及びスイッチングトランジスタ9を、Pチャネル電界効果トランジスタからなる選択ゲートトランジスタ4A,駆動トランジスタ6A及びスイッチングトランジスタ9Aによって置き替えたものであって、従って、図8に示された第3実施例の場合と比べて、電圧の関係が逆になり、電流の向きが逆になるが、その動作は、第3実施例の場合と同様であって、図9に示されたタイミングチャートを適用することができるので、以下においては、詳細な説明を省略する。 Third Embodiment select gate transistor consisting of N-channel field effect transistor in the case of that shown in 4, the driving transistor 6 and the switching transistor 9, the select gate transistor 4A consisting of P-channel field effect transistor, the driving transistor 6A and the switching transistor be those which replaced by 9A, therefore, as compared with the case of the third embodiment shown in FIG. 8, the relationship of the voltage is reversed, the direction of current is reversed, the operation is the 3 a as in the embodiment, it is possible to apply the timing chart shown in FIG. 9, in the following, a detailed description thereof will be omitted. 【0058】このように、この例の電流制御素子の駆動回路によれば、第5実施例の場合と同様に駆動トランジスタ6Aのしきい値を補整して、その変化の影響を受けないようにすることができる。 [0058] Thus, according to the driving circuit of the current control element in this example, the case of the fifth embodiment and to compensate the threshold similarly driving transistor 6A, so as not to be influenced by the change can do. この際、第5実施例の場合と比較して、スイッチングトランジスタ9Aが余分に必要となるが、スイッチングトランジスタ9Aによる保持容量5A及び電流制御素子7の寄生容量8のリセットを、選択ゲートトランジスタ4Aによる保持容量5Aの書き込みと独立に行うことができるので、リセットの時期を選択することによって、保持容量5A及び寄生容量8Aのリセットをより確実に行うことができるようになる。 In this case, as compared with the case of the fifth embodiment, the switching transistor 9A but is additionally required, the resetting of the parasitic capacitance 8 of the storage capacitor 5A and the current control device 7 by the switching transistors 9A, according to the selection gate transistor 4A can be performed independently of the write of the storage capacitor 5A, by selecting the timing of reset, it is possible to perform the reset of the storage capacitor 5A and parasitic capacitance 8A reliably. 【0059】◇第8実施例図14は、本発明の第8実施例である電流制御素子の駆動回路の構成を示す回路図である。 [0059] ◇ Eighth Embodiment FIG. 14 is a circuit diagram showing a configuration of a drive circuit of the current control device according to an eighth embodiment of the present invention. この例の電流制御素子の駆動回路は、図13に示すように、電源線1と接地線2と信号線3との間に接続された、選択ゲートトランジスタ4Aと、保持容量5Aと、駆動トランジスタ6A Driving circuit of the current control element of this example, as shown in FIG. 13, which is connected between the power supply line 1 and ground line 2 and the signal line 3, and the selection gate transistors 4A, a storage capacitor 5A, the driving transistor 6A
と、電流制御素子7Aと、寄生容量8Aと、スイッチングトランジスタ10Aとから概略構成されている。 When a current control element 7A, the parasitic capacitance 8A, is schematically composed of a switching transistor 10A. 【0060】この例の電流制御素子の駆動回路においては、電源線1,接地線2,信号線3,選択ゲートトランジスタ4A,保持容量5A,駆動トランジスタ6A,電流制御素子7A及び寄生容量8Aの構成は、図12に示された第5実施例の場合と同様であるが、これらに加えて、図14に示すスイッチングトランジスタ10Aを有する点が、第5実施例の場合と異なっている。 [0060] In the driving circuit of the current control element in this example, the power line 1, the ground line 2, the signal lines 3, the selection gate transistors 4A, storage capacitor 5A, the driving transistor 6A, the configuration of the current control element 7A and the parasitic capacitance 8A is the same as in the fifth embodiment shown in FIG. 12, in addition to these, it is that it has a switching transistor 10A shown in FIG. 14 are different from those of the fifth embodiment. スイッチングトランジスタ10Aは、Pチャネル電界効果トランジスタからなり、ゲート電極を選択線に接続され、ソース電極を電源線1に接続され、ドレイン電極を駆動トランジスタ6Aのゲート電極及び保持容量5Aの一端に接続されている。 The switching transistor 10A is a P-channel field effect transistor, the gate electrode of which is connected to the selection line is connected to the source electrode to the power supply line 1 is connected to the drain electrode at one end of the gate electrode and the storage capacitor 5A of the driving transistor 6A ing. 【0061】この例の電流制御素子の駆動回路は、図1 [0061] a driving circuit of the current control element in this example, FIG. 1
0に示された第4実施例の場合のNチャネル電界効果トランジスタからなる選択ゲートトランジスタ4,駆動トランジスタ6及びスイッチングトランジスタ10を、P In the case of the fourth embodiment shown in 0 N-channel select gate transistor 4 composed of a field effect transistor, the driving transistor 6 and the switching transistor 10, P
チャネル電界効果トランジスタからなる選択ゲートトランジスタ4A,駆動トランジスタ6A及びスイッチングトランジスタ10Aによって置き替えたものであって、 Selection gate transistors 4A consisting channel field effect transistor, there is that replaced by the driving transistors 6A and the switching transistors 10A,
従って、図10に示された第4実施例の場合と比べて、 Therefore, as compared with the case of the fourth embodiment shown in FIG. 10,
電圧の関係が逆になるので、電流の向きが逆になるが、 The relationship of the voltage is reversed, the direction of current is reversed,
その動作は、第4実施例の場合と同様であって、図11 Its operation is similar to what the case of the fourth embodiment, FIG. 11
に示されたタイミングチャートを適用することができるので、以下においては、詳細な説明を省略する。 It is possible to apply the timing chart shown in, in the following, a detailed description thereof will be omitted. 【0062】このように、この例の電流制御素子の駆動回路によれば、第5実施例の場合と同様に駆動トランジスタ6Aのしきい値を補正して、その変化の影響を受けないようにすることができる。 [0062] Thus, according to the driving circuit of the current control element of this embodiment, the threshold as in the case the driving transistor 6A of the fifth embodiment is corrected so as not to be affected by the change can do. この際、第5実施例の場合と比較して、スイッチングトランジスタ10Aが余分に必要となるが、スイッチングトランジスタ10Aによる保持容量5A及び電流制御素子7の寄生容量8のリセットを、選択ゲートトランジスタ4Aによる保持容量5 In this case, as compared with the case of the fifth embodiment, the switching transistor 10A is is additionally required, the resetting of the parasitic capacitance 8 of the storage capacitor 5A and the current control device 7 by the switching transistors 10A, due to the selection gate transistor 4A retention capacity 5
Aの書き込みと独立に行うことができるので、リセットの時期を選択することによって、保持容量5A及び寄生容量8Aのリセットをより確実に行うことができるようになる。 Can be performed independently of the write A, by selecting the timing of reset, it is possible to perform the reset of the storage capacitor 5A and parasitic capacitance 8A reliably. 【0063】以上、この発明の実施例を図面により詳述してきたが、具体的な構成はこの実施例に限られたものではなく、この発明の要旨を逸脱しない範囲の設計の変更等があってもこの発明に含まれる。 [0063] Having thus described in detail with reference to the drawings an embodiment of the present invention, the specific configuration is not limited to this embodiment, there is a change of the design within the range of not departing from the gist of the invention also included in this invention. 例えば、第3実施例,第4実施例及び第7実施例,第8実施例において、 For example, the third embodiment, the fourth embodiment and the seventh embodiment, the eighth embodiment,
スイッチングトランジスタによる保持容量5と寄生容量8の放電は、非選択期間でもよく、又は選択期間の初期でもよい。 Discharge of the parasitic capacitance 8 and the holding capacitor 5 by the switching transistor may be a non-selection period, or early in may select period. 非選択期間の場合は、その終期に限らず、任意のタイミングで行うことができる。 For non-selection period is not limited to its end, it can be performed at any timing. 選択期間の初期の場合は、選択ゲートトランジスタをオフにしておくことが必要である。 For initial selection period, it is necessary to keep off the selection gate transistor. また、各実施例において、駆動トランジスタがNチャネル電界効果トランジスタ又はPチャネル電界効果トランジスタの場合に、その他の選択ゲートトランジスタ及びスイッチングトランジスタは、Nチャネル電界効果トランジスタ又はPチャネル電界効果トランジスタに限らず、Nチャネル電界効果トランジスタとP Further, in each embodiment, when the driving transistor is an N-channel field effect transistor or P-channel field effect transistor, the other of the selection gate transistor and the switching transistor is not limited to the N-channel field effect transistor or P-channel field effect transistor, N-channel field effect transistor and the P
チャネル電界効果トランジスタとを任意に混用することが可能である。 It is possible to mix and channel field effect transistor arbitrarily. さらに、この発明の電流制御素子の駆動回路は、多数の電流制御素子を平面状に、行方向と列方向とにマトリクス状に配列した画像表示装置における、 Furthermore, the driving circuit of the current control device of the invention, a number of current control elements in a plane, in the image display device are arranged in a matrix in a row direction and a column direction,
電流制御素子の駆動回路にも適用可能であって、この場合に前述の各実施例の効果を得られることは明らかである。 A can also be applied to a driving circuit of the current control element, it is apparent that an effect is obtained in the embodiments described above in this case. また、第3、第4の実施例では、スイッチングトランジスタ9のソース電極が、接地線2に接続されているが、接地線2とは異なる電圧の他の電源線に接続し、リセット時の駆動トランジスタ6のソース電圧VSを0V Further, third and fourth embodiment, the source electrode of the switching transistor 9, are connected to the ground line 2 is connected to the other power supply line of the voltage different from the ground line 2, the driving of the reset 0V the source voltage VS of the transistor 6
ではない電圧に設定することで、回路設計の許容度を広げることもできる。 By setting the voltage not, it may also broaden the tolerance of the circuit design. 第7、第8の実施例についても同様な変更が可能である。 Seventh, it is possible to similar changes also, Embodiment 8. 【0064】 【発明の効果】以上説明したように、本発明の電流制御素子の駆動回路及び画像表示装置によれば、電流制御素子を駆動する駆動トランジスタのしきい値特性にばらつきがあっても影響を受けないようにすることができるとともに、従来の同様な電流制御素子の駆動回路と比較して、画素回路を構成する素子数を少なくすることができるので、画素の開口率を大きくできるとともに、製造プロセスが容易になる。 [0064] As has been described in the foregoing, according to the driving circuit and the image display apparatus of the current control device of the present invention, even if there are variations in the threshold characteristics of the driving transistor that drives the current control element effect it is possible to make not subject to, as compared with the driving circuit of the conventional similar current control element, it is possible to reduce the number of elements constituting the pixel circuit, it is possible to increase the aperture ratio of the pixel , to facilitate the manufacturing process. また、小さな書き込み電圧で、駆動回路の書き込みを行うことができるので、消費電力の点からも有利である。 Further, a small write voltage, it is possible to perform the writing of the drive circuit, which is advantageous from the power point.

【図面の簡単な説明】 【図1】本発明の第1実施例である電流制御素子の駆動回路の構成を示す回路図である。 Is a circuit diagram showing a configuration of a drive circuit of the current control element is a first embodiment of the BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] present invention. 【図2】同実施例の電流制御素子の駆動回路の動作を説明するタイミングチャートである。 2 is a timing chart for explaining the operation of the driving circuit of the current control element of the embodiment. 【図3】同実施例における駆動トランジスタのIDS− [Figure 3] of the driving transistor in the embodiment IDS-
VGS特性を示す図である。 It is a diagram illustrating a VGS characteristic. 【図4】同実施例における電流制御素子のIL−VL特性を示す図である。 4 is a diagram showing the IL-VL characteristic of the current control element in the same embodiment. 【図5】駆動トランジスタの特性がばらついているときのIDS−VGS特性を示す図である。 5 is a diagram showing the IDS-VGS characteristics when is varied characteristics of the driving transistor. 【図6】駆動トランジスタの特性がばらついているときのVGSの過渡特性を示す図である。 6 is a diagram showing the transient characteristics of the VGS when the characteristics of the driving transistor is varied. 【図7】本発明の第2実施例である電流制御素子の駆動回路の動作を説明するタイミングチャートである。 7 is a timing chart for explaining the operation of the driving circuit of the current control device according to a second embodiment of the present invention. 【図8】本発明の第3実施例である電流制御素子の駆動回路の構成を示す回路図である。 8 is a circuit diagram showing a configuration of a drive circuit of the current control element is a third embodiment of the present invention. 【図9】同実施例の電流制御素子の駆動回路の動作を説明するタイミングチャートである。 9 is a timing chart for explaining the operation of the driving circuit of the current control element of the embodiment. 【図10】本発明の第4実施例である電流制御素子の駆動回路の構成を示す回路図である。 10 is a circuit diagram showing a configuration of a drive circuit of the current control device of a fourth embodiment of the present invention. 【図11】同実施例の電流制御素子の駆動回路の動作を説明するタイミングチャートである。 11 is a timing chart for explaining the operation of the driving circuit of the current control element of the embodiment. 【図12】本発明の第5実施例である電流制御素子の駆動回路の構成を示す回路図である。 12 is a circuit diagram showing a configuration of a drive circuit of the current control device of a fifth embodiment of the present invention. 【図13】本発明の第7実施例である電流制御素子の駆動回路の構成を示す回路図である。 13 is a circuit diagram showing a configuration of a drive circuit of the current control device according to a seventh embodiment of the present invention. 【図14】本発明の第8実施例である電流制御素子の駆動回路の構成を示す回路図である。 14 is a circuit diagram showing a configuration of a drive circuit of the current control device according to an eighth embodiment of the present invention. 【図15】第1の従来例の電流制御素子の駆動回路の構成を示す図である。 15 is a diagram showing a configuration of a drive circuit of the current control device of the first conventional example. 【図16】駆動トランジスタの特性がばらついているときのIDS−VGS特性を示す図である。 16 is a diagram showing the IDS-VGS characteristics when is varied characteristics of the driving transistor. 【図17】第2の従来例の電流制御素子の駆動回路の構成を示す図である。 17 is a diagram showing a configuration of a drive circuit of the current control element of the second conventional example. 【図18】第2の従来例の電流制御素子の駆動回路の動作を説明するタイミングチャートである。 18 is a timing chart for explaining the operation of the driving circuit of the current control element of the second conventional example. 【符号の説明】 1 電源線(第1の電源線) 2 接地線(第2の電源線) 3 信号線4,4A 選択ゲートトランジスタ5,5A 保持容量6,6A 駆動トランジスタ7,7A 電流制御素子8,8A 寄生容量9,9A スイッチングトランジスタ10,10A スイッチングトランジスタ [Description of Reference Numerals] 1 Power line (first power supply line) second ground line (second power supply line) third signal line 4,4A select gate transistor 5,5A storage capacitor 6,6A driving transistor 7,7A current control element 8,8A parasitic capacitance 9,9A switching transistor 10,10A switching transistor

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl. 7識別記号 FI テーマコート゛(参考) H03K 17/687 H05B 33/14 A H05B 33/14 H03K 17/687 H Fターム(参考) 3K007 AB02 AB06 AB17 AB18 BA06 BB07 DB03 GA04 5C080 AA06 BB05 DD05 DD22 DD26 DD28 EE28 FF11 JJ03 JJ04 JJ05 5J055 AX04 AX49 BX16 CX29 DX13 DX14 DX53 DX55 EX01 EX07 EX21 EY00 EY10 EY21 EY29 FX12 FX17 FX24 FX35 GX00 GX01 GX06 ────────────────────────────────────────────────── ─── of the front page continued (51) Int.Cl. 7 identification mark FI theme Court Bu (reference) H03K 17/687 H05B 33/14 a H05B 33/14 H03K 17/687 H F -term (reference) 3K007 AB02 AB06 AB17 AB18 BA06 BB07 DB03 GA04 5C080 AA06 BB05 DD05 DD22 DD26 DD28 EE28 FF11 JJ03 JJ04 JJ05 5J055 AX04 AX49 BX16 CX29 DX13 DX14 DX53 DX55 EX01 EX07 EX21 EY00 EY10 EY21 EY29 FX12 FX17 FX24 FX35 GX00 GX01 GX06

Claims (1)

  1. 【特許請求の範囲】 【請求項1】 第1の電源線と第2の電源線との間に直列に接続された駆動トランジスタと電流制御素子と、前記駆動トランジスタと電流制御素子の接続点と前記駆動トランジスタのゲート電極との間に接続された保持容量と、信号線と前記駆動トランジスタのゲート電極との間に接続された選択ゲートトランジスタとを備え、 前記駆動回路の選択期間に、選択ゲートトランジスタをオンにして前記信号線から第1の信号電圧を入力し、前記保持容量に書き込まれた信号電荷を前記駆動トランジスタを経て放電したのち、前記信号線から第2の信号電圧を入力して前記保持容量に保持し、前記駆動回路の非選択期間に、前記選択ゲートトランジスタをオフにして前記駆動トランジスタを経て前記電流制御素子に電流を流す A drive transistor and a current control element connected in series between the Patent Claims 1. A first power supply line and the second power supply line and a connection point of the drive transistor and the current control element a storage capacitor connected between the gate electrode of the driving transistor, and a connected selection gate transistor between the gate electrode of the driving transistor to the signal line, the selection period of the driving circuit, the select gate to turn on transistor receives the first signal voltage from the signal line, after the written signal charges to the storage capacitor has discharged through the driving transistor, and enter a second signal voltage from the signal line held in the holding capacitor, the non-selection period of the driving circuit, a current flows in the current control device via the driving transistor to turn off the selection gate transistor とを特徴とする電流制御素子の駆動回路。 Driving circuit of the current control element characterized and. 【請求項2】 前記駆動回路の選択期間の初期に、前記信号線にリセット信号電圧を入力することによって、前記保持容量及び前記電流制御素子の寄生容量に蓄積されている電荷をリセットすることを特徴とする請求項1記載の電流制御素子の駆動回路。 The initial wherein selection period of the driving circuit, by inputting a reset signal voltage to the signal line, to reset the charge stored in the parasitic capacitance of the storage capacitor and the current control element driving circuit of the current control device according to claim 1, wherein. 【請求項3】 前記駆動回路の選択期間の初期に、前記駆動トランジスタをオンにし、前記第1の電源線をリセット信号電圧とすることによって、前記保持容量及び前記電流制御素子の寄生容量に蓄積されている電荷をリセットすることを特徴とする請求項1記載の電流制御素子の駆動回路。 The initial wherein selection period of the driving circuit, the driving transistor is turned on by the reset signal voltage to the first power supply line, accumulated in the parasitic capacitance of the storage capacitor and the current control element driving circuit of the current control device according to claim 1, wherein resetting the charge that is. 【請求項4】 前記選択ゲートトランジスタと駆動トランジスタとが、Nチャネル電界効果トランジスタからなることを特徴とする請求項1乃至3のいずれか一に記載の電流制御素子の駆動回路。 Wherein said selection gate transistor and the driving transistor, the driving circuit of the current control device according to any one of claims 1 to 3, characterized in that it consists of N-channel field effect transistor. 【請求項5】 前記選択ゲートトランジスタと駆動トランジスタとが、Pチャネル電界効果トランジスタからなることを特徴とする請求項1乃至3のいずれか一に記載の電流制御素子の駆動回路。 Wherein said selection gate transistor and the driving transistor, the driving circuit of the current control device according to any one of claims 1 to 3, characterized in that it consists of P-channel field effect transistor. 【請求項6】 前記駆動トランジスタのゲート電極とソース電極との間にスイッチングトランジスタを備え、前記駆動回路の非選択期間又は選択期間の初期に、前記スイッチングトランジスタをオンにすることによって、前記保持容量及び前記電流制御素子の寄生容量に蓄積されている電荷をリセットすることを特徴とする請求項1記載の電流制御素子の駆動回路。 Further comprising: a switching transistor between the gate electrode and the source electrode of the driving transistor, the beginning of the non-selection period or selection period of the driving circuit, by turning on the switching transistor, the storage capacitor and a driving circuit of the current control device according to claim 1, wherein resetting the charge stored in the parasitic capacitance of the current control element. 【請求項7】 前記駆動トランジスタのゲート電極と前記他方の電源線との間にスイッチングトランジスタを備え、前記駆動回路の非選択期間又は選択期間の初期に、 7. a switching transistor between the other power supply line and the gate electrode of the driving transistor, the beginning of the non-selection period or selection period of the drive circuit,
    前記スイッチングトランジスタをオンにすることによって、前記保持容量及び前記電流制御素子の寄生容量に蓄積されている電荷をリセットすることを特徴とする請求項1記載の電流制御素子の駆動回路。 Wherein by turning on the switching transistor, the storage capacitor and the driving circuit of the current control device according to claim 1, wherein the resetting the electric charges accumulated in the parasitic capacitance of the current control element. 【請求項8】 前記選択ゲートトランジスタと駆動トランジスタとスイッチングトランジスタとが、Nチャネル電界効果トランジスタからなることを特徴とする請求項6又は7に記載の電流制御素子の駆動回路。 Wherein said selection gate transistor and the driving transistor and the switching transistor, a driving circuit of the current control device according to claim 6 or 7, characterized in that it consists of N-channel field effect transistor. 【請求項9】 前記選択ゲートトランジスタと駆動トランジスタとスイッチングトランジスタとが、Pチャネル電界効果トランジスタからなることを特徴とする請求項6又は7に記載の電流制御素子の駆動回路。 Wherein said selection gate transistor and the driving transistor and the switching transistor, a driving circuit of the current control device according to claim 6 or 7, characterized in that it consists of P-channel field effect transistor. 【請求項10】 請求項1乃至9のいずれか一記載の電流制御素子の駆動回路を複数個平面状に配列して、行方向と列方向とに駆動可能なように構成してなることを特徴とする画像表示装置。 10. arranging a drive circuit of the current control element according to any one of claims 1 to 9 into a plurality planar, to become configured so as to be driven in a row direction and a column direction an image display device comprising.
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