JP2013176143A - Semiconductor device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electric circuit in which influence of fluctuation in characteristics of transistors is suppressed.SOLUTION: A source follower circuit comprises an amplification transistor 111, a bias transistor 112, capacitive elements 113 and 114, analog switches 115-118, 120, 127 and 128, and a reference constant-current source 126. In the source follower circuit, the output potential is equal to the input potential, regardless of characteristics of the transistors.

Description

The present invention relates to electric circuit technology. The present invention also belongs to the technical field of a semiconductor device having a source follower circuit, a differential amplifier circuit, a sense amplifier, an electric circuit typified by an operational amplifier, a signal line driver circuit, and a photoelectric conversion element.

In recent years, integrated circuits (ICs) widely used in mobile phones and mobile terminals are
Forming hundreds of thousands to millions of transistors and resistors on a 5 mm square silicon substrate plays an important role in downsizing and high reliability of devices and mass production of devices.

When designing an electric circuit used for an integrated circuit (IC) or the like, in many cases, an amplifier circuit having a function of amplifying a voltage or current of a signal having a small amplitude is designed. An amplifier circuit is widely used because it is an indispensable circuit for eliminating the occurrence of distortion and allowing an electric circuit to work stably.

Here, the configuration and operation of a source follower circuit will be described as an example of an amplifier circuit. First, FIG. 5A shows a configuration example of the source follower circuit, and the operation in a steady state will be described. Next, the operating point of the source follower circuit will be described with reference to FIGS. Finally, FIG. 6 shows an example of a source follower circuit having a configuration different from that in FIG. 5A, and the operation in a transient state will be described.

First, operation in a steady state will be described with reference to FIG. 5A using a source follower circuit.

In FIG. 5A, 11 is an n-channel amplification transistor, and 12 is an n-channel bias transistor. Note that the amplifying transistor 11 and the biasing transistor 12 illustrated in FIG. 5A are n-channel transistors, but may be configured using p-channel transistors. Here, for simplicity, it is assumed that the amplifying transistor 11 and the biasing transistor 12 have the same characteristics and size, and that the current characteristics are ideal. That is, it is assumed that the current value in the saturation region does not change even when the source-drain voltage of the amplifying transistor 11 and the biasing transistor 12 changes.

The drain region of the amplifying transistor 11 is connected to the power supply line 13, and the source region is connected to the drain region of the biasing transistor 12. A source region of the bias transistor 12 is connected to the power supply line 14.

A bias potential V _b is applied to the gate electrode of the bias transistor 12. A power supply potential (high potential power supply) V _dd is applied to the power supply line 13, and a ground potential (low potential power supply) V _ss (= 0 V) is applied to the power supply line 14.

In the source follower circuit shown in FIG. 5 (A), the gate electrode of the amplifying transistor 11 has as an input terminal, to the gate electrode of the amplifying transistor 11, the input potential V _in is inputted. The source region of the amplifying transistor 11 is an output terminal, and the potential of the source region of the amplifying transistor 11 is the output potential V _out.
It becomes. When the bias potential V _b is applied to the gate electrode of the bias transistor 12 and the bias transistor 12 operates in the saturation region, Ib
Suppose that the current indicated by. At this time, since the amplifying transistor 11 and the biasing transistor 12 are connected in series, the same amount of current flows through both transistors. That is, when the current Ib flows through the biasing transistor 12, the current Ib also flows through the amplifying transistor 11.

Here, the output potential _Vout in the source follower circuit is obtained. Output potential V _o
ut is the gate-source voltage of the amplifying transistor 11 than the input voltage V _in V _gs1
The value will be lower by. At this time, the relationship between the input potential V _in , the output potential V _out and the gate-source voltage V _gs1 satisfies the following expression (1).

V _out = V _in -V _gs1 (1)

When the amplifying transistor 11 is operating in the saturation region, in order for the current Ib to flow through the amplifying transistor 11,
It is necessary that the source voltage V _gs1 is _equal to the bias potential V _b (the gate-source voltage of the biasing transistor 12). Then, the following equation (2) is established. However, Expression (2) is established only when the amplifying transistor 11 and the biasing transistor 12 operate in the saturation region.

V _out = V _in -V _b (2)

Next, the operating point of the source follower circuit will be described with reference to FIGS. 5B and 5C showing the relationship between the voltage and current of the amplifying transistor 11 and the biasing transistor 12. More specifically, the gate-source voltage V _gs1 of the amplifying transistor 11, the gate-source voltage V _gs2 of the bias transistor 11 for the case of the same value, will be described with reference to FIG. 5 (B). Next, the amplifying transistor 11
The gate-source voltage V _gs1 of, for the case in the case of the gate-source voltage V _gs2 and different values of the bias transistor 11, for example, the bias transistor 12 is operating in the linear region, FIG. 5 A description will be given using (C).

In FIG. 5B, the dotted line 21 shows the relationship between the voltage and current when the gate-source voltage V _gs1 of the amplifying transistor 11 is V _b , and the solid line 22 shows the gate-source voltage of the biasing transistor 12. The relationship between voltage and current when V _gs2 is V _b is shown. In FIG. 5C, a dotted line 21 indicates the gate of the amplifying transistor 11
The relationship between voltage and current when the source-to-source voltage V _gs1 is V _b `is shown, and the solid line 22 shows the relationship between voltage and current when the gate-source voltage V _gs2 of the biasing transistor 12 is V _b. .

In FIG. 5 (B), the gate-source voltage V _gs1 of the amplifying transistor 11, the same value is the gate-source voltage V _gs2 of the bias transistor 11, further a bias potential V _b, bias transistor 11 Gate-source voltage V _{g
Since s2} has the same value, the gate-source voltage _Vgs1 of the amplifying transistor 11 is the same value as the bias potential _Vb . That is, V _gs1 = V _gs2 = V _b , and FIG.
As shown, the amplifying transistor 11 and the biasing transistor 12 operate in the saturation region. In this case, the relationship between the input potential V _in and the output potential V _out becomes linear.

On the other hand, in FIG. 5C, the gate-source voltage of the amplifying transistor 11
V _gs1 is a value different from the gate-source voltage V _gs2 of the bias transistor 11. The gate-source voltage V _gs2 of the bias transistor 11 is the same value as the bias potential V _b . Further, it is assumed that the gate-source voltage V _gs1 of the amplifying transistor 11 is the bias potential V _b ′. That is, V _gs2 = V _b and V _gs1 = V _b `, and as shown in FIG. 5C, the amplifying transistor 11 operates in the saturation region, and the bias transistor 22 operates in the linear region. Yes. At this time, the relationship between the input potential V _in , the output potential V _out and the bias potential V _b ′ satisfies the following expression (3).

V _out = V _in -V _b '(3)

If the current flowing when the biasing transistor 12 operates in the linear region is Ib ′, then Ib ′ <Ib. In other words, 'it becomes <V _b, the input potential V _in and the current Ib' V _b both values of the smaller. As a result, the bias potential V _b ′ also decreases. The relationship between the input potential V _in and the output potential V _out this time is non-linear.

In summary, in the source follower circuit in the steady state, the output potential
In order to increase the amplitude of _Vout , it is preferable to decrease the bias potential _Vb . This is due to the following two reasons.

The first reason is that the output potential _Vout can be increased when the bias potential _Vb is small as shown in the equation (2). The second reason is the bias potential V _b
Of if the value is large, reducing the input potential V _in, because the bias transistor 12 becomes easier to operate in the linear region. The bias transistor 12 operates in the linear region, the relationship between the input potential V _in and the output potential V _out is likely to be nonlinear.

Since the bias transistor 12 needs to be in a conductive state,
The value of the bias potential _Vb needs to be larger than the threshold voltage of the biasing transistor 12.

Up to now, the operation of the source follower circuit in the steady state has been described. Subsequently, the operation of the source follower circuit in the transient state will be described with reference to FIG.

The source follower circuit shown in FIG. 6 has a structure designed by adding a capacitor 15 to the circuit of FIG. One terminal of the capacitive element 15 is the amplifying transistor 11.
The other terminal is connected to the power supply line 16. Power line 1
6, the ground potential V _ss is applied.

The potential difference between both electrodes of the capacitive element 15 is the same as the output potential _Vout of the source follower circuit. Here, the operation when V _out <V _in −V _b is described with reference to FIG. 6A, and then the operation when V _out > V _in −V _b is described with reference to FIG. 6B. To do.

First, the operation in the transient state of the source follower circuit in the case of V _out <V _in −V _b will be described with reference to FIG.

In FIG. _6A , when t = 0, the gate-source voltage V _gs1 of the amplifying transistor 11 is equal to the gate-source voltage V _g of the biasing transistor 12.
Greater than the value of _s2 . For this reason, a large current flows through the amplifying transistor 11, and the charge is rapidly held in the capacitive element 15. As a result, the output potential V _out increases, and the value of the gate-source voltage V _gs1 of the amplifying transistor 11 decreases.

As time passes (t = t ₁ , t ₁ > 0), the gate of the amplifying transistor 11
When the source voltage V _gs1 becomes equal to the bias potential V _b , the steady state is obtained. At this time,
Output voltage V _out, the relationship between the input voltage V _in and the bias potential V _b satisfies the above equation (2).

In summary, when V _out <V _in −V _b , the value of the gate-source voltage V _gs1 of the amplifying transistor 11 is larger than the bias potential V _b , so that the amplifying transistor 11 has a large value. A current flows, and the charge is rapidly held in the capacitor 15. Therefore, the time for the capacitor 15 to hold a predetermined charge, in other words, the time required to write a signal to the capacitor 15 can be shortened.

Next, the operation in the transient state of the source follower circuit when V _out > V _in −V _b is described with reference to FIG.

In FIG. 6B, when t = 0, the gate-source voltage V _gs1 of the amplifying transistor 11 is smaller than the threshold voltage of the amplifying transistor 11. Therefore, the amplifying transistor 11 is in a non-conductive state. Then, the electric charge accumulated in the capacitive element 15 passes through the biasing transistor 12 to the ground potential V _s.
It flows in the direction of _s and is eventually discharged. At this time, since the gate-source voltage V _gs2 of the biasing transistor 12 is the same value as the bias potential V _b ,
The current flowing through the biasing transistor 12 is Ib.

As time passes (t = t ₁ , t ₁ > 0), the output potential V _out decreases and the gate-source voltage V _{gs1 of} the amplifying transistor 11 increases. When the gate-source voltage V _{gs1 of the} amplifying transistor 11 becomes equal to the bias potential V _b , the steady state is obtained. At this time, the output potential V _out, the relationship between the input voltage V _in and the bias potential V _b satisfies the above equation (2). Note that, in a steady state, the output potential V _out maintains a constant value, and no charge flows through the capacitor element 15. Then, the amplifying transistor 11
The current Ib flows through the biasing transistor 12.

In summary, when V _out > V _in −V _b , the time for which the capacitive element 15 holds a predetermined charge, in other words, the signal writing time for the capacitive element 15 is the current flowing through the biasing transistor 12. Depends on Ib. Then, the current Ib is dependent on the magnitude of the bias voltage V _b. Therefore, by increasing the current Ib, in order to shorten the signal writing time for the capacitance element 15 is required to have caused increasing the bias voltage V _b.

As a method for correcting the variation in the threshold voltage of the transistor, there is a method in which the variation is observed based on the output of the circuit to which the signal is input, and then the variation is fed back and corrected (for example, non-patent literature). (See 1)
.

H. Sekine et al, “Amplifier Compensation Method for a Poly-Si TFT LCLV with an Integrated Data-Driver”, IDRC '97, p. 45-48

The operation of the source follower circuit described above is performed on the assumption that the characteristics of the amplifying transistor 11 and the biasing transistor 12 are the same. However, both transistors have overlapping factors such as variations in gate length (L), gate width (W), and gate insulating film thickness due to differences in manufacturing processes and substrates used, and variations in the crystal state of the channel formation region. As a result, the threshold voltage and mobility vary.

For example, in FIG. 5A, it is assumed that the threshold voltage of the amplifying transistor 11 is 3V and the threshold voltage of the biasing transistor 12 is 4V, resulting in a variation of 1V. Then, in order to pass the current Ib, it is necessary to apply a voltage 1V lower than the gate-source voltage V _gs2 of the biasing transistor 12 to the gate-source voltage V _gs1 of the amplifying transistor 11. That is, V _gs1 = V
_b -1. Then, V _out = V _in −V _gs1 = V _in −V _b +1. That is, if the threshold voltage of the amplifying transistor 11 and the bias transistor 12 is varied even at 1V, the output potential _Vout also varies.

The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an electric circuit in which the influence of variation in transistor characteristics is suppressed. For more details,
An object of the present invention is to provide an electric circuit capable of supplying a desired voltage while suppressing the influence of variation in transistor characteristics in an electric circuit having a function of amplifying current.

In order to solve the above-described problems, the present invention uses an electric circuit having the following configuration.

The electric circuit shown in FIG. 3A includes a reference constant current source 21, a switching element 22 having a switching function (hereinafter referred to as sw22), an n-channel transistor 23, and a capacitor 24. The source region of the transistor 23 is connected to the power supply line 25, and the drain region is connected to the reference constant current source 21. The gate electrode of the transistor 23 is connected to one terminal of the capacitor 24. The other terminal of the capacitive element 24 is connected to the power supply line 25.
The capacitive element 24 plays a role of holding the gate-source voltage V _gs of the transistor 23. Further, the ground potential V _ss is applied to the power line 25.

In FIGS. 3A to 3C, the transistor 23 is an n-channel transistor; however, the transistor 23 is not limited to this and may be a p-channel transistor.

In the electric circuit shown in FIG. 3A, both capacitance elements are connected so that the current flowing between the source and drain of the transistor is equal to the signal current I _data (also referred to as reference current) flowing from the reference constant current source. A potential difference between the electrodes, that is, a gate-source voltage of the transistor is set. This operation will be described below.

In FIG. 3A, sw22 is on. At this time, the signal current I _data set in the reference constant current source 21 flows toward the power supply line 25. At this time, the current I _data flows separately into I ₁ and I ₂ . The current I _data is I
_data = I ₁ + I ₂ is satisfied.

At the moment when current starts to flow from the reference constant current source 21, no charge is held in the capacitive element 24. Therefore, the transistor 23 is off. Therefore, I ₂ = 0 and I _data = I ₁ .

Then, charges are gradually accumulated in the capacitive element 24, and a potential difference starts to occur between both electrodes of the capacitive element 24. When the potential difference between the two electrodes reaches the threshold voltage of the transistor 23, the transistor 23 is turned on and I ₂ > 0. As mentioned above, I _data = I ₁ + I ₂
Therefore, I ₁ gradually decreases, but current still flows (FIGS. 3C and 3D).
, A point).

The potential difference between both electrodes of the capacitor 24 is a gate-source voltage of the transistor 23. Therefore, the charge accumulation in the capacitor 24 is continued until the transistor 23 has a voltage (VGS) sufficient to allow a signal current that is a desired current to flow. When charge accumulation is completed (points B and C in FIGS. 3C and 3D), the current I ₂ stops flowing, and the transistor 23 is on, so that I _data = I ₁ .

Subsequently, as shown in FIG. 3B, sw22 is turned off. Since VGS written in the above-described operation is held in the capacitor 24, the transistor 23 is on, and further, a signal current is present in the drain region of the transistor 23.
A current equal to I _data flows. At this time, if the transistor 23 is operated in the saturation region, the drain current value of the transistor 23 can flow without change even if the source-drain voltage of the transistor 23 changes.

As described above, in order to flow the same current as the signal current set in the reference constant current source through a specific transistor, the gate-source voltage of the transistor may be set. In the present invention, the capacitor connected to the transistor can be set by holding the gate-source voltage of the transistor. Then, by using the voltage held in the capacitor, the influence of variation in transistor characteristics can be suppressed.

In addition, as a method of using the voltage held in the capacitor, the following method can be used. The voltage held in the capacitor is held as it is, and a signal voltage (such as a video signal voltage) is input to one terminal of the capacitor. Then, in addition to the signal voltage, a voltage obtained by adding a voltage held in the capacitor is input to the gate electrode of the transistor. As a result, a value obtained by adding the voltage held in the capacitor and the signal voltage is input to the gate electrode of the transistor. In other words, in the present invention, even when characteristic variation occurs between transistors, a value obtained by always adding a voltage and a signal voltage held in each capacitive element to which each transistor is connected in a transistor to which a signal voltage is input. Will be entered.
Therefore, it is possible to provide an electric circuit in which the influence of characteristic variation between transistors is suppressed.

Note that the mechanism by which the voltage held in the capacitor is added to the signal voltage is explained by the law of conservation of charge. The charge conservation law indicates the fact that the total electric quantity of the algebraic sum of the positive electric quantity and the negative electric quantity is constant.

In the present invention, a transistor using any material, a transistor obtained by any means, and a manufacturing method may be used, and any type of transistor may be used. For example, a thin film transistor (TFT) may be used. TF
As T, the semiconductor layer is amorphous (amorphous), polycrystalline (polycrystal),
Any single crystal may be used. As another transistor, a transistor made of a single crystal substrate or a transistor made of an SOI substrate may be used. Further, a transistor formed of an organic material or a carbon nanotube may be used. Further, it may be a MOS transistor or a bipolar transistor.

In order to flow the same current as the signal current set in the constant current source for reference through a specific transistor, the gate-source voltage of the transistor may be set. In the present invention, the capacitor connected to the transistor can be set by holding the gate-source voltage of the transistor. Then, by using the voltage held in the capacitor element, it is possible to suppress the influence of transistor variation.

In addition, as a method of using the voltage held in the capacitor, the following method can be used. The voltage held in the capacitor is held as it is, and a signal voltage (such as a video signal voltage) is input to one terminal of the capacitor. Then, in addition to the signal voltage, a voltage obtained by adding a voltage held in the capacitor is input to the gate electrode of the transistor. As a result, a value obtained by adding the voltage held in the capacitor and the signal voltage is input to the gate electrode of the transistor. In other words, in the present invention, even when characteristic variation occurs between transistors, a value obtained by always adding a voltage and a signal voltage held in each capacitive element to which each transistor is connected in a transistor to which a signal voltage is input. Will be entered.
Therefore, it is possible to provide an electric circuit in which the influence of characteristic variation between transistors is suppressed.

The figure explaining operation | movement of the source follower circuit of this invention. The figure explaining operation | movement of the source follower circuit of this invention. The figure explaining the structure of the electric circuit of this invention, and its operation | movement. The figure of the electric equipment with which this invention is applied. The figure explaining operation | movement of a source follower circuit. The figure explaining operation | movement of a source follower circuit. The figure which shows the source follower circuit of this invention. The figure which shows the source follower circuit of this invention. The figure which shows the source follower circuit of this invention. The figure which shows the differential amplifier circuit of this invention. The figure which shows the differential amplifier circuit of this invention. The figure which shows the operational amplifier of this invention. The figure which shows the operational amplifier of this invention. FIG. 11 illustrates a semiconductor device of the present invention. 4A and 4B each illustrate a pixel and a bias circuit in a semiconductor device of the present invention. The figure explaining the structure of the electric circuit of this invention. 1 is a diagram of a signal line driver circuit of the present invention. 1 is a diagram of a signal line driver circuit of the present invention. FIG. 6 illustrates operation of a signal line driver circuit of the present invention. The figure which shows the constant current source for a reference. The figure which shows the constant current source for a reference. The figure which shows the constant current source for a reference. The figure which shows the constant current source for a reference. The figure which shows the source follower circuit of this invention. The figure which shows the source follower circuit of this invention. The figure which shows the source follower circuit of this invention. The figure which shows the source follower circuit of this invention. The figure which shows the source follower circuit of this invention. The figure which shows the source follower circuit of this invention. The figure which shows the differential amplifier circuit of this invention. The figure which shows the differential amplifier circuit of this invention. The figure which shows the differential amplifier circuit of this invention. The figure which shows the differential amplifier circuit of this invention. The figure which shows the differential amplifier circuit of this invention. The figure which shows the differential amplifier circuit of this invention. The figure which shows the differential amplifier circuit of this invention. The figure which shows the differential amplifier circuit of this invention. The figure which shows the operational amplifier of this invention. The figure which shows the operational amplifier of this invention. 1 is a diagram of a signal line driver circuit of the present invention. 1 is a diagram of a signal line driver circuit of the present invention. FIG. 6 illustrates operation of a signal line driver circuit of the present invention.

(Embodiment 1)
In this embodiment mode, a source follower circuit is shown as an example of the electric circuit of the present invention, and the configuration and operation thereof will be described with reference to FIGS.

  First, the configuration of the source follower circuit of the present invention will be described with reference to FIGS.

1 and 2, reference numeral 111 denotes an n-channel amplification transistor.
Reference numeral 2 denotes an n-channel type bias transistor. Reference numerals 113 and 114 denote capacitive elements. In addition, reference numerals 115 to 118, 120, 127, and 128 denote elements having a switching function, and a semiconductor element such as an analog switch preferably including a transistor is used. At this time, since the semiconductor element is a simple switch, its polarity is not particularly limited.

Reference numeral 126 denotes a reference constant current source, which has a capability of flowing a constant current. The reference constant current source 126 is formed of a semiconductor element such as a transistor. In this specification, an example of the reference constant current source 126 formed using a transistor is described in Embodiment Mode 6 and may be referred to.

_{Reference numerals} 123 to _{125 denote} power supply lines. A power supply potential V _dd1 is applied to the power supply line 123.
A ground potential V _ss is applied to the power line 124. The power supply line 125 has a power supply potential V
_dd2 is applied. The power supply potential V _dd1 applied to the power supply line 123 and the power supply line 1
The power supply potential V _dd2 applied to 25 may be the same value or different values. However,
The power supply potential V _dd2 applied to the power supply line 125 needs to be set to a value that allows the reference constant current source 126 to operate normally as a constant current source. For example, when the reference constant current source 126 configures the current source using the saturation region of the transistor, it is necessary to set the value within a range in which the transistor can operate in the saturation region.

Note that although the case where the amplifying transistor 111 and the biasing transistor 112 are n-channel type is described in this embodiment mode, the present invention is not limited to this, and both transistors may be p-channel type. Moreover, the polarity of both transistors may differ and the push pull circuit may be comprised. However, when a push-pull circuit is configured, as shown in FIG. 24, both transistors function as amplification transistors. Therefore, a signal is input to both transistors.

The drain region of the amplifying transistor 111 is connected to the power line 1 via the switch 127.
The source region is connected to the switch 117, the switch 118, and the drain region of the transistor 112. A gate electrode of the amplifying transistor 111 is connected to one terminal of the capacitor 113. The other terminal of the capacitor 113 is connected to the source region of the transistor 111 through the switch 117. The capacitive element 113 plays a role of holding a gate-source voltage of the amplifying transistor 111 and the like. Hereinafter, the amplifying transistor 111 is referred to as a transistor 111.

The source region of the bias transistor 112 is connected to the power supply line 124, and the drain region is connected to the switch 117, the switch 118, and the switch 120. A gate electrode of the bias transistor 112 is connected to one terminal of the capacitor 114. The other terminal of the capacitor 114 is connected to the biasing transistor 1
12 source regions are connected. The capacitive element 114 serves to hold the gate-source voltage of the biasing transistor 112. Hereinafter, the biasing transistor 112 is referred to as a transistor 112.

The switches 115 to 118, 120, 127, and 128 are controlled to be turned on or off (on or off) according to an input signal. However, in FIGS. 1 and 2, the switches 115 to 118, 120, 127, 12 are shown for ease of explanation.
Illustration of a signal line for inputting a signal to 8 is omitted.

In the source follower circuit shown in FIGS. 1 and 2, one terminal of the switch 116 is an input terminal. An input potential V _in (signal voltage) is input to one terminal of the capacitor 113 through the input terminal. Further, one terminal of the switch 118 is an output terminal, and the potential of the source region of the transistor 111 is the output potential _Vout .

  Next, the operation of the source follower circuit shown in FIGS.

In FIG. 1, the switch 115, the switch 117, the switch 120, and the switch 128 are turned on. And switches other than the above are turned off. In this state, the signal current I _data set in the reference constant current source 126 flows in the direction of the power supply line 124 via the capacitive element 113 and the capacitive element 114.

At the moment when current starts to flow from the reference constant current source 126, the capacitive element 11
3 and the capacitor element 114 are not charged. Therefore, transistor 1
11 and transistor 112 are off. The current is a constant current source for reference 1
26, through the switch 128, the switch 115, and the switch 117, then through the switch 119, and further through the switch 120, in the direction of the power supply line 124.

Then, charges are gradually accumulated in the capacitor 113 and the capacitor 114, and a potential difference starts to occur between the electrodes of the capacitor 113 and the capacitor 114. Capacitance element 11
The transistor 111 is turned on when the potential difference between the two electrodes 3 becomes the threshold voltage V _th1 of the transistor 111. Similarly, when the potential difference between both electrodes of the capacitor 114 becomes the threshold voltage V _th2 of the transistor 112, the transistor 112 is turned on.

Next, the voltage between the gate and the source of the transistor 111 is a predetermined signal current I _data
The charge is continuously accumulated in the capacitor 113 so that the voltage can flow. The voltage between the gate and source of the transistor 112 is a predetermined signal current.
The charge is continuously accumulated in the capacitor 114 so that the voltage at which I _data can flow is obtained.

Then, as illustrated in FIG. 2A, when charge accumulation in the capacitor 113 and the capacitor 114 is finished and the steady state is reached, the switch 115, the switch 117, and the switch 120 are turned off from the other, The switch maintains the state of FIG. At this time, the signal current I _d set by the constant current source 126 for reference
_ata flows from the drain region of the transistor 111 through the source region and from the drain region of the transistor 112 through the source region. Incidentally, the potential difference between both electrodes of the capacitor 113 at this time is with V _a, the potential difference between both electrodes of the capacitor 114 and V _c.

Subsequently, as shown in FIG. 2B, the switch 116, the switch 118, and the switch 127 are turned on. Then, all the switches other than the above are turned off. This time through the switch 116 from the input terminal, the input potential V _in is input to one terminal of the capacitor 113. Then, by the charge conservation law, the gate electrode of the transistor 111, in addition to the gate-source voltage V _a of the transistor 111, the input potential V _in is plus value (V _a + V _in) is applied.

The output potential V _out is the potential of the source region of the transistor 111. That is, the gate-source voltage V _g from the gate potential (V _in + V _a ) of the transistor 111
It corresponds to a value obtained by subtracting _s (= V _a ).

Note that the signal current I _data flows through the transistor 111 even after the switch 128 is turned off and the switch 127 is turned on. This is because a voltage necessary for the signal current I _data to flow is added to the gate-source voltage V _gs (= V _c ) of the transistor 112. Therefore, the gate-source voltage of the transistor 111
A voltage necessary for the transistor 111 to flow the signal current I _data is also applied to V _gs . And the its required voltage, a voltage represented by V _a. Therefore, it can be seen that the gate-source voltage V _gs of the transistor 111 has the same value as V _a .
In summary, the following formula (4) is established.

V _out = (V _in + V _a ) −V _a = V _in (4)

As shown in equation (4), the output potential V _out is the same value as the input potential V _in, it does not depend on the characteristics of the transistor. Therefore, even if the characteristics of the transistor 111 and the transistor 112 _vary , the influence on the output potential _Vout can be suppressed.

The electric circuit shown in FIGS. 1 and 2 is a source follower circuit, but does not have an input terminal for inputting a bias potential. This is because a predetermined charge is already held in the capacitor 114 so that the signal current I _data set by the reference constant current source 126 flows in the gate-source voltage of the transistor 112.

According to the present invention, the influence of the characteristic variation of the transistor 111 and the transistor 112 can be suppressed. Therefore, it is not necessary to design the gate length (L) and the gate width (W) of the transistor 111 and the transistor 112 with the same value, and the variation occurs. May be.

In this specification, an operation for holding a predetermined charge in the capacitor is referred to as a setting operation. In this embodiment mode, the operations in FIGS. 1 and 2A correspond to setting operations. Also,
Enter the input potential V _in, referred to as an output operation an operation to retrieve the output potential V _out. In this embodiment, the operation in FIG. 2B corresponds to an output operation.

The electric circuit shown in FIGS. 1 and 2 includes a power line 125 and a reference constant current source 12.
6 and switch 128 are connected in this order, but the present invention is not limited to this. For example, the reference constant current source 126 and the switch 128 are reversed so that the power line 12
5, the switch 128, and the reference constant current source 126 may be connected in this order.

Further, the reference constant current source 126 may be arranged as shown in FIGS. Below, the structure of the electric circuit shown to FIG. 7 (A) (B) is demonstrated. Note that the electric circuit illustrated in FIGS. 7A and 7B has the same circuit elements as those illustrated in FIGS. 1 and 2 except that the power supply line 125 is not provided. A power supply potential V _dd is applied to the power supply line 123, and a ground potential V _ss is applied to the power supply line 124. In addition, FIG.
The operation of the source follower circuit shown in (B) conforms to the operation of the source follower circuit shown in FIGS.

In FIG. 7A, the switch 127 is provided between the drain region of the transistor 112 and the power supply line 124. Then, the switch 128 is disposed between the drain region of the transistor 112 and the power supply line 124 so as to be in parallel with the switch 127. Finally, the reference constant current source 126 is disposed between the drain region of the transistor 112 and the switch 128 or between the switch 128 and the power supply line 124. Note that FIG. 7A illustrates the case where the transistor 112 is disposed between the drain region of the transistor 112 and the switch 128.

In FIG. 7A, both the switch 127 and the switch 128 are connected to the ground potential V _ss . However, the present invention is not limited to this. In Figure 1, the connection switch 127 to the power supply potential V _dd1, the switch 128 is the power supply potential V _d
It may be connected to different power supply lines so as to be connected to _d2 . For example,
The switch 127 may be connected to the ground potential V _{ss as} shown in FIG. 7A, and the switch 128 may be connected to the newly arranged ground potential V _ss2 . Ground potential V _ss and ground potential V
_The same value may be sufficient as _ss2 , and a different value may be sufficient as it.

In FIG. 7B, the switch 127 is connected to the source region of the transistor 111;
It is disposed between the drain region of the transistor 112. And switch 127
The switch 128 is arranged so as to be in parallel with each other. Finally, the reference constant current source 126 is disposed between the source region of the transistor 111 and the switch 128 or between the switch 128 and the drain region of the transistor 112. Note that FIG.
FIG. 5B shows a case where the transistor 111 is disposed between the source region of the transistor 111 and the switch 128.

Note that in FIG. 7B, the switch 118 is connected to the source region of the transistor 111 and to the drain region of the transistor 112 through the switch 127; however, the present invention is not limited to this. The switch 118 may be connected to the drain region of the transistor 112 and may be connected to the source region of the transistor 111 through the switch 127.

However, the switch 118 is preferably connected to the source region of the transistor 111 and connected to the drain region of the transistor 112 via the switch 127. This is because when the switch 118 is connected to the drain region of the transistor 112 and is connected to the source region of the transistor 111 via the switch 127, if the switch 127 has an on-resistance, the output potential V _out This is because the output potential V _out is lowered due to the influence.

8A, in the electric circuit shown in FIGS. 1 and 2, the switch 119 is disposed between the drain region of the transistor 111 and the power supply line 124, and the transistor 112, the capacitor 114, and the switch 120 are disposed. The source follower circuit in the case of not performing is shown. The operation of the source follower circuit shown in FIG.
Since the operation is the same as that of FIGS. 1 and 2 except that 19 is on during the setting operation and off during the output operation, the description thereof is omitted in the present embodiment.

In FIG. 8A, the switch 127, the switch 128, and the current source 12 are the same as in FIG.
6 is connected to the power supply potential _Vdd . However, as shown in FIGS. 7A and 7B, the switch 127, the switch 128, and the current source 126 may be connected to another element such as the ground potential V _ss . As an example, in FIG.
, The switch 128 and the current source 126 are connected to the ground potential V _ss .

Here, FIG. 25A illustrates a source follower circuit when the transistor 112 is not provided. However, the transistor 112 is originally a circuit that operates as a current source for providing a bias in the source follower circuit. Therefore, the current source 126 in FIG.
It may be operated as a current source for applying a bias. That is, the current source 126 is not used during the setting operation and not used during the output operation, but is used as a current source for setting the transistor 111 during the setting operation, and a source follower circuit during the output operation. You may use as a current source which gives the bias in. In that case, since there is no need to switch between the setting operation and the output operation, the switches 127 and 128 are unnecessary. The circuit diagram at this time is shown in FIG.
Shown in (A).
FIG. 27 shows a circuit diagram in the case where the current source 126 in FIG. Next, the operation will be described.

In FIG. 27, the switch 115 and the switch 117 are turned on. And switches other than the above are turned off. In this state, the signal current I _data set in the transistor 112 flows toward the power supply line 124 through the capacitor 113. The magnitude of the signal current I _data is determined by the bias voltage Vb applied to the gate of the transistor 112 and the characteristics of the transistor 112. Accordingly, if there are a plurality of circuits in FIG. 27, the characteristics of the transistor 112 may vary in the plurality of circuits. In that case, each transistor 1
Even if the same voltage Vb is applied to 12 gates, the magnitude of the signal current I _data is
Different in each circuit.

At the moment when current starts to flow from the transistor 112, no charge is held in the capacitor 113. Therefore, the transistor 111 is off. The current is supplied from the transistor 112 through the switch 115 and the switch 117 to the power line 12.
It flows in the direction of 4.
Then, electric charges are gradually accumulated in the capacitor 113, and a potential difference starts to occur between both electrodes of the capacitor 113. The potential difference between both electrodes of the capacitor 113 is the transistor 1
When the threshold voltage _Vth1 becomes 11, the transistor 111 is turned on.
Next, the voltage between the gate and the source of the transistor 111 is a predetermined signal current I _data
The charge is continuously accumulated in the capacitor 113 so that the voltage can flow.

As shown in FIG. 28A, when charge accumulation in the capacitor 113 is finished and the steady state is reached, the switches 115 and 117 are turned off from the on state, and the other switches are in the state shown in FIG. maintain. At this time, transistor 1
The signal current I _data flowing from the 12, flows through the source region from the drain region of the transistor 111. Incidentally, the potential difference between both electrodes of the capacitor 113 at this time is V _a.

If there are a plurality of circuits in FIG. 27, the characteristics of the transistor 111 and the transistor 112 may vary in the plurality of circuits. In that case, the magnitude of the signal current I _data differs in each circuit. Similarly, the potential difference V _a between both electrodes of the capacitor 113 is also different in each circuit.

Subsequently, as shown in FIG. 28B, the switch 116 and the switch 118 are turned on. Then, all the switches other than the above are turned off. This time through the switch 116 from the input terminal, the input potential V _in is input to one terminal of the capacitor 113. Then, by the charge conservation law, the gate electrode of the transistor 111, in addition to the gate-source voltage V _a of the transistor 111, the input potential V _in is plus value (V _a + V _in) is applied.

The output potential V _out is the potential of the source region of the transistor 111. That is, the output potential V _out corresponds to a value obtained by subtracting the gate-source voltage V _gs (= V _a ) from the gate potential (V _in + V _a ) of the transistor 111.

The signal current I _data continues to flow through the transistor 111. This is because the gate voltage Vb of the transistor 112 remains the same value. Thus, transistor 1
A voltage necessary for the transistor 111 to flow the signal current I _data is also applied to the gate-source voltage V _gs 11. And the its required voltage, a voltage represented by V _a. Therefore, it can be seen that the gate-source voltage V _gs of the transistor 111 has the same value as V _a . Summarizing the above, formula (4) is also established here.

As shown in equation (4), the output potential V _out is the same value as the input potential V _in, it does not depend on the characteristics of the transistor. Therefore, even when the transistor 111 and the transistor 112 have characteristic variations, the influence of the characteristic variations on the output potential _Vout can be suppressed.

If there are a plurality of circuits in FIG. 27, the characteristics of the transistor 112 and the transistor 111 may vary in the plurality of circuits. In that case, the magnitude of the signal current I _data, the potential difference V _a between both electrodes of the capacitor 113 is different each circuit. However, as shown in Equation (4), the output potential V _out is the same value as the input potential V _in, the potential difference V _a between the electrodes of the signal current I _data size and capacitor 113,
Do not depend. That is, when there are a plurality of circuits in FIG.
Even if the characteristics of the transistor 112 and the transistor 111 vary, the influence is mitigated.

According to the present invention, the influence of the characteristic variation of the transistor 111 and the transistor 112 can be suppressed. Therefore, it is not necessary to design the gate length (L) and the gate width (W) of the transistor 111 and the transistor 112 with the same value, and the variation occurs. May be.

Next, a case where a current is supplied from outside the source follower circuit as shown in FIG. 1 is compared with a case where a setting operation is performed using a bias current source of the source follower circuit as shown in FIG. .

First, considering the circuit configuration, FIG. 26 is simpler and more advantageous. In particular,
It is more advantageous when a plurality of source follower circuits are arranged. However,
In FIG. 26, when there are a plurality of source follower circuits, the current value flowing through each of the source follower circuits may be different due to variations in the characteristics of the current source. As a result, when the steady state is reached, the input voltage and the output voltage are equal in all the source follower circuits, but the transient characteristics may be different for each source follower circuit.

On the other hand, in the case of FIG. 1, since it is necessary to supply current from outside the source follower circuit, the circuit configuration becomes complicated. Especially when arranging multiple source follower circuits,
The circuit configuration becomes more complicated. If only one current source 126 in FIG. 1 is arranged and a plurality of source follower circuits are arranged, the setting operation cannot be performed simultaneously in all the source follower circuits. Therefore, the operation timing is complicated. Alternatively, when the number of current sources 126 in FIG. 1 is the same as the number of source follower circuits, it is desirable that each current source 126 does not vary.

However, when there are a plurality of source follower circuits, even if the characteristics of the source follower circuit vary, the value of the current flowing through the source follower circuit does not vary. This is because the current value is determined by the current source 126 outside the source follower circuit. Therefore, not only the steady state but also the transient characteristics do not vary for each source follower circuit.

Thus, in the present invention, even if occurred characteristic variation between transistors, the transistor a signal voltage of an input potential V _in is input, the value is always plus the gate-source voltage and the signal voltage of the transistor Will be entered. Therefore, it is possible to provide an electric circuit in which the influence of characteristic variation between transistors is suppressed.

(Embodiment 2)
The source follower circuit shown in FIGS. 1 and 2 shows a case where the n-channel type amplifying transistor 111 and the n-channel type biasing transistor 112 are configured. Next, in this embodiment mode, a p-channel amplification transistor 132 is used.
FIG. 9 shows a source follower circuit including a p-channel bias transistor 131, and the configuration thereof will be described. Note that the operation of the source follower circuit shown in FIG. 9 is the same as the operation of the source follower circuit shown in FIGS. 1 and 2 described in Embodiment 1, and thus description thereof is omitted in this embodiment.

In FIG. 9, reference numeral 131 denotes a p-channel bias transistor.
Reference numeral 2 denotes a p-channel type amplifying transistor. Reference numerals 133 and 134 denote capacitive elements. Reference numerals 135 to 142 denote elements having a switching function, and a semiconductor element such as an analog switch preferably composed of a transistor is used.

Reference numeral 146 denotes a reference constant current source, which has a capability of flowing a constant current. The reference constant current source 146 is formed of a semiconductor element such as a transistor. In this specification, an example of the reference constant current source 146 formed using a transistor is described in Embodiment 6 and may be referred to.

Reference numerals 143 to 145 denote power supply lines, and a power supply potential V _dd1 is applied to the power supply line 143.
A ground potential V _ss is applied to the power supply line 144. The power supply line 145 has a power supply potential V
_dd2 is applied. The power supply potential V _dd1 applied to the power supply line 143 and the power supply line 1
The power supply potential V _dd2 applied to 45 may be the same value or different values. However,
The power supply potential V _dd2 applied to the power supply line 145 needs to be set to a value that allows the reference constant current source 146 to operate normally as a constant current source. For example, when the reference constant current source 146 uses the saturation region of the transistor to configure the current source, it must be set to a value within a range in which the transistor can operate in the saturation region.

Note that although the amplifying transistor 132 and the biasing transistor 131 are p-channel transistors in this embodiment mode, the push-pull circuit may be configured with the two transistors having different polarities.

The source region of the bias transistor 131 is connected to the power supply line 143 through the switch 136, and the drain region is connected to the switches 135, 138, and 142. A gate electrode of the bias transistor 131 is connected to one terminal of the capacitor 133. The other terminal of the capacitor 133 is connected to the power supply line 143 through the switch 136. The capacitor 133 plays a role of holding the gate-source voltage of the biasing transistor 131.

The drain region of the amplifying transistor 132 is connected to the power supply line 144, and the source region is connected to the switches 138 and 142. The gate electrode of the amplifying transistor 132 is connected to one terminal of the capacitor element 134. The other terminal of the capacitor element 134 is connected to the source region of the amplifying transistor 132 via the switch 142. The capacitive element 134 holds the gate-source voltage of the amplifying transistor 132.

The switches 135 to 142 are controlled to be conductive or nonconductive (ON or OFF) according to an input signal. However, in FIG. 9, illustration of signal lines and the like for inputting signals to the switches 135 to 142 is omitted for the sake of simplicity.

In the source follower circuit illustrated in FIG. 9, one terminal of the switch 141 serves as an input terminal. An input potential V _in (signal voltage) input from the input terminal is input to one terminal of the capacitive element 134. One terminal of the switch 138 is an output terminal, and the potential of the source region of the amplifying transistor 132 is the output potential V _o.
It becomes _ut .

The electric circuit shown in FIGS. 1 and 2 is a source follower circuit, but does not have an input terminal for inputting a bias potential. This is because a predetermined charge is already held in the capacitor 114 so that the signal current I _data set by the reference constant current source 126 flows in the gate-source voltage of the transistor 131.

Further, according to the present invention, the influence of the characteristic variation of the bias transistor 131 and the amplification transistor 132 can be suppressed.
The gate length (L) and the gate width (W) of the amplifying transistor 132 do not need to be designed with the same value, and may vary.

In FIG. 9, the power supply line 145, the reference constant current source 146, and the switch 139 are connected in this order, but the present invention is not limited to this. The reference constant current source 146 and the switch 139 may be reversed, and the power supply line 145, the switch 139, and the reference constant current source 146 may be connected in this order.

Further, the reference constant current source 146 may be disposed between the switch 140 and the power supply line 144 with reference to the first embodiment described above and FIGS. 7A and 7B.
Further, the reference constant current source 146 may be disposed between the switch 138 and the switch 142.

FIG. 8B shows a source follower circuit in the case where the biasing transistor 131, the capacitor 133, the switch 135, and the switch 137 are not provided. The operation of the source follower circuit illustrated in FIG. 8B is similar to the operation illustrated in FIGS. 1 and 2 described in Embodiment 1, and thus description thereof is omitted in this embodiment.

In FIG. 8B, the switch 136, the switch 139, and the current source 14 are the same as in FIG.
6 is connected to the power supply potential _Vdd . However, as shown in FIGS. 7A and 7B, the switch 136, the switch 139, and the current source 146 may be connected to another power line or element such as the ground potential V _ss . As an example, FIG.
A case where the switch 136, the switch 139, and the current source 146 are connected to the ground potential V _ss will be described.

Here, FIG. 8B illustrates a source follower circuit when the transistor 131 is not provided. However, the transistor 131 is originally a circuit that operates as a current source that provides a bias in the source follower circuit. Therefore, the current source 146 in FIG. 8B may be operated as a current source for applying a bias instead of the transistor 131. That is, the current source 146 is used during the setting operation and not used during the output operation, but is used as a current source for setting the transistor 132 during the setting operation, and in the source follower circuit during the output operation. You may use as a current source which gives a bias. In that case, since there is no need to switch between the setting operation and the output operation, the switches 136 and 139 are unnecessary. The circuit diagram at this time is shown in FIG.
Shown in
FIG. 29 shows a circuit diagram in the case where the current source 146 in FIG. The operation of the source follower circuit shown in FIG. 29 is similar to the operation of FIGS. 27 and 28 described in the first embodiment, and thus the description thereof is omitted in this embodiment.

  This embodiment mode can be arbitrarily combined with Embodiment Mode 1.

(Embodiment 3)
In the first and second embodiments, the source follower circuit to which the present invention is applied has been described. However, the present invention can also be applied to various circuits such as an arithmetic circuit typified by a differential amplifier circuit, a sense amplifier, and an operational amplifier. In this embodiment, an arithmetic circuit to which the present invention is applied will be described with reference to FIGS.

First, a differential amplifier circuit to which the present invention is applied will be described with reference to FIG. FIG. 10 corresponds to the case where the reference constant current source 268 is arranged outside the original circuit as shown in FIG. The differential amplifier circuit calculates the difference between the input potential V _in1 and the input potential V _in2 and outputs the output potential V _out .

In the differential amplifier circuit shown in FIG. 10, 272 and 273 are p-channel transistors, and 274, 275 and 286 are n-channel transistors. Reference numerals 276, 277, and 287 denote capacitive elements. Also, the switches 265, 266
Reference numerals 278 to 284 and 288 denote elements having a switching function, and a semiconductor element such as a transistor is preferably used. The polarity of the semiconductor element is not particularly limited.

Reference numeral 268 is a constant current source for reference, and has a capability of flowing a constant current. The reference constant current source 268 is configured by a semiconductor element such as a transistor. In this specification, an example of the reference constant current source 268 including a transistor is described in Embodiment 6 and may be referred to.

Reference numerals 267, 271, and 291 denote power supply lines. A power supply potential V _dd1 is applied to the power supply line 271, and a ground potential V _ss is applied to the power supply line 291. A power supply potential V _dd2 is applied to the power supply line 267. Incidentally, the power source potential V _dd1 applied to the power line 271, the power supply potential V _dd2 applied to the power line 267 may be the same value, or different values. However, the power supply potential V _dd2 applied to the power supply line 267 is the reference constant current source 2
It is necessary to set 68 to a value that can operate normally as a constant current source. For example, when the reference constant current source 268 uses the saturation region of the transistor to configure the current source, it is necessary to set the value within a range in which the transistor can operate in the saturation region.

In the differential amplifier circuit illustrated in FIG. 10, one terminal of the switch 281 is an input terminal, and the input potential V _in1 is input to one terminal of the capacitor 276. One terminal of the switch 284 is also an input terminal, and the input potential _Vin2 is input to one terminal of the capacitor 277. The drain region of the transistor 275 serves as an output terminal, and the potential of the drain region of the transistor 275 is the output potential V _o.
It becomes _ut .

The drain region of the transistor 272 is connected to the power supply line 271, and the source region is connected to the drain region of the transistor 274. The drain region of the transistor 273 is connected to the power supply line 271, and the source region is connected to the drain region of the transistor 275. Transistor 272 gate electrode and transistor 2
73 gate electrodes are connected. Note that a resistor may be provided instead of the transistor 272 and the transistor 273. This is because, in the differential amplifier circuit as shown in FIG. 10, 272 and 273 are portions called active loads, and operate as resistors. Therefore, the portion of the active load in FIG.
As in the case of FIG.

The drain region of the transistor 274 includes a switch 502 and a transistor 272.
The source region is connected to one terminal of the capacitor 276 via the switch 282. A gate electrode of the transistor 274 is connected to the other terminal of the capacitor 276. The capacitor 276 plays a role of holding the gate-source voltage of the transistor 274 when the setting operation is performed.

The drain region of the transistor 275 includes a switch 503 and a transistor 273.
The source region is connected to one terminal of the capacitor 277 via the switch 283. A gate electrode of the transistor 275 is connected to the other terminal of the capacitor 277. The capacitor 277 plays a role of holding the gate-source voltage of the transistor 275 when the setting operation is performed.

The drain region of the transistor 286 is connected to the source region of the transistor 274 and the source region of the transistor 275 through the switch 285, and the source region of the transistor 286 is connected to one terminal of the capacitor 287. A gate electrode of the transistor 286 is connected to the other terminal of the capacitor 287. The capacitor 287 plays a role of holding a gate-source voltage of the transistor 286.

The capacitive elements 276, 277, and 287 include a reference constant current source 2
68 is used to hold a predetermined charge. However, it is not possible to hold predetermined charges for the three capacitive elements 276, 277, and 287 at a time. Therefore, the control is performed so that one of the switch 265 and the switch 266 is turned on. For example, when the switch 265 is turned on, the switch 266 is turned off. Then, predetermined charges are held in the capacitor elements 277 and 287. Similarly, the switch 265 is turned off and the switch 266 is turned off.
Then, predetermined charges are held in the capacitor elements 276 and 287.

Note that the reference constant current source 268 is included in the capacitors 276, 277, and 287.
The description of the operation when a predetermined charge is held using the same as in the first embodiment is omitted in this embodiment mode.

When the holding of the predetermined charge in the capacitor 276 is completed, the input potential _Vin1 is input to one terminal of the capacitor 276, and when the holding of the predetermined charge in the capacitor 277 is finished, The input potential _Vin2 is input to the terminal of, and an output operation is performed. The description of the operation at this time is the same as in the first embodiment, and is omitted in this embodiment.

Next, as shown in FIGS. 26 and 27, a differential amplifier circuit to which a circuit for performing a setting operation using a current source included in an original circuit is applied will be described with reference to FIG.

In FIG. 10, the current supplied from the current source 268 is used as the current during the setting operation. In FIG. 31, the setting operation is performed using the transistor 286. The transistor 286 operates as a current source, and the magnitude of the current is determined by the bias voltage Vb applied to its gate.

Next, the operation will be described. First, as shown in FIG.
79 and 282 are turned on, and the other switches are turned off. Then, a current flows toward the transistor 274, and the setting operation of the transistor 274 can be performed. Next, as shown in FIG. 33, the switches 505, 280, and 283 are turned on,
Turn off the other switches. Then, a current flows toward the transistor 275, and the setting operation of the transistor 275 can be performed. This completes the setting operation. Therefore, as shown in FIG. 34, the switches 502, 503, 281, 28
4 is turned on and the other switches are turned off. Then, a normal operation is performed.
Note that the switch 504 can be deleted by turning on the switch 502 in the setting operation of the transistor 274.

Further, the voltage applied to the gate of the transistor 286 may be changed between the setting operation and the normal operation (output operation). Normally, in the differential amplifier circuit, the transistor 2
74 and the transistor 275 often have substantially the same amount of current. Therefore, when performing the setting operation, it is better to perform the setting operation under conditions similar to those for performing the normal operation (output operation). That is more accurate. Therefore, it is desirable to adjust the voltage applied to the gate of the transistor 286 so that half the current during normal operation (output operation) flows during the setting operation.

Thus, as another method for obtaining the same effect, FIG. 35 shows a diagram in which the transistor 506 is arranged in parallel with the transistor 286. Transistor 5
06 is preferably the same size as the transistor 286. And
During normal operation, the same voltage as that of the transistor 286 is applied to the gate of the transistor 506 so that no current flows through the transistor 506 during the setting operation.

As a circuit similar to FIG. 35, FIG. 36 shows a circuit diagram in the case where the magnitude of current is changed by the switch 507 during normal operation and during setting operation. During setting operation,
By turning off the switch 507, the current value is halved.
Switch 507 is turned on. As a result, the setting operation can be performed in a state close to the actual operation state, so that the effect of the setting operation is improved.

Next, the case where the transistors included in the differential amplifier circuit illustrated in FIG. 10 have opposite conductivity types will be described with reference to FIGS.

In the differential amplifier circuit illustrated in FIG. 11, 272 and 273 are n-channel transistors, and 274, 275, and 286 are p-channel transistors. One terminal of the switch 281 is an input terminal, and the input potential _Vin1 is input to one terminal of the capacitor 276. One terminal of the switch 284 is also an input terminal, and the input potential _Vin2 is input to one terminal of the capacitor 277. Further, the potential of the source region of the transistor 275 becomes the output potential _Vout .

Note in the differential amplifier circuit shown in FIG. 11, the power supply potential V _dd1 is applied to the power supply line 291, the power supply potential V _dd1 is applied to the power supply line 267, a ground potential V _ss to a power supply line 271
Except for the point that is applied, the configuration and operation of the differential amplifier circuit shown in FIG.

In the differential amplifier circuit shown in FIGS. 10 and 11, the location where the reference constant current source 268 is disposed is different. In the present invention, the location where the reference constant current source 268 is disposed is not particularly limited, but the following conditions must be satisfied.

As described above, when the predetermined constant charge is held in the capacitors 276, 277, and 287 using the reference constant current source 268, the switches 265 and 266 are controlled. That is, the switch 265 and the switch 26
6, it is necessary to prevent current from flowing through the capacitor 277 and the transistor 275 when the capacitor 276 holds a predetermined charge. Similarly, when the capacitive element 277 holds a predetermined charge, the capacitive element 2
It is necessary to prevent current from flowing through the transistor 76 and the transistor 274.

That is, the reference constant current source 268 and the switch 26 are set so that the two capacitive elements of the capacitive element 276 and the capacitive element 277 do not hold predetermined charges at the same time.
5 and switch 266 need to be arranged. Moreover, it is necessary to add and arrange switches as necessary.

Based on the above, the locations where the reference constant current source 268, the switch 265, and the switch 266 are disposed are not limited to the locations shown in FIGS. For example, in FIG. 11, the switch 265 is provided between the power supply line 271 and the source region of the transistor 272, and the switch 266 is connected to the power supply line 271 and the transistor 273.
It may be arranged between the source regions. The switch 265 is connected to the transistor 27.
The switch 266 may be disposed between the drain region of the transistor 273 and the switch 280.

Next, FIG. 37 illustrates the case where the transistors included in the differential amplifier circuit illustrated in FIG. 31 have opposite conductivity types. Since this is also the same as the configuration and operation of the differential amplifier circuit shown in FIG. 31, the description thereof is omitted here.

Similarly in FIG. 37, it is possible to control the current value of the current source portion by doing as shown in FIGS.

In the present embodiment, the electric circuits shown in FIGS. 10 and 11 are shown as differential amplifier circuits. However, the present invention is not limited to this, and the voltages input as the input potential _Vin1 and the input potential _Vin2 are appropriately changed. Thus, it can be used as another arithmetic circuit such as a sense amplifier.

Next, an operational amplifier to which the present invention is applied will be described with reference to FIGS. FIG. 12A shows a circuit symbol of the operational amplifier, and FIG. 12B shows a circuit configuration of the operational amplifier.

There are various circuit configurations of operational amplifiers. Therefore, FIG.
2 describes the case where a source follower circuit is combined with a differential amplifier circuit as the simplest case. Therefore, the circuit configuration of the operational amplifier is not limited to FIG.

In the operational amplifier, the characteristics are defined by the relationship between the input potential V _in1 and the input potential V _in2 and the output potential V _out . More specifically, the operational amplifier has a function of multiplying the voltage of the difference between the input potential V _in1 and the input potential V _in2 by the amplification factor A and outputting the output potential V _out .

In the operational amplifier illustrated in FIG. 12B, one terminal of the switch 281 is an input terminal, and the input potential V _in1 is input to one terminal of the capacitor 276. One terminal of the switch 284 is also an input terminal, and the input potential _Vin2 is input to one terminal of the capacitor 277. Further, the potential of the source region of the transistor 292 becomes the output potential _Vout .

In the circuit shown in FIG. 12B, a portion surrounded by a dotted line 305 is shown in FIG.
This is the same configuration as the differential amplifier circuit shown in FIG. A portion surrounded by a dotted line 306 is the same as that of the source follower circuit shown in FIGS. 1 and 2, and thus detailed description of the operational amplifier shown in FIG. 12B is omitted.

In FIG. 12B, the current source 268 is shared by the differential amplifier circuit 305 and the source follower circuit 306.
Therefore, in FIG. 38, the same configuration as the differential amplifier circuit shown in FIG. 31 is used for the portion surrounded by a dotted line indicated by 305, and the source follower shown in FIG. An operational amplifier in the case of using the same configuration as the circuit is shown.

FIG. 13 illustrates an operational amplifier in the case where the transistor 299 is a p-channel type. That is, it corresponds to the case where a push-pull circuit is used. In FIG. 13B, one terminal of the capacitor 300 is connected to the drain region of the transistor 275 through the switch 302 and the switch 278 except that FIG.
), The detailed description of the configuration is omitted in this embodiment.

FIG. 39 shows an operational amplifier when the same configuration as that of the differential amplifier circuit shown in FIG. 31 is used in a portion surrounded by a dotted line 305 with respect to FIG. In FIG. 39, the source follower circuit is a push-pull circuit, and there is no bias current source. Therefore, the current of the current source in the differential amplifier circuit is used as the current used during the setting operation of the source follower circuit (push-pull circuit). That is, the transistor 286 can be connected to a push-pull circuit.

Note that this embodiment can be arbitrarily combined with Embodiments 1 and 2.

(Embodiment 4)
In this embodiment, a structure and operation of a semiconductor device including a photoelectric conversion element to which the present invention is applied will be described with reference to FIGS.

A semiconductor device illustrated in FIG. 14A includes a pixel portion 702 in which a plurality of pixels are arranged in a matrix over a substrate 701. A signal line driver circuit 703, first to first pixels are provided around the pixel portion 702. Fourth scan line driver circuits 704 to 707 are provided. A semiconductor device illustrated in FIG. 14A includes a signal line driver circuit 703 and four sets of scan line driver circuits 704 to 7.
However, the present invention is not limited to this, and the number of signal line driver circuits and scan line driver circuits can be arbitrarily set in accordance with the pixel structure. Signals are supplied to the signal line driver circuit 703 and the first to fourth scanning line driver circuits 704 to 707 from the outside via the FPC 708. However, the present invention is not limited to this, and electrical circuits other than the pixel portion may be supplied from the outside using an IC or the like.

First, structures of the first scan line driver circuit 704 and the second scan line driver circuit 705 are described with reference to FIG. The third scan line driver circuit 706 and the fourth scan line driver circuit 707 are similar to those in FIG.

The first scan line driver circuit 704 includes a shift register 709 and a buffer 710. The second scan line driver circuit 705 includes a shift register 711 and a buffer 712.
Have In brief, the shift registers 709 and 711 sequentially output sampling pulses in accordance with a clock signal (G-CLK), a start pulse (SP), and a clock inversion signal (G-CLKb). After that, the sampling pulses amplified by the buffers 710 and 712 are input to the scanning line and selected one row at a time.

Note that the shift register 709 and the buffer 710 or the shift register 71
A level shifter circuit may be arranged between 1 and the buffer 712.
By arranging the level shifter circuit, the voltage amplitude can be increased.

Next, the structure of the signal line driver circuit 703 is described with reference to FIG.

The signal line driver circuit 703 includes a signal output line driver circuit 715, a sample hold circuit 716, a bias circuit 714, and an amplifier circuit 717. Bias circuit 71
4 forms a source follower circuit paired with the amplifying transistor of each pixel. The sample hold circuit 716 has functions of temporarily storing a signal, performing analog / digital conversion, and reducing noise. The signal output drive circuit 715 has a function of outputting a signal for sequentially outputting the temporarily stored signals. The amplifier circuit 717 includes a sample hold circuit 716.
And a circuit for amplifying the signal output from the signal output drive circuit 715. Note that the amplifier circuit 717 is not necessarily provided when it is not necessary to amplify the signal.

The configuration and operation of the circuit of the pixel 713 arranged in the i-th column and the j-th row in the pixel portion 702 and the peripheral bias circuit 714 in the i-th column will be described with reference to FIG.

First, the configuration of the circuit of the pixel 713 arranged in the i-th column and the j-th row and the bias circuit 714 around the i-th column will be described.

The pixel shown in FIG. 15 includes first to fourth scanning lines Ga (j) to Gd (j) and a signal line S.
(I) The power supply line V (i) is included. In addition, an n-channel transistor 255,
A photoelectric conversion element 257 and switches 250 to 254 are included.

In this embodiment, the transistor 255 is an n-channel transistor; however, the present invention is not limited to this and may be a p-channel transistor. However, since the transistor 255 and the transistor 260 form a source follower circuit, it is preferable that both transistors have the same polarity.

The switches 250 to 254 are semiconductor elements having a switching function, and preferably transistors are used. Switch 251 and switch 25
2 is controlled to be turned on or off by a signal input from the first scanning line Ga (j). The switch 250 is controlled to be turned on or off by a signal input from the second scanning line Gb (j). The switch 253 is controlled to be turned on or off by a signal input from the third scanning line Gc (j). The switch 254 is controlled to be turned on or off by a signal input from the fourth scanning line Gd (j).

One of a source region and a drain region of the transistor 255 is connected to the power supply line V (i), and the other is connected to the signal line S (i) through the switch 250. A gate electrode of the transistor 255 is connected to one terminal of the capacitor 256. The other terminal of the capacitor 256 is connected to the photoelectric conversion element 2 via the switch 253.
57 is connected to one terminal. The other terminal of the photoelectric conversion element 257 is connected to the power supply line 258. A ground potential V _ss is applied to the power supply line 258. The capacitor 256 plays a role of holding the gate-source voltage of the transistor 255 when the setting operation is performed.

The bias circuit 714 includes a transistor 260, a capacitor 261, and a switch 2
59. The source region of the transistor 260 is connected to the power supply line 264, and the drain region is connected to the signal line S (i). The power supply line 264 has a ground potential V
_ss is applied. A gate electrode of the transistor 260 is connected to one terminal of the capacitor 261. The other terminal of the capacitor 261 is connected to the power supply line 264. The capacitor 261 plays a role of holding the gate-source voltage of the transistor 260 when the setting operation is performed.

Reference numeral 247 is a reference constant current source, which has a capability of flowing a constant current. The reference constant current source 247 is configured by a semiconductor element such as a transistor. In this specification, an example of the reference constant current source 247 including a transistor will be described later in Embodiment 6 and may be referred to.

A power line 245 is connected to the power line V (i) via a switch 248. A reference constant current source 247 is connected via a switch 249. Then, the power supply potential V _dd1 is applied to the power supply line 245, the power supply potential V _dd2 is applied to the power supply line 246. The power supply potential V _dd1 applied to the power supply line 245 and the power supply line 24
The power supply potential V _dd2 applied to 6 may be the same value or a different value. However, the power supply potential V _dd2 applied to the power supply line 246 needs to be set to a value that allows the reference constant current source 247 to operate normally as a constant current source. For example, when the reference constant current source 247 configures the current source using the saturation region of the transistor, it is necessary to set the value within a range in which the transistor can operate in the saturation region.

The reference constant current source 247 may be formed integrally with the signal line driver circuit on the substrate. Alternatively, a constant current may be input from the outside of the substrate using an IC or the like as the reference current.

Further, the places where the switches 248 and 249 and the reference constant current source 247 are arranged are not limited to the places shown in FIG. With reference to Embodiments 1 to 3 described above, they may be arranged at different locations, for example, incorporated in the pixel 713.

In FIG. 15, a portion surrounded by a dotted line 719 and a portion surrounded by a dotted line 714 correspond to a source follower circuit.

Next, the operation of the circuit of the pixel 713 arranged in the i-th column and the j-th row and the operation of the bias circuit 714 around the i-th column will be briefly described.

First, in the pixel 713, the switches 249 to 252 and the bias circuit 7 are used.
14, the switch 259 is turned on. The other switches are turned off. Then, the signal current I _data set in the reference constant current source 247 is passed through the switches 249, 252 and 251, and then the switch 25
The current flows in the direction of the power line 264 through 0 and further through the switch 259.

At the moment when current starts to flow, no charge is held in the capacitive elements 256 and 261. Therefore, the transistors 255 and 260 are off.

Then, charges are gradually accumulated in the capacitive elements 256 and 261, and the capacitive elements 256 are stored.
, 261 begins to generate a potential difference between the two electrodes. When the potential difference between the electrodes of the capacitors 256 and 261 reaches the threshold voltage of the transistors 255 and 260, the transistors 255 and 260 are turned on.

Next, the voltage between the gate and the source of the transistor 255 is set to a predetermined signal current I _data
The charge is continuously accumulated in the capacitor 256 so that the voltage can flow. The voltage between the gate and source of the transistor 260 is a predetermined signal current.
The charge is continuously accumulated in the capacitor 261 so that the voltage at which I _data can flow is obtained.

Then, in the capacitive elements 256 and 261, after the accumulation of electric charges ends and a steady state is reached, the switches 251, 252, and 259 are turned off. Switch 249, 2
50 is still on. All the switches other than the above are turned off. At this time, the signal current I _data set by the reference constant current source 247 is further transferred from the drain region of the transistor 255 through the source region to the transistor 2.
It flows from the drain region of 60 through the source region.

Subsequently, in this state, in the pixel 713, the switch 248, the switch 250, and the switch 253 are turned on, and the other switches are turned off.

Then, a signal is input from the photoelectric conversion element 257 to the gate electrode of the transistor 255 through the capacitor 256.

At this time, a value obtained by adding a signal from the photoelectric conversion element 257 is input to the gate electrode of the transistor 255 in addition to the voltage held in the capacitor 256. That is, a signal input to the gate electrode of the transistor 255 is a signal input to the gate electrode of the transistor in addition to the voltage held in the capacitor 256. Therefore, the influence of variation in transistor characteristics can be suppressed.

The potential is the output potential V _out next to the source region of the transistor 255, the output potential V _out is a signal read by the photoelectric conversion element 257, the switch 25
The signal is output to the signal line S (i) via 0.

Next, the switch 254 is turned on and all other switches are turned off, so that the photoelectric conversion element 257 is initialized. More specifically, the photoelectric conversion element 2 so that the potential of the n-channel side terminal of the photoelectric conversion element 257 is the same as the potential of the power supply line 258.
The electric charge held by 57 flows through the switch 254 in the direction of the power supply line V (i). Thereafter, the above operation is repeated.

The semiconductor device of the present invention having the above structure can suppress the influence of variation in transistor characteristics.

The present invention can be arbitrarily combined with Embodiments 1 to 3.

(Embodiment 5)
In this embodiment, an example of an electric circuit to which the present invention is applied, which is different from those in Embodiments 3 and 4, will be described with reference to FIGS.

In FIG. 16A, reference numeral 310 denotes the source follower circuit shown in FIGS. Since the circuit configuration and operation of the source follower circuit 310 are the same as those in FIGS.
In this embodiment, the description is omitted.

As described above, the operation of the source follower circuit 310 can be roughly divided into a setting operation and an output operation. Note that the setting operation is an operation of holding a predetermined charge in the capacitor, and corresponds to the operation illustrated in FIGS. Also the output operation, by inputting an input voltage V _in, and that the operation of taking out the output voltage V _out, corresponds to the operation shown in FIG. 2 (B).

In the source follower circuit 310, the terminal a corresponds to an input terminal, and the terminal b corresponds to an output terminal. The switches 127, 116, and 118 are controlled by a signal input from the terminal c. The switches 115, 117, and 120 are controlled by a signal input from the terminal d. The switch 128 is controlled by a signal input from the terminal e.

When designing an electric circuit including the source follower circuit 310, as shown in FIG. 16B, at least two source follower circuits 315 and 316 are provided.
It is good to arrange. One of the source follower circuits 315 and 316 may perform a setting operation, and the other may perform an output operation. Then, since two operations can be performed at the same time, the operation is not wasted and no wasted time is required, so that the operation of the electric circuit can be performed at a higher speed.

If only one source follower circuit is arranged, the output operation cannot be performed during the setting operation. Therefore, useless time is generated.

In the source follower circuits 315 and 316, the setting operation and the output operation are not performed simultaneously. Therefore, it is not necessary to arrange one current source 126 in each of the source follower circuits 315 and 316. That is, one current source 12
6 can be shared by the source follower circuits 315 and 316.

For example, when designing a signal line driver circuit using a source follower circuit, it is preferable to arrange at least two source follower circuits for each signal line. In designing a scanning line driver circuit using a source follower circuit, it is preferable to dispose at least two source follower circuits for each scanning line. When designing a pixel using a source follower circuit, it is preferable to arrange at least two source follower circuits for each pixel.

In FIG. 16B, reference numerals 311 to 314 denote switches. Switch 311,
When 312 is on, the switches 313 and 314 are off. Switch 3
When the switches 11 and 312 are off, the switches 313 and 314 are turned on. In this way, one of the two source follower circuits 315 and 316 performs the setting operation, and the other performs the output operation. In addition, switch 311-switch 3
14, switches 116 and 118 included in the source follower circuit 310.
The two source follower circuits 315 and 316 may be controlled by controlling.

In the present embodiment, the portions 315 and 316 surrounded by the dotted line correspond to the source follower circuit, but the present invention is not limited to this, and the differential amplifier circuit and the operational amplifier shown in FIGS. Etc. may be applied.

In this embodiment, the structure and operation of a signal line driver circuit in which at least two source follower circuits are arranged for each signal line will be described with reference to FIGS.

FIG. 17 shows a signal line driver circuit. The signal line driver circuit includes a shift register 321, a first latch circuit 322, a second latch circuit 323, a D / A converter circuit 324, and a signal amplifier circuit 325. Have.

Note that in the case where the first latch circuit 322 or the second latch circuit 323 is a circuit that can store analog data, the D / A conversion circuit 324 can be omitted in many cases. If the data output to the signal line is binary, that is, a digital quantity, D
In many cases, the / A conversion circuit 324 can be omitted. The D / A conversion circuit 324 includes
There may be a built-in gamma correction circuit. Thus, the signal line driver circuit is
The configuration is not limited to that shown in FIG.

To briefly describe the operation, the shift register 321 includes a flip-flop circuit (
FF) etc., using multiple columns, clock signal (S-CLK), start pulse (SP)
The clock inversion signal (S-CLKb) is input, and sampling pulses are sequentially output according to the timing of these signals.

The sampling pulse output from the shift register 321 is input to the first latch circuit 322. A video signal is input to the first latch circuit 322, and the video signal is held in each column in accordance with the timing at which the sampling pulse is input.

When the first latch circuit 322 completes holding of the video signal up to the last column, a latch pulse (Latch Pulse) is sent to the second latch circuit 323 during the horizontal blanking period.
, And the video signals held in the first latch circuit 322 are transferred to the second latch circuit 323 all at once. After that, the video signal held in the second latch circuit 323 is input to the D / A conversion circuit 324 for one row at the same time. A signal input from the D / A conversion circuit 324 is input to the signal amplification circuit 325.

While the video signal held in the second latch circuit 323 is input to the D / A conversion circuit 324, the sampling pulse is output again in the shift register 321. Thereafter, this operation is repeated.

Then, the signal amplification circuit 325 around the three signal lines from the i-th column to the (i + 2) -th column.
The configuration will be described with reference to FIG.

The signal amplification circuit 325 includes two source follower circuits 315 and 316 for each column. The source follower circuits 315 and 316 each have five terminals from terminal a to terminal e. The terminal a corresponds to an input terminal in the source follower circuits 315 and 316, and the terminal b corresponds to an output terminal in the source follower circuits 315 and 316. Further, the switches 127, 116, 1 and 2 are determined by a signal input from the terminal c.
18 is controlled, and switches 115, 117, 1 are controlled by a signal input from a terminal d.
20 is controlled. Further, the switch 128 is controlled by a signal input from the terminal e.

In the signal amplifier circuit 325 shown in FIG. 18, a logical operator is arranged between the two signal lines of the setting signal line 326 and the threshold signal line 327 and the source follower circuits 315 and 316. ing. 329 is an inverter, 330 is an AND, 3
31 and 332 are inverters, and 333 is an AND. Then, either a signal output from the setting signal line 327 or a signal output from the output terminal of the logical operator is input to the terminals c to e.

Next, signals output from the two signal lines of the setting signal line 326 and the threshold signal line 327, and signals input to the switches via the terminals c to e in the source follower circuits 315 and 316 Will be described with reference to FIG.

Note that a switch to which a signal is input via the terminals c to e is turned on when a high signal is input, and is turned off when a low signal is input.

Then, signals as shown in FIG. 19 are input from the two signal lines of the setting signal line 326 and the threshold signal line 328. Further, the signal output from the setting signal line 326 is input to the terminal c in the source follower circuit 315 as it is. A signal output from the output terminal of the AND 330 is input to the terminal d, and a signal output from the output terminal of the inverter 331 is input to the terminal e. Then
The source follower circuit 315 can be controlled to perform either the setting operation or the output operation.

In addition, a signal output from the output terminal of the inverter 332 is input to the terminal c in the source follower circuit 316. A signal output from the output terminal of the AND 333 is input to the terminal d, and a signal output from the setting signal line 326 is input to the terminal e as it is. Then, the source follower circuit 316 can be controlled to perform either the setting operation or the output operation.

In FIG. 16, a current source 126 is arranged in each source follower circuit. Therefore, it is desirable that the current values flowing from the current sources 126 arranged in the signal line driver circuit do not vary. Therefore, it is possible to prevent the current value from varying by performing a setting operation on each current source 126. Regarding this technique, Japanese Patent Application No. 2002-2002 which is the inventor's invention.
No. 287997, Japanese Patent Application No. 2002-288104, Japanese Patent Application No. 2002-28043, Japanese Patent Application No. 2002-287921, Japanese Patent Application No. 2002-287948, and the like. Therefore, by applying this technique to the present application, it is possible to correct the characteristic variation of the current source 126 even when a plurality of the signal line driver circuits are arranged.

So far, FIGS. 16, 18 and 19 have described the case of using a source follower circuit in the case where a current source is arranged outside the original circuit as shown in FIG. Next, an example in which a source follower circuit as shown in FIGS. 27 and 29 is used will be described.

FIG. 40 shows a diagram corresponding to FIG. Also, a diagram corresponding to FIG.
As shown in FIG. FIG. 42 shows a diagram corresponding to FIG. Since the operation and the like are the same as before, they are omitted. Compared to the cases of FIG. 16, FIG. 18, and FIG.
In FIG. 16A, the current source 126 is arranged, but not arranged in FIG. As a result, circuit arrangement is facilitated and layout can be performed in a small area. In addition, as described above, in FIG. 16A, it is desirable to have an additional circuit in order to prevent the current value of the current source 126 from varying.
This is not necessary in the circuit of FIG. As a result, circuit arrangement is facilitated and layout can be performed in a small area. In addition, the drive timing becomes simpler.

In many cases, a plurality of pixels are connected to the tip of each signal line of the signal line driver circuit. In many cases, the pixel changes its state by a voltage input from a signal line. Examples include LCD and organic EL. In addition, various things can be connected.

Note that this embodiment mode can be arbitrarily combined with Embodiment Modes 1 to 4.

(Embodiment 6)
In the electric circuit and semiconductor device of the present invention described above, a reference constant current source having a capability of flowing a constant current is disposed, and a setting operation is performed using the reference constant current source. The reference constant current source is composed of a semiconductor element such as a transistor. Therefore, in this embodiment, the configuration of the reference constant current source in the case where the transistor is configured with a transistor and a capacitor is described with reference to FIGS.

First, the outline of the reference constant current source will be described with reference to FIG. In FIG. 20A, reference numeral 401 denotes a reference constant current source. The reference constant current source 401 has a terminal A, a terminal B, and a terminal C. A setting signal is input to the terminal A. A current is supplied to the terminal B from a current supply line 405 to the outside. A current set in the reference constant current source 401 is supplied from the terminal C. In other words, the reference constant current source 401 is controlled by the setting signal input to the terminal A, the current is supplied from the terminal B, and the current is supplied from the terminal C.

In FIG. 20B, reference numeral 404 denotes a reference constant current source. The reference constant current source 404 has a plurality of reference constant current sources. Here, it is assumed that two reference constant current sources 402 and 403 are provided. The constant current sources for reference 402 and 403 have terminals A to D. A setting signal is input to the terminal A. A current is supplied to the terminal B from a current supply line 405.
From the terminal C, the current set in the reference constant current source 401 is supplied to the outside. A control signal output from the control line 406 is input to the terminal D. That is, the reference constant current sources 402 and 403 are controlled by a setting signal input to the terminal A and a control signal input to the terminal D, and current is supplied from the terminal B and current is supplied from the terminal C. .

Next, the configuration of the reference constant current source 401 illustrated in FIG. 20A will be described with reference to FIGS.

The electric circuits shown in FIGS. 21A to 21F all correspond to the reference constant current source 401.

21A and 21B, a switch 54 to a switch 56, an n-channel transistor 52, and a capacitor 53 that holds a gate-source voltage of the transistor 52 when a setting operation is performed. The electric circuit that is included corresponds to the reference constant current source 401. The electric circuits shown in FIGS. 21A and 21B have the same circuit elements, but the connection relations of the circuit elements are different.

In FIG. 21C, an electric circuit having switches 74 and 75, n-channel transistors 72 and 76, and a capacitor 73 that holds a gate-source voltage of the transistor 72 when a setting operation is performed. Is a constant current source for reference 40
Corresponds to 1.

21D to 21F, the switches 68 and 70, the n-channel transistors 65 and 66, and the transistors 65 and 6 when the setting operation is performed.
The electric circuit having the capacitor 67 that holds the gate-source voltage of 6 corresponds to the reference constant current source 401. The electric circuits illustrated in FIGS. 21D to 21F have the same circuit elements, but the connection relation of the circuit elements is different.

Subsequently, the operation of the reference constant current source 401 shown in FIGS.
The operation of the reference constant current source 401 shown in FIGS. 21D to 21F will be briefly described below. Since the operation of the reference constant current source 401 illustrated in FIG. 21C is similar to the operation of the circuit illustrated in FIGS. 21A and 21B, description thereof is omitted in this embodiment.

First, the operation of the reference constant current source 401 shown in FIGS. 21A and 21B will be described. In the electric circuits shown in FIGS. 21A and 21B, the switches 54 and 55 are turned on by a signal input through the terminal A. At this time, the switch 56 is off. Then, a current is supplied from the current supply line 405 via the terminal B, and a predetermined charge is held in the capacitor element 53.

Next, the switches 54 and 55 are turned off. At this time, since a predetermined charge is held in the capacitor 53, the transistor 52 has a capability of flowing a current having the magnitude of the signal current _Idata .

Then, the switches 54 and 55 are kept off and the switch 56 is turned on. Then, a predetermined current flows from the terminal C. At this time, the transistor 5
2 is maintained at a predetermined gate-source voltage by the capacitive element 53, the signal current I _data is present in the drain region of the transistor 52.
A drain current corresponding to the current flows.

Note that in the case of the circuits shown in FIGS. 21A and 21B, the operation of holding a predetermined charge in the capacitor 53 and the operation of supplying a predetermined current cannot be performed simultaneously. For this reason, the timing at which a predetermined charge is held in the capacitor 53 and the timing at which a predetermined current is supplied are controlled using the switches 54 to 56.

Next, the operation of the reference constant current source 401 will be described with reference to FIGS. In the electric circuits illustrated in FIGS. 21D to 21F, the switches 68 and 70 are turned on by a signal input through the terminal A. Then, a current is supplied from the current supply line 405 via the terminal B, and a predetermined charge is held in the capacitor 67. At this time, since the gate electrode of the transistor 65 and the gate electrode of the transistor 66 are connected, the transistor 65 and the transistor 6
6 is held by the capacitive element 67.

Next, the switches 68 and 70 are turned off. At this time, since a predetermined charge is held in the capacitive element 67, the transistors 65 and 66 have a capability of flowing a current having the magnitude of the signal current I _data . In other words, since the gate-source voltage of the transistor 66 is maintained at a predetermined gate-source voltage by the capacitor 67, a drain current corresponding to the signal current I _data flows in the drain region of the transistor 66.

Note that in the case of the circuits illustrated in FIGS. 21D to 21F, the operation of holding a predetermined charge in the capacitor 67 and the operation of supplying a predetermined current can be performed simultaneously.

In the case of the circuits shown in FIGS. 21D to 21F, the sizes of the transistors 65 and 66 are important. When the sizes of the transistor 65 and the transistor 66 are the same, a current having the same value as the current supplied from the current supply line 405 flows through the terminal C. On the other hand, when the sizes of the transistors 65 and 66 are different, that is, W (gate width) /
When the value of L (gate length) is different, the value of the current supplied from the current supply line 405 and the value of the current flowing through the terminal C are different. The difference depends on the W / L value of both transistors.

In the electric circuits shown in FIGS. 21A to 21F, current flows from the terminal C toward the ground potential V _ss . FIG. 22 shows a circuit configuration when the polarity of the transistors 52, 65, and 66 is a p-channel type and current flows from the terminal C toward the ground potential V _ss .

The direction of current flow is determined from the terminal C to the ground potential V _ss as shown in FIGS.
It is not limited only to the direction that flows toward. In the electric circuit shown in FIG. 21, the ground potential V _{ss is set} to the power supply potential V _dd , and the transistors 52, 65, 66, and 72 are connected to p.
In the case of the channel type, current flows from the power supply potential V _dd toward the terminal C. In the electric circuit shown in FIG. 22, when the ground potential V _ss is the power supply potential V _dd and the transistors 52, 65, 66 are n-channel type, current flows from the power supply potential V _dd toward the terminal C.

Next, the reference constant current sources 402 and 403 illustrated in FIG. 20B will be described with reference to FIG. Note that in the case of the circuits shown in FIGS. 21A and 21B, the operation of holding a predetermined charge in the capacitor and the operation of supplying a predetermined current cannot be performed simultaneously. Therefore, as shown in FIG. 20 (B), a plurality of reference constant current sources are arranged, and in one reference constant current source, an operation of holding a predetermined charge in the capacitor element is performed, and the other constant current source is operated. In the reference constant current source, it is preferable to perform an operation of passing a predetermined current. That is, FIG.
The reference constant current sources 402 and 403 shown in FIG.
It is preferable to use the circuit shown in FIG.

In FIG. 23A, a circuit including switches 84 to 89, an n-channel transistor 82, and a capacitor 83 that holds a gate-source voltage of the transistor when a setting operation is performed is a reference. This corresponds to the constant current source 402 or 403 for use. The electric circuit illustrated in FIG. 23A is a circuit illustrated in FIGS.

23B, a circuit including the switches 94 to 97, transistors 92 and 98, and a capacitor 93 that holds the gate-source voltage of the transistor 92 when the setting operation is performed. Constant current source 402 for reference
Or 403. The electric circuit illustrated in FIG. 23B is the circuit illustrated in FIG.

Note that the operation of the electric circuit shown in FIGS. 23A and 23B is the same as that shown in FIGS.
In this embodiment, the description is omitted.

This embodiment mode can be arbitrarily combined with Embodiment Modes 1 to 5.

(Embodiment 7)
As an electronic device using the electric circuit of the present invention, a video camera, a digital camera,
Goggle type display (head-mounted display), navigation system, sound playback device (car audio, audio component, etc.), notebook type personal computer, game machine, portable information terminal (mobile computer, mobile phone, portable game machine or electronic book) ), An image reproducing apparatus provided with a recording medium (specifically, an apparatus provided with a display capable of reproducing a recording medium such as a digital versatile disc (DVD) and displaying the image). Specific examples of these electronic devices are shown in FIGS.

FIG. 4A illustrates a light-emitting device, which includes a housing 2001, a support base 2002, and a display portion 200.
3, a speaker portion 2004, a video input terminal 2005, and the like. The present invention can be used for an electric circuit included in the display portion 2003. In addition, according to the present invention, FIG.
The light emitting device shown in A) is completed. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. Note that the light emitting device includes all display devices for displaying information such as for personal computers, for receiving TV broadcasts, and for displaying advertisements.

FIG. 4B illustrates a digital still camera, which includes a main body 2101, a display portion 2102,
Image receiving portion 2103, operation keys 2104, external connection port 2105, shutter 21
Including 06. The present invention can be used for an electric circuit included in the display portion 2102. Further, according to the present invention, the digital still camera shown in FIG. 4B is completed.

FIG. 4C illustrates a notebook personal computer, which includes a main body 2201 and a housing 2.
202, a display unit 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The present invention can be used for an electric circuit included in the display portion 2203. Further, according to the present invention, the light-emitting device shown in FIG. 4C is completed.

FIG. 4D illustrates a mobile computer, which includes a main body 2301, a display portion 2302,
A switch 2303, an operation key 2304, an infrared port 2305, and the like are included. The present invention can be used for an electric circuit included in the display portion 2302. Further, according to the present invention, the mobile computer shown in FIG. 4D is completed.

FIG. 4E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, and a display portion B24.
04, a recording medium (DVD or the like) reading unit 2405, an operation key 2406, a speaker unit 2407, and the like. The display portion A 2403 mainly displays image information, and the display portion B 2404 mainly displays character information. However, the present invention is not limited to the display portions A and B 2403.
2404 can be used. Note that an image reproducing device provided with a recording medium includes a home game machine and the like. In addition, according to the present invention, FIG.
The DVD playback apparatus shown in E) is completed.

FIG. 4F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The present invention can be used for an electric circuit included in the display portion 2502. In addition, according to the present invention, FIG.
The goggle type display shown in F) is completed.

FIG. 4G illustrates a video camera, which includes a main body 2601, a display portion 2602, and a housing 26.
03, an external connection port 2604, a remote control receiving unit 2605, an image receiving unit 2606, a battery 2607, an audio input unit 2608, an operation key 2609, and the like. The present invention can be used for an electric circuit included in the display portion 2602. Further, according to the present invention, the video camera shown in FIG. 4G is completed.

FIG. 4H illustrates a mobile phone, which includes a main body 2701, a housing 2702, and a display portion 2703.
, An audio input unit 2704, an audio output unit 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The present invention can be used for an electric circuit included in the display portion 2703. Note that the display portion 2703 can suppress current consumption of the mobile phone by displaying white characters on a black background. In addition, the mobile phone shown in FIG. 4H is completed by the present invention.

If the emission luminance of the luminescent material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like to be used for a front type or rear type projector.

In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the response speed of the light emitting material is very high, the light emitting device is preferable for displaying moving images.

In addition, since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background. It is desirable to do.

As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic device of this embodiment may use any circuit or semiconductor device having any structure described in Embodiments 1 to 6.

Claims (7)

A semiconductor device having a source follower circuit,
The source follower circuit includes first and second transistors, first and second capacitors, and first to fifth switches,
A first terminal of the first capacitor is electrically connected to a gate of the first transistor;
A first terminal of the first switch is electrically connected to a source of the first transistor;
A second terminal of the first switch is electrically connected to a second terminal of the first capacitive element;
A drain of the second transistor is electrically connected to a source of the first transistor;
A first terminal of the second switch is electrically connected to a drain of the second transistor;
A second terminal of the second switch is electrically connected to a gate of the second transistor;
A first terminal of the second capacitor is electrically connected to a gate of the second transistor;
A second terminal of the second capacitor is electrically connected to a source of the second transistor;
A first terminal of the third switch is electrically connected to an input terminal;
A second terminal of the third switch is electrically connected to a second terminal of the first capacitor;
A first terminal of the fourth switch is electrically connected to an output terminal;
A second terminal of the fourth switch is electrically connected to a source of the first transistor;
A first terminal of the fifth switch is electrically connected to the wiring;
The semiconductor device, wherein the second terminal of the fifth switch is electrically connected to the drain of the first transistor. A semiconductor device having a source follower circuit,
The source follower circuit includes first and second transistors, first and second capacitors, and first to fifth switches,
A gate of the first transistor is electrically connected to a source of the first transistor through the first capacitor and the first switch;
A gate of the second transistor is electrically connected to a source of the second transistor through the second capacitor;
The drain of the second transistor is electrically connected to the gate of the second transistor via the second switch,
A source of the first transistor is electrically connected to an input terminal via the first switch and the third switch;
The output terminal is electrically connected to the source of the first transistor through the fourth switch,
A drain of the first transistor is electrically connected to a wiring through a fifth switch;
The semiconductor device is characterized in that the drain of the second transistor is electrically connected to the source of the first transistor. In claim 1 or claim 2,
The third switch is controlled to be turned on or off depending on a signal,
The semiconductor device, wherein the fourth switch is controlled to be turned on or off depending on the signal. In any one of Claims 1 thru | or 3,
The semiconductor device is characterized in that the gate length of the first transistor is different from the gate length of the second transistor. In any one of Claims 1 thru | or 4,
The semiconductor device according to claim 1, wherein a gate width of the first transistor is different from a gate width of the second transistor.   An electronic apparatus comprising the semiconductor device according to claim 1. An antenna, an audio output unit or operation keys;
An electronic apparatus comprising: the semiconductor device according to claim 1.

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