JP2000013153A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of correcting the manufacturing variation of voltage gain of an amplification MOS transistor(TR) that outputs a signal corresponding to photo charges generated from the light made incident on a photodiode receiving. SOLUTION: A source follower circuit 2 consists of an amplification MOS TR 2 and a resistor array 7 connected to a source comprising a plurality of resistors and MOS TRs each connected to each resistor in parallel. The resistance of the resistor array 7 is set under the control of a memory block 10 that has a memory cell array consisting of read only memory elements, which writes information of a resistance providing an optimum voltage gain is electrically writable only once.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device using a source-follower circuit for photo-electric charge detection and, in combination with a non-volatile semiconductor device, corrects manufacturing variations such as resistance and changes operating conditions to improve the yield. Improving and stabilizing performance.

[0002]

2. Description of the Related Art Conventionally, a solid-state imaging device using an N-channel MOS (metal-oxide-semiconductor) transistor as an amplification element has been known. FIG. 5 is a drawing showing the configuration of such a conventional solid-state imaging device.

Referring to FIG. 5, the photoelectric conversion cell includes a photodiode 70, an amplifying MOS transistor 71 for amplifying a signal based on photocharges accumulated by the photodiode 70 and extracting the signal as an output voltage signal, and an amplifier M.
A reset MOS transistor 74 for initializing the gate potential of the OS transistor 71 to the potential Vr;
A resistive load 73 that converts the detected current into a detection voltage according to the sensor current amplified by the OS transistor 71 is connected.

Here, the amplification MOS transistor 71 is source-followed. That is, the gate is connected to the photodiode 70, and the drain is connected to the power supply voltage Vdd.
, And the source is connected to the output terminal Vout, and grounded via the load resistor 73.

Here, the charge amount accumulated by the photodiode 70 is represented by Qs, the photodiode 70 and the amplification M
The sum of the parasitic capacitance of the OS transistor 71 is represented by Cpd, and the amplification M
Assuming that the change in the gate voltage of the OS transistor 71 is ΔVg, the voltage gain of the source follower of the amplifying MOS transistor 71 is A, the transfer conductance thereof is gm, and the resistance value of the load resistor 73 is Rs, the signal output ΔV output from the output terminal Vout. ΔV = A · ΔVg = {gm · Rs / (1 + gm · Rs)} · (Qs / Cp
d) The signal output ΔV depends on the transmission conductance gm of the amplification MOS transistor 71 and the resistance value Rs of the load resistor 73.

[0006]

As described above, the amplification MO
Since the voltage gain A of the S transistor 71 depends on the conductance gm of the amplifying MOS transistor 71 and the resistance value Rs of the load resistor 73, these values need to be set strictly.

However, the amplification MOS transistor 7
If the conductance gm of 1 and the resistance value Rs of the load resistor 73 fluctuate due to manufacturing variations, the output voltage will vary between the solid-state imaging devices.

[0008] In the prior art, in order to solve this variation in output voltage, in testing in a wafer state, ranking was performed according to the output voltage. In order to correct the amplification factor, an external load resistor is connected.

[Object of the Invention] The object of the present invention is to
It is an object of the present invention to solve the above-mentioned problems and to provide a semiconductor device capable of realizing a stable output voltage without attaching an external load resistor to a voltage gain A of an amplification MOS transistor 71.

[0010]

In order to achieve the above object, a semiconductor device according to the present invention employs the following structure.

According to the semiconductor device of the present invention, a photoelectric conversion element for generating a photoelectric charge corresponding to the amount of incident light, a charge storage unit for storing the photoelectric charge generated by the photoelectric conversion element, and a potential of the charge storage unit are initialized. Reset switch and the potential of the charge storage section are input to the gate electrode of the amplification MOS transistor,
A source follower circuit for generating an output signal corresponding to the potential of the charge storage portion, and a memory block for storing data for controlling an output voltage of the source follower circuit are provided.

According to the semiconductor device of the present invention, a photoelectric conversion element for generating a photoelectric charge according to the amount of incident light, a charge storage unit for storing the photoelectric charge generated by the photoelectric conversion element, and a potential of the charge storage unit are initialized. Reset switch and the potential of the charge storage section are input to the gate electrode of the amplification MOS transistor,
A source follower circuit for generating an output signal corresponding to the potential of the charge storage unit; and a memory block for storing data for controlling the output voltage of the source follower circuit. The source follower circuit includes an amplifying MOS transistor and a source of the amplifying MOS transistor. A memory cell array having a plurality of resistors connected in series to each other and a MOS transistor connected in parallel to each resistor, wherein the memory block has a read-only nonvolatile memory element which can be electrically written only once, and a memory cell array. A data read control circuit for controlling the reading of information from the memory and a data latch circuit.

According to the semiconductor device of the present invention, a photoelectric conversion element for generating a photoelectric charge corresponding to the amount of incident light, a charge storage unit for storing the photoelectric charge generated by the photoelectric conversion element, and a potential of the charge storage unit are initialized. Reset switch and the potential of the charge storage section are input to the gate electrode of the amplification MOS transistor,
A source follower circuit for generating an output signal corresponding to the potential of the charge storage unit; and a memory block for storing data for controlling the output voltage of the source follower circuit. The source follower circuit includes an amplifying MOS transistor and a source of the amplifying MOS transistor. The memory block has a resistor array composed of a plurality of resistors connected in series and MOS transistors connected in parallel to each resistor, and the memory block is an n-channel MOS which is a read-only memory element that can be electrically written only once.
A memory cell array including a transistor, a terminal for supplying a write voltage, and a memory cell having a resistance for comparing a resistance value; a data read control circuit and a data latch circuit for controlling reading of information from the memory cell array; It is characterized by having.

[Operation] In the semiconductor device of the present invention, the output voltage of the source follower circuit is output by amplifying the charge generated by the light incident on the photodiode by the amplifying MOS transistor. At that time, the amplification factor can be arbitrarily changed by selecting the resistance of the resistance array.

Therefore, after the manufacture of the semiconductor integrated circuit device, the selection information of the resistor array for obtaining the output voltage most matching the semiconductor device specifications is stored in the nonvolatile memory of the memory block. The information written in this memory block is stored in the MO that constitutes the resistance array at power-on or immediately after power-on.
By reading as the gate control signal of the S transistor, the output voltage of the source follower circuit can be set to an optimum value.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit block diagram illustrating a semiconductor device according to an embodiment of the present invention. A description will be given of an example in which a pn junction type photodiode is used as a photoelectric conversion element, a parasitic capacitance of the pn junction type diode is used as a photocharge storage unit, and a MOS transistor is used as a reset switch.

[Structural Description of Semiconductor Device: FIG. 1] As shown in FIG. 1, the semiconductor device has a pn junction type photodiode 1 as a photoelectric conversion element, a parasitic capacitance 8 as a charge storage part, and A source follower circuit 2 for outputting a signal corresponding to a photocharge generated by light incident on the diode 1, a reset MOS transistor 3 as a reset switch for initializing an input potential of the source follower circuit 2 to a reset potential Vr, This source follower circuit 2
And a memory block 10 for storing data for controlling the output voltage of the memory.

Further, the source follower circuit 2 includes an amplification MO
It comprises an S transistor 5 and a resistor array 7.
Here, the gate of the amplifying MOS transistor 5 is connected to the photodiode 1, the drain is connected to the high potential of the power supply voltage (hereinafter referred to as Vdd), the source is connected to the output terminal 6, and the resistance array 7 is connected. To a low power supply potential (hereinafter referred to as Vss).

The memory block 10 includes a 3-bit memory cell array 11 composed of three read-only memory cells that can be electrically written only once, a data latch circuit 12, and a data read control circuit 13 for controlling data read. And the configuration.

[Explanation of Memory Operation: FIG. 2] Next, the memory operation will be described with reference to FIG. 2 which shows a part of a circuit of a memory cell constituting the memory cell array 11 of FIG.

In FIG. 2, an n-channel MOS transistor (hereinafter referred to as a memory transistor) 20 as a memory element includes a drain 21, a source 22, a gate 23,
And a substrate electrode 24. A first resistor 25 is connected between the gate 23 and the source 22, and the gate 23 is connected to the second resistor 25.
Is connected to Vss via the resistor 26 and the diode 19. Drain 21 is connected to Vdd.

Further, when information is written to the memory transistor 20, a high negative write voltage (hereinafter referred to as Vp)
The terminal 16 is connected to a source 22 via a bit line 17. The bit line 17 and the word line 15 are connected by a third resistor 18.

To write information, the bit line 1
The potential difference Vds (Vdd-Vpp) between the source 22 and the drain 21 connected via the
From the external power supply to terminal 1
6 to cause the junction breakdown between the drain and the substrate of the memory transistor 20 to occur. Due to this junction breakdown, the drain 21 and the source 22 of the memory transistor 20 are electrically short-circuited through the substrate electrode 24.

At the time of writing, since a high negative voltage Vpp is applied to the source 22, the diode 29 becomes forward and a current flows. From this Vss, diode 1
9, the second resistor 26, the first resistor 25 and the source 22
When a current flows in the path to the first resistor 25, the magnitude of the resistance of the diode 19 is sufficiently smaller than that of the first resistor 25 and the second resistor 26, so that the potential of the gate 23 becomes the first resistor 25 and the second resistor 25. Vss-0.6V to Vp depending on the size of resistor 26
It is possible to take any value between p.

That is, it is possible to make the potential difference between the gate 23 and the source 22 higher than the threshold voltage of the memory transistor 20. Therefore, writing can be performed with the memory transistor 20 turned on. Generally, the drain breakdown voltage of an enhanced n-channel MOS transistor is determined by the avalanche breakdown between the drain and the substrate,
It is determined by the electric field concentration on the surface due to the influence of the gate, and the parasitic bipolar operation involving the injection of minority carriers.

The mechanism of the junction breakdown itself is the same as that of the junction breakdown PROM. That is, in writing, the drain is reverse-biased at a voltage higher than the drain withstand voltage, so that a breakdown occurs and a current flows. Since most of the voltage is applied to the thin junction interface, heat loss at the junction is large, and the temperature of a part of the non-uniform junction suddenly rises due to thermal runaway, leading to destruction.

A junction destruction type P for destroying a diode junction
In the ROM, only the avalanche breakdown of the PN junction determines the breakdown voltage, whereas in the memory transistor, a plurality of effects reduce the drain breakdown voltage as described above.

FIG. 6 shows that the memory element has a gate length of 1.6 μm, a gate width of 8 μm, and a gate oxide film thickness of 20 n.
The relationship between the drain withstand voltage and the gate voltage with reference to the source potential when an n-channel MOS transistor having a threshold voltage of 0.5 m is used. When the gate voltage is about の of the drain voltage, the drain withstand voltage is 11 V, which is the lowest. On the other hand, when the gate voltage is 0 V, the drain withstand voltage is the highest at 18 V, and this drain withstand voltage substantially matches the reverse withstand voltage of the pn junction of the semiconductor device.

As described above, the first resistor 25 and the second resistor 2
By appropriately selecting the size ratio of 6 and performing writing with the memory transistor turned on, writing can be performed with the drain withstand voltage being the lowest.

[Explanation of Information Reading Operation: FIG. 2] Next, in the information reading operation, the potential of the bit line 27 is set to (V).
A state higher than (dd−Vss) / 2 is defined as “1”, and a state lower than “dd−Vss) / 2 is defined as“ 0 ”.

When reading the stored information, when the potential of the word line 25 is set to Vss, the resistance value of the memory transistor whose junction has been destroyed becomes the resistance value of the third resistor 18 because the drain 21 and the source 22 are short-circuited. Since it is sufficiently small, “1” is output from the bit line 17.

On the other hand, the resistance value of the memory transistor in the non-writing state in which the junction is not broken is the third resistance 1 since the memory transistor 20 is always in the off state.
Since it is sufficiently larger than the resistance value of 8, “0” is read as information.

FIG. 3 is a circuit diagram showing one embodiment of the resistor array 7 in the source follower circuit 2. Resistance array 7
Are eight series-connected resistors 31, 32, 33, 3
4, 35, 36, 37, 38, and eight MOS transistors 41, 42, 4 connected in parallel to these eight resistors.
3, 44, 45, 46, 47, 48 and the decoder 30.

Next, in order to set the output voltage of the source follower circuit 2 in FIG. 1 which conforms to the specifications after the manufacture of the semiconductor integrated circuit device, the resistance value in the resistance array 7 is controlled using the data written in the memory block 10. The method will be described with reference to FIGS.

When the output from the data latch circuit 12 of the memory block 10 is input to the decoder 30,
OS transistors 41, 42, 43, 44, 45, 4
By turning on any of 6, 47, and 48, eight types of resistance values can be selected.

For example, when the data stored in the memory block 10 is (0, 0, 0), the data controls the decoder 30 so that the MOS transistor 41 is turned on. As a result, the resistance value becomes the resistance value of the resistor 31.

If the data stored in the memory block 10 is (0, 1, 1), the data is
0, the MOS transistor 44 is turned on, and the resistance values are the resistance 31, the resistance 32, the resistance 33, and the resistance 34.
And the resistance value.

Next, the relationship between the voltage gain A and the resistance value R of the resistor array 7 when the gate voltage of the amplification MOS transistor 5 in FIG. 1 fluctuates from 2.5 V to 2 V due to accumulation of photocharges by the photodiode. Is shown in FIG. As the resistance value increases, the voltage gain A also increases. The value of the voltage gain A is set to 20 according to the combination of the resistance values of the resistance array.
% Can be corrected.

As described above, even if the transmission conductance gm of the amplifying MOS transistor or the resistance value fluctuates due to manufacturing variations or the like, the voltage gain can be corrected by changing the resistance value of the resistance array.

In the embodiment of the present invention, the number of memory elements constituting the memory block 10 is 3 bits, but the number of bits may be increased. For example, with 4 bits, 16 types of resistance values can be selected, and by increasing the number of bits, the correction amount of the resistance value can be finely adjusted.

In the embodiment of the present invention, an n-channel MOS transistor is used as a memory element of the memory element array 11 which can be written only once, but a fuse ROM or an anti-fuse ROM may be used. At this time, there is no change in the embodiment of the present invention in FIG.
It is only necessary to use a fuse ROM and an anti-fuse ROM as memory elements that can be written only once electrically and constitute the memory element array 11.

[0042]

As described above, according to the present invention,
After the semiconductor integrated circuit device has an output voltage value that fluctuates due to manufacturing variations or the like, the resistance value can be corrected and the voltage gain of the amplification MOS transistor can be set to the best value.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a memory cell according to the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a resistor array according to the embodiment of the present invention.

FIG. 4 is a graph showing a relationship between a voltage gain and a resistance value of the amplification MOS transistor according to the embodiment of the present invention.

FIG. 5 is a circuit diagram showing a semiconductor device according to the related art.

FIG. 6 is a graph showing an example of writing information in a memory cell in an embodiment of the present invention and showing a relationship between a drain withstand voltage and a gate voltage of a memory transistor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 photodiode 2 source follower circuit 2 3 reset MOS transistor 5 amplifying MOS transistor 6 output terminal 7 resistor array 8 parasitic capacitance 10 memory block

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04B 10/26 10/14 10/04 10/06 H04N 5/335 F-term (Reference) 4M118 AA10 AB01 BA06 CA03 DD09 DD12 5C024 AA01 CA14 FA01 FA11 GA01 GA31 HA10 HA23 5J092 AA01 AA56 CA00 CA11 CA14 FA12 FA18 HA10 HA19 HA25 HA27 HA39 HA44 KA00 KA19 KA28 KA31 KA33 MA02 SA08 TA02 UL02 5K002 AA03 BA07 CA10 DA05

Claims (3)

[Claims] A photoelectric conversion element for generating a photoelectric charge corresponding to an amount of incident light; a charge storage unit for storing the photoelectric charge generated by the photoelectric conversion element; a reset switch for initializing a potential of the charge storage unit; A source follower circuit for generating an output signal corresponding to the potential of the charge storage unit by using the potential of the charge storage unit as an input to the gate electrode of the amplification MOS transistor; and a memory block for storing data for controlling the output voltage of the source follower circuit And a semiconductor device comprising: 2. A photoelectric conversion element for generating a photoelectric charge according to an amount of incident light, a charge storage unit for storing the photoelectric charge generated by the photoelectric conversion element, a reset switch for initializing a potential of the charge storage unit, A source follower circuit for generating an output signal corresponding to the potential of the charge storage unit by using the potential of the charge storage unit as an input to the gate electrode of the amplification MOS transistor; and a memory block for storing data for controlling the output voltage of the source follower circuit The source follower circuit includes an amplification MOS transistor and an amplification M
A memory cell array having a resistor array composed of a plurality of resistors connected in series to the source of the OS transistor and a MOS transistor connected in parallel to each resistor, and wherein the memory block has a read-only nonvolatile memory element which can be electrically written only once. A data read control circuit for controlling reading of information from the memory cell array, and a data latch circuit. 3. A photoelectric conversion element for generating a photoelectric charge according to an amount of incident light; a charge storage unit for storing the photoelectric charge generated by the photoelectric conversion element; a reset switch for initializing a potential of the charge storage unit; A source follower circuit for generating an output signal corresponding to the potential of the charge storage unit by using the potential of the charge storage unit as an input to the gate electrode of the amplification MOS transistor; and a memory block for storing data for controlling the output voltage of the source follower circuit The source follower circuit includes an amplification MOS transistor and an amplification M
The memory block has a resistor array including a plurality of resistors connected in series to the source of the OS transistor and MOS transistors connected in parallel to each resistor. A memory cell array including a memory cell having a terminal for supplying a write voltage, a resistor for comparing a resistance value, a data read control circuit for controlling reading of information from the memory cell array, and a data latch circuit. A semiconductor device characterized by the above-mentioned.