JPH11330874A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS operational amplifier, whose offset can be canceled by adding a relatively simple circuit, and to attain miniaturization and reduction in power of an amplifier using the CMOS operational amplifier as a basic constituent element and of radio communication equipment including the CMOS operational amplifier. SOLUTION: An amplifier, included in ratio communication equipment which uses a CMOS operational amplifier as a basic constituent element, is provided with a level holding means, constituted of a capacity C1 at an inversion input terminal IN-side of the CMOS operation amplifier, and a switch S1 for selectively transmitting an input signal VIN or the ground potential of the circuit to a non-inverted input terminal IN+ and a switch S2 for selectively connecting a non-inverted output terminal OUT with an output terminal VOUT of the circuit or with its inverted input terminal IN-. The CMOS operation amplifier is selectively turned into a voltage follower configuration, and a level equivalent to the offset cancellation amount of the CMOS operation amplifier is learned and written in the capacity C1 which constitutes the level holding means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an amplifier having a CMOS (complementary MOS) operational amplifier (operational amplifier) as a basic constituent element and an effective offset canceling method. It is about technology.

[0002]

2. Description of the Related Art A differential MOSFET (metal oxide semiconductor type field effect transistor; in this specification, a MOSFET)
(Hereinafter referred to as an insulated gate field effect transistor). Also, C
There is an amplifier using a MOS operational amplifier as a basic component,
There is a wireless communication device including a plurality of stages of amplifier circuits.

[0003]

In recent years, high integration and low power of semiconductor integrated circuits have been remarkable. In particular, high integration and low power technologies in CMOS circuits contribute to miniaturization and low power of wireless communication devices. The place to do is big. However, prior to the present invention, the present inventors have faced the following problems in attempting to employ an amplifier having a CMOS operational amplifier as a basic component element in all amplifier circuits including a first-stage amplifier circuit of a certain wireless communication device. .

That is, the amplifier includes a CMOS operational amplifier centered on a pair of N-channel type differential MOSFETs N1 and N2 as illustrated in FIG. As is well known, the CMOS operational amplifier has an input offset due to variations in threshold voltages of the differential MOSFETs N1 and N2, as exemplified by a dotted line in FIG. , An output offset resulting from multiplying the input offset −Vos by the DC gain Ga is generated. This output offset causes a large offset in the latter-stage amplifier circuit when, for example, a CMOS operational amplifier is employed in a first-stage amplifier circuit of a wireless communication device that handles a small signal, and in some cases, its operation region deviates from the linear region. To the clip state. For this reason, a bipolar transistor type operational amplifier having a small offset is often used in a first-stage amplifier circuit or the like of a wireless communication device, which restricts miniaturization and low power of the wireless communication device.

On the other hand, some methods for canceling the offset of a CMOS operational amplifier have been proposed. In a so-called time-discrete system, such as a switched capacitor, which operates synchronously according to a predetermined clock signal, the clock signal is not used. It is possible to easily learn the offset canceling amount during the invalid level and cancel the offset. However, in a so-called temporally continuous system that does not perform a synchronous operation according to a clock signal, there is no time margin for learning the amount of offset cancellation, and for example, a device that handles a small-amplitude signal such as a first-stage amplifier circuit of a wireless communication device. In order to replace this with a system that is discrete in time, a system with an extremely large order is needed, especially when trying to obtain a sufficient S / N.

An object of the present invention is to provide a CMOS operational amplifier which can cancel the offset by adding a relatively simple circuit. Another object of the present invention is
An object of the present invention is to promote miniaturization and low power of an amplifier having a CMOS operational amplifier as a basic constituent element and a wireless communication device including a plurality of stages of amplifier circuits.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, the CM included in the wireless communication device or the like
In an amplifier having an OS operational amplifier as a basic constituent element,
A level holding means comprising a capacitor or the like is provided on the inverting input terminal side of the CMOS operational amplifier, and a first signal for selectively transmitting an input signal or the ground potential of the circuit to the non-inverting input terminal.
And a second switch means for selectively connecting the non-inverted output terminal thereof to the output terminal of the circuit or the inverted input terminal thereof. Is written to the level holding means.

According to the above-mentioned means, the first and second switch means are selectively switched according to, for example, a clock signal in a time-discrete system, and the amplifier is in a power-down state in a time-continuous system. Switch to select the required amount of offset cancellation,
The offset of the CMOS operational amplifier can be offset. As a result, the offset of an amplifier having a CMOS operational amplifier as a basic constituent element can be eliminated, and the CMO of a wireless communication device or the like including its first-stage amplifier circuit can be eliminated.
S can be promoted, and the size and power consumption can be reduced.

[0010]

FIG. 1 is a circuit diagram of a first embodiment of an amplifier to which the present invention is applied, and FIG. 2 is a signal waveform diagram of the first embodiment. . With reference to these figures, the configuration and operation of the amplifier of this embodiment and the characteristics thereof will be described. Although not particularly limited, the amplifier of this embodiment is mounted on a wireless communication device including a plurality of stages of amplifier circuits, and becomes a basic circuit of each stage amplifier circuit including the first stage amplifier circuit. Each circuit element in FIG. 1 is a known MOS element together with other circuit elements constituting the wireless communication device.
It is formed on a single semiconductor substrate such as single crystal silicon by a manufacturing technology of the FET integrated circuit. In the following circuit diagrams, the MOSFETs whose channel (back gate) portions are indicated by arrows are P-channel type,
It is shown differently from an N-channel MOSFET without an arrow.

In FIG. 1, the amplifier of this embodiment has N
It includes a pair of channel type differential MOSFETs N1 and N2. The drains of these differential MOSFETs are a pair of mirrored P-channel load MOSFETs.
It is coupled via P1 and P2 to the high-potential power supply voltage, that is, the power supply voltage VDD, and its commonly coupled source is coupled via the N-channel MOSFET N3 to the low-potential power supply voltage, that is, the power supply voltage VSS. A predetermined constant voltage VG is supplied to the gate of the MOSFET N3. Thereby, the MOSFET N3 is a so-called current source MOSFET.
And the differential MOSFETs N1 and N2 are the load MOSFETs P1 and P2 and the current source MOSFETs.
Together with N3, one differential amplifier circuit is formed. In addition,
The power supply voltage VDD is not particularly limited, but may be +2.0 V
(Volts) and the power supply voltage VSS is
A negative potential such as -2.0V is used.

The drain of the differential MOSFET N2 serving as a non-inverting output terminal of the differential amplifier circuit is a P-channel MOSF
It is coupled to the gate of ETP3. This MOSFET P3
Is coupled to the power supply voltage VDD, and its drain is connected to the power supply voltage VN through an N-channel MOSFET N4.
It is coupled to SS and to a second terminal of a switch S2 (second switch means). The switch S
2 is a first terminal that is selectively connected to the second terminal when it is off, and a third terminal that is selectively connected to the second terminal when it is on. Is provided. The constant voltage VG is supplied to the gate of the MOSFET N4.

As a result, the MOSFET N4 is connected to the current source M
Acting as an OSFET, the MOSFET P3 forms one source follower type output circuit together with the current source MOSFET N4. The source follower type output circuit constitutes one CMOS operational amplifier together with the differential amplifier circuit including the differential MOSFETs N1 and N2. Further, the gates of the differential MOSFETs N1 and N2 forming the differential amplifier circuit are respectively coupled to the non-inverting input terminal IN + or the inverting input terminal IN− of the CMOS operational amplifier,
MOSFET P3 constituting a source follower type output circuit
Is the non-inverting output terminal O of the CMOS operational amplifier.
Coupled to the UT.

The amplifier further has a second terminal CMO.
It includes another switch S1 (first switch means) coupled to the non-inverting input terminal IN + of the S operational amplifier. The switch S1 has a first terminal selectively connected to the second terminal when the switch S2 is off and a second terminal selectively when the switch S1 is on. A third terminal in a connected state. The first terminal of the switch S1 is connected to the input terminal VIN of the circuit or amplifier.
And its third terminal is connected to the circuit ground potential,
V. Also, a first terminal of the switch S2 is coupled to the output terminal VOUT of the circuit or amplifier, and a third terminal thereof is coupled to the inverting input terminal IN- of the CMOS operational amplifier. CMOS operational amplifier inverting input terminal IN-
A capacitor C1 serving as a level holding means is coupled between the capacitor C1 and the ground potential of the circuit.

In this embodiment, the switches S1 and S
2 is, for example, P-channel and N-channel MOSFE
T comprises a transfer gate or the like in which T is connected in parallel, and is periodically turned on according to, for example, a predetermined clock signal. That is, in this embodiment, the wireless communication device including the amplifier is a so-called time-discrete system,
While the clock signal is at a valid level, it is selectively activated. The switches S1 and S2 are selectively turned on while the clock signal is at an invalid level, that is, while the wireless communication device is in an inactive state. Needless to say, it is desirable that the time constant including the leakage path of the capacitor C1 serving as the level holding means is sufficiently larger than the cycle of the clock signal.

When the wireless communication device is activated and the switches S1 and S2 are turned off, a predetermined input signal is supplied to the input terminal VIN of the amplifier from a preceding circuit (not shown) of the wireless communication device. This input signal is transmitted to the non-inverting input terminal IN + of the CMOS operational amplifier via the switch S1, that is, to the gate of the differential MOSFET N2, and is amplified by the AC gain of the CMOS operational amplifier.
The non-inverted output signal of the CMOS operational amplifier is output from the drain of the MOSFET P3, and is transmitted from the switch S2 to a subsequent-stage amplifier circuit (not shown) via the output terminal VOUT.

On the other hand, the wireless communication device is brought into a non-operation state,
When the switches S1 and S2 are turned on, in the amplifier, the non-inverting input terminal IN + of the CMOS operational amplifier is connected to the circuit ground potential via the switch S1, and the non-inverting output terminal OUT is connected via the switch S2. It is connected to its inverting input terminal IN-. Thereby, the CMOS operational amplifier is in a so-called voltage follower form,
The DC gain Ga is 1. As mentioned above, CMOS
Between the inverting input terminal IN- of the operational amplifier and the ground potential of the circuit, a capacitor C1 serving as level holding means is coupled.

As is well known, the threshold voltages of the differential MOSFETs N1 and N2 slightly vary due to, for example, the influence of the previous process, and the non-inverting input terminal IN + and the inverting input terminal of the CMOS operational amplifier in the operating state. Terminal IN-
Between them, there is an input offset −Vos as exemplified by the dotted line in FIG. This input offset-Vo
When the cancel processing is not performed, s is amplified by the DC gain Ga times of the CMOS operational amplifier, and then becomes the output offset + Vos × Ga to increase the DC level of the output analog signal. As a result, in some cases, the latter-stage amplifier circuit of the wireless communication device may be in a clipping state and may not operate normally.

However, the amplifier of this embodiment includes the two switches S1 and S2 that are selectively turned on when the wireless communication device is deactivated, as described above. Are turned on to selectively set the voltage follower mode. As described above, the DC gain Ga of the CMOS operational amplifier of the voltage follower type is set to 1. The non-inverting input terminal IN + of the CMOS operational amplifier has
The ground potential of the circuit, that is, 0 V is supplied. Therefore, C
The non-inverting output terminal OUT of the MOS operational amplifier has the configuration shown in FIG.
As shown in (b), an output offset + Vos corresponding to the input offset -Vos is output, and this output offset is written and held in the capacitor C1 as the level holding means, and the inverted input terminal IN of the CMOS operational amplifier is written. Is transmitted to

Needless to say, the absolute value of the potential written to the capacitor C1 corresponds to the input offset -Vos of the CMOS operational amplifier, and has the opposite polarity. As a result, the switches S1 and S2 are turned off, and when the wireless communication device enters the next operation state, as shown by a solid line in FIG. 2A, the non-inverting output terminal OUT of the CMOS operational amplifier is turned off. The output offset is eliminated, and the post-amplifier circuit of the wireless communication device can operate normally without being clipped.

That is, in the amplifier according to this embodiment, so-called offset learning is performed while the wireless communication device is inactive and the switches S1 and S2 are on.
The potential corresponding to the offset cancellation amount is written to the capacitor C1, whereby the offset of the CMOS operational amplifier is eliminated, and the operation of the rear-stage amplifier circuit of the wireless communication device is normalized. In other words, the amplifier of this embodiment can be adopted also in the first-stage amplifier circuit for handling a small signal of the wireless communication device although the CMOS operational amplifier is used as a basic constituent element. It is possible to promote the use of CMOS and to reduce the size and power consumption.

FIG. 3 is a circuit diagram showing a second embodiment of the amplifier to which the present invention is applied. This embodiment basically follows the embodiment shown in FIGS. 1 and 2 and, therefore, a description will be added only for parts different from this.

In FIG. 3, the amplifier of this embodiment has a basic configuration of a CMOS operational amplifier centered on differential MOSFETs N1 and N2 and a P-channel MOSFET P3.
, An N-channel type current source MOSFET N3 and N4, and switches S1 and S2 for offset learning.

The amplifier of this embodiment further includes a switch S3 (third switch means) for selectively transmitting a predetermined constant voltage VG to the gates of the current source MOSFETs N3 and N4.
And a resistor R1 (resistor) and a capacitor C2 (capacitor) provided in parallel between the gates of these current source MOSFETs and the ground potential of the circuit.

In this embodiment, the radio communication apparatus including the amplifier is a so-called temporally continuous system that operates asynchronously, but has a power down mode for reducing power consumption, and has a receiving section including the amplifier. The operation is selectively stopped when the wireless communication device itself is not in an operation state or in a transmission state. The switch S3 is turned on, ie, connected, when the wireless communication device is in a normal operation state, and is turned off, ie, disconnected, when put into a power-down mode. The switches S1 and S2 are turned off when the wireless communication device is in a normal operation state, that is, the first terminal and the second terminal are connected, and temporarily turned on at the beginning of the power down mode. The state, that is, the second terminal and the third terminal are connected.

When the wireless communication apparatus is in a normal operation state, the gates of the current source MOSFETs N3 and N4 are supplied with the constant voltage VG via the switch S3 which is in the ON state. The central CMOS operational amplifier receives an operation current and enters an operation state. The non-inverting input terminal IN + of the CMOS operational amplifier
Is supplied with a predetermined input signal from the input terminal VIN of the circuit via the switch S1. This input signal is amplified by the AC gain of the operational amplifier, transmitted to the non-inverted output terminal OUT of the CMOS operational amplifier, and further transmitted to the subsequent amplifier circuit (not shown) via the switch S2 and the output terminal VOUT of the circuit.

Next, when the radio communication device is set to the power down mode, the amplifier first turns on the switches S1 and S2 temporarily for a predetermined period, and the switch S3 sets the radio communication device to the power down mode. During this time, it is constantly turned off. Therefore, the current source MOSFET N
3 and N4 continue to operate as a current source for a period corresponding to the product of the resistance value of the resistor R1 and the capacitance value of the capacitor C2, that is, a time period according to the time constant. Does not act as a source. Further, the CMOS operational amplifier is in a voltage follower form only while the switches S1 and S2 are turned on, and is in an offset learning state. As described above, this offset learning result is written and held in the capacitor C1 as an offset canceling amount, and the inversion input terminal I of the CMOS operational amplifier is used.
N- and transmitted to the offset cancel. As a result, in this embodiment, the offset of the amplifier can be reduced despite the fact that the wireless communication apparatus including the amplifier is a temporally continuous system. The use of a CMOS device can be promoted, and its size and power consumption can be reduced.

The functions and effects obtained from the above embodiment are as follows. That is, (1) In an amplifier or the like included in a wireless communication device or the like and having a CMOS operational amplifier as a basic constituent element, a level holding means including a capacitor or the like is provided on the inverting input terminal side of the CMOS operational amplifier, and an input is provided to a non-inverting input terminal thereof. A first switch means for selectively transmitting a signal or a ground potential of a circuit, and a second switch means for selectively connecting a non-inverted output terminal thereof to an output terminal of the circuit or an inverted input terminal thereof; By selectively setting the operational amplifier in a voltage follower form and writing a level corresponding to the offset cancellation amount to the level holding means, the first and second operational amplifiers can be used.
Is selectively switched according to, for example, a clock signal in a system that is discrete in time, and is selectively switched while the amplifier is in a power-down state in a system that is temporally continuous, for example, to obtain a necessary offset canceling amount. And the offset of the CMOS operational amplifier can be offset.

(2) According to the above item (1), an effect that an offset of an amplifier having a CMOS operational amplifier as a basic component can be eliminated can be obtained. (3) According to the above items (1) and (2), the use of CMOS in a wireless communication device or the like including a plurality of stages of amplifier circuits, including the first stage amplifier circuit, is promoted, and its size and power consumption are reduced. The effect that it can be obtained is obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1 and FIG. 3, the level holding means provided on the inverting input terminal IN− side of the CMOS operational amplifier can be replaced with means other than the capacitance. Further, the switches S1 and S2 may be temporarily turned on immediately before the invalid level of the clock signal ends or immediately before the power down mode ends. Further, in these embodiments, the capacitance C is connected to the inverting input terminal IN- of the CMOS operational amplifier.
1 are coupled, so that the input signal cannot be a so-called complementary signal.
This can be dealt with by configuring a CMOS operational amplifier centering on. CMOS operational amplifier, specific circuit configuration of amplifier, polarity and absolute value of power supply voltage, and MOS
The conductivity type of the FET and the like can take various embodiments.

In FIG. 2, the specific polarity and absolute value of the input offset and the output offset, and the signal waveforms of the input signal and the output signal are merely examples for explaining the gist of the present invention. Does not impose any restrictions.

In the above description, the case where the invention made by the present inventor is mainly applied to a wireless communication apparatus having a plurality of stages of amplifying circuits or an amplifier thereof, which is a field of use, has been described. However, the present invention can be applied to, for example, a single amplifier formed as an amplifier or various analog integrated circuits or digital integrated circuits including similar amplifiers. INDUSTRIAL APPLICABILITY The present invention is widely applicable to at least a semiconductor integrated circuit device including an amplifier having a CMOS operational amplifier as a basic constituent element, and a device or system including such a semiconductor integrated circuit device.

[0033]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, C included in a wireless communication device or the like
In an amplifier having a MOS operational amplifier as a basic constituent element, a level maintaining means including a capacitor or the like is provided on an inverting input terminal side of a CMOS operational amplifier, and an input signal or a ground potential of a circuit is selectively transmitted to a non-inverting input terminal thereof. 1 switch means and second switch means for selectively connecting the non-inverting output terminal thereof to the output terminal of the circuit or the inverting input terminal thereof. By writing the level corresponding to the quantity into the level holding means, the first and second switch means are selectively switched according to, for example, a clock signal in a time discrete system.
In a system that is temporally continuous, for example, it is possible to selectively switch while the amplifier is in a power-down state, learn the necessary amount of offset cancellation, and cancel the offset of the CMOS operational amplifier. As a result, CMOS
It is possible to eliminate the offset of an amplifier having an operational amplifier as a basic constituent element, to promote the use of CMOS in a wireless communication device and the like including its first-stage amplifier circuit, and to reduce the size and power consumption thereof.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an amplifier to which the present invention is applied.

FIG. 2 is a signal waveform diagram showing one embodiment of the amplifier of FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the amplifier to which the present invention is applied.

FIG. 4 is a circuit diagram showing an example of a conventional amplifier using an operational amplifier as a basic element.

[Explanation of symbols]

VIN: Input signal or input terminal of amplifier, IN +:
Non-inverting input signal or non-inverting input terminal of CMOS operational amplifier, IN -... inverting input signal or inverting input terminal of CMOS operational amplifier, OUT ... non-inverting output signal or non-inverting output terminal of CMOS operational amplifier, VOUT ... output of amplifier Signal or output terminal, VG: constant voltage, VDD: high-potential power supply voltage, VSS: low-potential power supply voltage. Vos ...
… Offset voltage, Ga… Amplifier DC gain. P1 to P
3 P-channel MOSFET, N1 to N4 N-channel MOSFET, S1 to S3 Switch, C1
.About.C2... Capacity, R1.

Claims (6)

[Claims] An amplifier comprising an operational amplifier and a level holding means provided on an inverting input terminal side of the operational amplifier, wherein the operational amplifier is selectively in a voltage follower form, and a non-inverting input thereof is provided. A semiconductor integrated circuit device, wherein a level corresponding to the offset cancellation amount of the operational amplifier is written to the level holding means by transmitting a circuit ground potential to a terminal. 2. The amplifier according to claim 1, wherein the amplifier includes a first switch for selectively transmitting an input signal or a ground potential of a circuit to a non-inverting input terminal of the operational amplifier, and a non-inverting output terminal of the operational amplifier. A second terminal selectively connected to the output terminal of the circuit or its inverting input terminal
And a switch means. 3. The amplifier according to claim 1, wherein the amplifier has a power-down mode, and wherein the first and second switch means operate in the power-down mode or at the beginning or end thereof. A semiconductor integrated circuit device for transmitting a ground potential of a circuit to a non-inverting input terminal of the operational amplifier, or connecting a non-inverting output terminal of the operational amplifier to the inverting input terminal. 4. The operational amplifier according to claim 3, wherein the operational amplifier comprises: a differential MOSFET;
A current source MOSFET provided between a common-coupled source of the SFET and a low potential side power supply voltage, wherein the amplifier applies a predetermined constant voltage to a gate of the current source MOSFET in a normal mode. Third to selectively communicate
And a resistance means and a capacitance means provided in parallel between the gate of the current source MOSFET and the low potential side power supply voltage. 5. The semiconductor integrated circuit device according to claim 1, wherein the amplifier constitutes a first-stage amplifier circuit of a predetermined wireless communication device. . 6. An amplifier comprising an operational amplifier and an amplifier having a power down mode, the amplifier including a level holding means provided on an inverting input terminal side of the operational amplifier, and the amplifier being in a power down mode. Wherein the offset canceling amount of the operational amplifier is measured and written to the level holding means.