JP4561096B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and can be applied to, for example, a display device using an organic EL (Electro Luminescence) element. In the configuration in which a light emitting element is driven by a transistor having a source follower circuit configuration by a gate source voltage based on a voltage between terminals of a signal level holding capacitor, the present invention biases the gate electrode of the transistor toward the source side, thereby In a configuration in which a light emitting element is driven by a transistor having a source follower circuit configuration by a gate source voltage based on a voltage between terminals of a holding capacitor, it is possible to prevent a decrease in luminance level and reliably correct a change with time of the light emitting element. To.

  Conventionally, in organic EL display devices, various applications to display devices have been proposed, for example, in US Pat. No. 5,684,365 and JP-A-8-234683.

  That is, as shown in FIG. 9, in this type of display device 1, the pixel unit 2 has scanning lines SCN provided in a horizontal direction in units of lines with respect to pixels (PX) 3 arranged in a matrix. A signal line SIG is provided in the vertical direction for each column so as to be orthogonal to the scanning line SCN. For the pixel unit 2 formed in this way, the display device 1 drives the scanning lines SCN by the vertical drive circuit 4 to sequentially drive the pixels 3 of the pixel unit 2 in units of lines. The gray level of each pixel 3 is set by driving the signal line SIG by the horizontal drive circuit 5 so as to correspond to the above driving.

  In the organic EL display device, each pixel 3 driven in this manner includes an organic EL element that is a self-luminous element driven by current driving, and a driving circuit (hereinafter referred to as a pixel driving circuit) that drives the organic EL element. (Referred to as a pixel circuit).

  For this reason, the vertical drive circuit 4 generates a write signal ws for sequentially instructing writing to each pixel 3 in line units by the write scan circuit (WSCN) 4A, and outputs the write signal ws to the scan line SCN. The setting of gradation in the pixel 3 is controlled. The horizontal drive circuit 5 generates a drive signal in accordance with the gradation data D1 indicating the gradation of each pixel 3, distributes this drive signal to each signal line SIG by the horizontal selector (HSEL) 5A, and outputs it. Thus, the display device 1 is configured to set the gradation of each pixel 3 in line units.

  In the display device thus formed, each pixel circuit is formed by an n-channel MOS type TFT (Thin Film Transistor), and the anode of the organic EL element is connected to the transistor. By driving with current, an organic EL element and a pixel circuit can be integrally formed on a glass substrate by applying an amorphous silicon process. As a result, as shown in FIG. It is conceivable to drive the element 12.

  That is, the display device 11 shown in FIG. 10 is formed in each pixel 3 so that the organic EL element 12 is current-driven by the transistor TR2 having a source follower circuit configuration in which the source is connected to the anode of the organic EL element 12. A signal level holding capacitor C1 is provided at the gate of the transistor TR2. The signal level holding capacitor C1 has one end connected to the gate of the transistor TR2 and the other end set to a predetermined reference voltage. In the example shown in FIG. 10, this reference voltage is set to the power supply voltage Vcc. Is done. The display device 11 outputs the write signal ws from the write scan circuit 4A provided in the vertical drive circuit 4, and this signal level holding capacitor C1 by the switch circuit by the transistor TR1 that is turned on by the write signal ws. Is connected to the signal line SIG, whereby the gate voltage Vg of the transistor TR2 is set according to the signal level of the drive signal output to the signal line SIG in response to the write signal ws. As a result, the display device 11 drives the organic EL element 12 with a current corresponding to the gate voltage Vg set in this way, and emits the organic EL element 12 of each pixel 3 with a gradation corresponding to the gradation data D1. Thus, a desired image can be displayed.

  However, in an organic EL element, as shown in FIG. 11, the current-voltage characteristics change in a direction in which current hardly flows by use. In FIG. 11 and FIG. 12, the symbol L1 indicates the initial characteristics, and the symbol L2 indicates the characteristics due to changes over time. On the other hand, in the driving by the sofa follower circuit described above with reference to FIG. 10, the characteristic curve due to the load intersects the characteristic curve of the drain-source voltage Vds−drain source current Ids of the transistor TR2, as shown in FIG. The intersecting point becomes the operating point. Accordingly, in the organic EL element, when the voltage-current characteristic is changed, the current flowing through the organic EL element is reduced correspondingly, thereby causing a problem that the luminance of each pixel is gradually lowered.

  As one method for solving this problem, a method of controlling the drive current of the organic EL element 12 by setting the gradation by the gate-source voltage Vgs instead of such a simple gradation setting by the gate voltage Vg can be considered. . In other words, the drain current Ids of the TFT is expressed by the following equation, whereby it is possible to prevent a change in drive current due to a change with time by setting a gradation by the gate-source voltage Vgs. Here, μ is the carrier mobility, W is the gate width, L is the gate length, Cox is the gate capacitance per unit area, and Vth is the threshold voltage.

これにより図１０との対比により図１３に示すように、各画素２３において、トランジスタＴＲ２のゲートに対する信号レベル保持用のコンデンサＣ１の配置に代えて、このトランジスタＴＲ２のゲートソース間に信号レベル保持用のコンデンサＣ２を配置し、この信号レベル保持用のコンデンサＣ２に信号線ＳＩＧの信号レベルを設定する。またドライブスキャン信号ｄｓ１によりオン動作するトランジスタＴＲ３をトランジスタＴＲ２のソースに接続し、信号レベル保持用のコンデンサＣ２に信号線ＳＩＧの信号レベルを設定する期間の間、このトランジスタＴＲ３によりトランジスタＴＲ２のソース電位を一定電位に設定する。これにより画素２３においては、発光素子である有機ＥＬ素子１２の発光、非発光を制御する発光制御用のスイッチ回路をトランジスタＴＲ３により構成する。なお図１３においては、この一定電位がアース電位の場合である。

Accordingly, as shown in FIG. 13 in comparison with FIG. 10, in each pixel 23, instead of disposing the signal level holding capacitor C1 with respect to the gate of the transistor TR2, a signal level holding signal is provided between the gate and source of the transistor TR2. The capacitor C2 is disposed, and the signal level of the signal line SIG is set in the signal level holding capacitor C2. Further, the transistor TR3 that is turned on by the drive scan signal ds1 is connected to the source of the transistor TR2, and during the period in which the signal level of the signal line SIG is set in the signal level holding capacitor C2, the transistor TR3 causes the source potential of the transistor TR2 to be set. Is set to a constant potential. Accordingly, in the pixel 23, a switch circuit for light emission control for controlling light emission and non-light emission of the organic EL element 12 which is a light emitting element is configured by the transistor TR3. In FIG. 13, this constant potential is a ground potential.

  Corresponding to the configuration of the pixel portion 22 by such pixels 23, in the vertical drive circuit 24, in addition to the write scan circuit 24A, a drive scan signal is synchronized with the output of the write signal ws by the write scan circuit 24A. A drive scan circuit (DSCN) 24B for outputting ds1 is provided, and in the horizontal drive circuit 25, a drive signal is generated in accordance with gradation data D1 indicating the gradation of each pixel, and is output from the horizontal selector 25A.

  As a result, as shown in FIGS. 14 and 15, in the display device 21, the organic EL element 12 is driven by the transistor TR2 by the gate-source voltage Vgs based on the voltage across the terminals of the signal level holding capacitor C2, and the drive scan signal Light emission and non-light emission of the organic EL element 12 are controlled by the on / off operation of the transistor TR3 by ds1. The transistor TR3 sets the gate side end of the signal level holding capacitor C2 to the signal level Vin of the signal line SIG while the transistor TR3 sets the source side end of the signal level holding capacitor C2 to the ground potential. . 15A to 15D show connections of the pixels 23 corresponding to the periods TA to TD in FIG.

  In this way, if the drive current of the organic EL element 12 is controlled by setting the gradation based on the gate-source voltage Vgs, even if the characteristics of the organic EL element 12 change, the constant current determined by the gradation data is used. Accordingly, it is possible to effectively avoid degradation of image quality due to changes over time. As a result, a pixel portion can be created by a TFT made of amorphous silicon and a high-quality image can be displayed.

  On the other hand, in the TFT made of amorphous silicon, the bottom gate method is widely applied, and in this bottom gate method, two kinds of device structures of a channel etch type and a channel stopper type are widely applied. ing.

  Here, in the channel etch type TFT, a cross section is taken in a direction crossing the source and drain, and as shown in FIG. 16, a gate electrode 42 is formed in a rectangular shape on the substrate 41, for example, and covers the gate electrode 42. A gate oxide film 43 is formed. Further, on this gate oxide film 43, an amorphous silicon film 44 and an amorphous silicon film 45 doped with n-type impurities are sequentially deposited to form a drain electrode 46 and a source electrode 47. In the channel etch type TFT, the drain electrode 46 and the source electrode 47 are formed at a predetermined interval, and a channel region is formed between the drain electrode 46 and the source electrode 47. Further, in the direction crossing the source / drain, the drain electrode 46 and the source electrode 47 are formed so that the center of the gate electrode 42 becomes the center of the channel region, whereby the drain electrode 46 and the gate electrode 42 overlap each other. The area of the part and the area of the part where the source electrode 47 and the gate electrode 42 overlap are formed so as to be substantially equal.

  On the other hand, the channel stopper type TFT is similarly doped with a gate electrode 42, a gate oxide film 43, an amorphous silicon film 44, and an n-type impurity on the substrate 41 as shown in FIG. 17 in comparison with FIG. After the amorphous silicon films 45 are sequentially deposited, an insulating layer 48 is formed in the channel region, and then a drain electrode 46 and a source electrode 47 are formed. Also in the channel etch type TFT, the drain electrode 46 and the source electrode 47 are formed so that the center of the gate electrode 42 becomes the center of the channel region in the direction crossing the source / drain. The area of the portion where the gate electrode 42 overlaps and the area of the portion where the source electrode 47 and the gate electrode 42 overlap are formed to be substantially equal.

  By the way, in the pixel 23 described above with reference to FIG. 13, when the transistor TR3 is set to the OFF state as shown in FIG. 18 in comparison with FIG. 14, the gate source by the inter-terminal voltage set in the signal level holding capacitor C2 is set. When the transistor TR2 drives the organic EL element 12 by the voltage Vgs and, for example, the gradation used for driving the organic EL element 12 is a gradation that causes the organic EL element 12 to emit light, the source voltage Vs of the transistor TR2 gradually increases. To rise. Further, the gate voltage of the transistor TR2 also rises in conjunction with the rise of the source voltage Vs, whereby the gate-source voltage Vgs of the transistor TR2 should be held at a voltage set by the signal level of the signal line SIG. is there.

  However, in practice, due to the parasitic capacitances of the transistors TR1 and TR2, the gate-source voltage Vgs of the transistor TR2 increases as the drive current of the organic EL element 12 increases and the source voltage Vs increases. It will be lower than the source-to-source voltage Vgs. That is, as shown in FIG. 19, in the transistor T2 according to the configuration of FIG. 13, the parasitic capacitance Cpgs between the gate and source of the transistor TR2, the parasitic capacitance Cpgd between the gate and drain of the transistor TR2, and the parasitic between the gate and source of the transistor TR1. Since the capacitance Cpws is interposed in the gate line of the transistor TR2, the voltage increase ΔVg of the gate voltage Vg with respect to the voltage increase ΔVs of the source voltage Vs is equal to the parasitic capacitances Cpgs and Cpgd as shown by the following equation. , Cpws, and capacitance division by the capacitance Cs of the signal holding capacitor C2.

この（３）式を整理すると、次式により表すことができる。

If this formula (3) is arranged, it can be expressed by the following formula.

ここで信号レベル保持用のコンデンサＣ２への信号線ＳＩＧの信号レベルＶｉｎの設定時にあっては、ソース間電圧Ｖｇｓを次式により表すことができる。

Here, when the signal level Vin of the signal line SIG is set to the signal level holding capacitor C2, the source-to-source voltage Vgs can be expressed by the following equation.

これに対して有機ＥＬ素子１２の駆動を開始した後のゲート電圧Ｖ’ｇにあっては、（３）式の利得ｇを用いてｇ・ΔＶｓにより表し得ることにより、このときのゲートソース間電圧Ｖ’ｇｓは、次式により表すことができる。

On the other hand, the gate voltage V′g after the driving of the organic EL element 12 is started can be expressed by g · ΔVs using the gain g of the equation (3). The voltage V′gs can be expressed by the following equation.

これにより図１３に係る構成においては、ソース電圧Ｖｓの電圧上昇に対してゲート電圧Ｖｇの電圧上昇が十分に追従できないことが判る。

Accordingly, it can be seen that the increase in the gate voltage Vg cannot sufficiently follow the increase in the source voltage Vs in the configuration according to FIG.

  On the other hand, in the configuration shown in FIG. 13, in the signal line transistor TR1, since it is necessary to reduce the leakage current, the transistor TR1 is generally made small, whereby the parasitic capacitance of the transistor TR1. In Cpws, the influence on the decrease in the gate-source voltage Vgs due to the increase in the source voltage Vs is small. However, in the transistor TR2, since the organic EL element 12 needs to be driven by current, the shape becomes large, thereby increasing the parasitic capacitances Cpgs and Cpgd. This greatly affects the decrease in the voltage Vgs.

  Thus, when the gate source voltage Vgs of the transistor TR2 decreases due to the increase in the source voltage Vs, the luminance level of the pixel in the display device eventually decreases.

Further, in the organic EL element 12, even when the terminal voltage of the signal level holding capacitor C2 is set by the same signal level Vin by changing with time in a direction in which the current hardly flows as described above with reference to FIG. In the case where it is difficult for the current to flow due to the change over time, the voltage increase ΔVs of the source voltage Vs increases accordingly. Thus, when the voltage increase ΔVs of the source voltage Vs is increased, the gate-source voltage Vgs of the transistor TR2 is decreased by the corresponding amount from the equation (5), thereby reducing the driving current of the organic EL element 12 and sufficiently organic EL. The change with time of the element 12 cannot be corrected.
USP 5,684,365 JP-A-8-234683

  The present invention has been made in consideration of the above points. In a configuration in which a light emitting element is driven by a transistor having a source follower circuit configuration by a gate source voltage by a voltage between terminals of a signal level holding capacitor, the luminance level is reduced. An object of the present invention is to propose a display device that can prevent and surely correct a change with time of a light emitting element.

  In order to solve such a problem, in the invention of claim 1, the pixel is applied to a display device having a pixel portion in which pixels driven by current drive are arranged in a matrix and a drive circuit for driving the pixel portion. A driving transistor by a source follower circuit that holds a signal level holding capacitor between a light emitting element and a gate source and drives the light emitting element by a gate-source voltage by a voltage between terminals of the signal level holding capacitor, and driving A signal line transistor for connecting the gate of the transistor for the signal line to the signal line, and a light emission control switch circuit for stopping the light emission of the light emitting element, and the drive circuit of the light emitting element by the light emission control switch circuit After the light emission is stopped, the signal level holding capacitor is driven by the signal level of the signal line by driving the signal transistor. Set the terminal voltage of the sub, the transistor for driving, so that the gate electrode is formed deviated to the source electrode side.

  According to a fifth aspect of the present invention, in a display device in which pixels driven by current are arranged in a matrix, the pixel holds a signal level holding capacitor between the light emitting element and the gate source, and the signal level holding The transistor for driving by the source follower circuit that drives the light emitting element by the voltage between the gate and the source due to the voltage between the terminals of the capacitor and the gate of the transistor for driving are connected to the signal line, and the voltage between the terminals of the capacitor for holding the signal level For light emission control that stops light emission of the light emitting element during the period when the terminal voltage of the signal level transistor is set by the signal line transistor and the signal line holding capacitor is set by the signal line signal level. The switching transistor has a gate electrode biased toward the source electrode side. Made is set to be in.

  In the invention of claim 8, the pixel is applied to a display device in which pixels of organic EL elements are arranged in a matrix, and the pixel holds a signal level holding capacitor between the organic EL element and the gate source. A transistor for driving by a source follower circuit for driving an organic EL element by a gate-source voltage by a voltage between terminals of a signal level holding capacitor and a gate of the driving transistor are connected to a signal line to hold the signal level. The signal line transistor for setting the voltage between the terminals of the capacitor according to the signal level of the signal line, and the period for which the terminal voltage of the signal level holding capacitor is set by the signal line transistor A light emission control switch circuit that stops light emission. It formed deviated to scan electrode side set to be in.

  According to the configuration of claim 1, the pixel is applied between a light emitting element and a gate source when applied to a display device having a pixel portion in which pixels driven by current are arranged in a matrix and a driving circuit for driving the pixel portion. The signal level holding capacitor is held in the gate, and the driving transistor by the source follower circuit that drives the light emitting element by the gate-source voltage by the voltage between the terminals of the signal level holding capacitor and the gate of the driving transistor is signaled. A signal line transistor connected to the line, and a light emission control switch circuit for stopping light emission of the light emitting element, the drive circuit after stopping light emission of the light emitting element by the light emission control switch circuit, By driving the transistor for the signal line, the voltage between the terminals of the capacitor for holding the signal level is set according to the signal level of the signal line, If the gate electrode is formed so as to be biased toward the source electrode side, the light emitting element stops the light emission of the light emitting element and sets the signal level holding capacitor according to the signal level of the signal line. As for the driving transistor that starts emitting light and raises the source voltage, the parasitic capacitance that impairs the rise of the gate voltage according to the rise of the source voltage is reduced, or the capacitance of the signal level holding capacitor is increased. Thus, the rise of the gate voltage according to the rise of the source voltage can be achieved. As a result, in the configuration in which the light emitting element is driven by the transistor having the source follower circuit configuration by the gate source voltage based on the voltage between the terminals of the signal level holding capacitor, the luminance level is prevented from being lowered and the temporal change of the light emitting element is reliably corrected. be able to.

Thus, according to the configurations of claims 5 and 8, in the configuration in which the light emitting element and the organic EL element are driven by the transistor having the source follower circuit configuration by the gate source voltage by the voltage between the terminals of the signal level holding capacitor, It is possible to provide a display device that can prevent a decrease in level and reliably correct a change with time of a light emitting element and an organic EL element .

  According to the present invention, in a configuration in which a light-emitting element and an organic EL element are driven by a transistor having a source follower circuit configuration by a gate-source voltage based on a voltage between terminals of a signal level holding capacitor, a reduction in luminance level is reliably prevented. A change with time of the light emitting element and the organic EL element can be corrected.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 1 is a cross-sectional view showing a transistor applied to a display device according to an embodiment of the present invention in comparison with FIG. In the display device according to this embodiment, except that the transistor TR2 related to driving of the organic EL element and the transistor TR1 connecting the gate of the transistor TR2 to the signal line SIG are formed by the configuration shown in FIG. The same configuration as that of the display device 21 described above with reference to FIG. 13 will be described below by using the configuration of FIG. 13, and a duplicate description will be omitted.

  In this display device, the gate electrode 42 of the transistor TR2 that drives the organic EL element 12 is formed by shifting to the source electrode 47 side, whereby the gate electrode 42 is formed biased toward the source electrode 47 side. ing. As a result, in this transistor TR2, the parasitic capacitance Cpgs between the gate and the source is increased as compared with the conventional case by the amount of biasing the gate electrode 42 toward the source electrode 47, and conversely, between the gate and drain. The parasitic capacitance Cpgd is reduced. As a result, in this display device, the value of the numerator on the right side of equation (3) increases compared to the conventional value, and the denominator value decreases compared to the conventional value. The gate voltage is raised by sufficiently following the rise of the gate voltage, and the change in the gate-source voltage Vgs can be reduced.

  In this display device, the gate electrode 42 of the transistor TR1 that connects the gate of the transistor TR2 that drives the organic EL element 12 to the signal line SIG is shifted to the electrode 47 side opposite to the gate side of the transistor TR2. Thus, the gate electrode 42 is formed so as to be biased toward the electrode 47 side opposite to the gate side of the transistor TR2. As a result, in the signal line transistor TR1, the parasitic capacitance Cpws added to the gate of the transistor TR2 is set to be smaller than that of the conventional one, and this is sufficient to increase the source voltage as compared with the conventional one. The gate voltage is raised by following the above and the change in the gate-source voltage Vgs can be reduced.

  Note that such a shift of the gate electrode 42 can be performed within a range in which the transistors TR1 and TR2 do not impair the functions of the transistors, respectively, and on the drain electrode 46 side, the channel region side end of the drain electrode 46 and the gate electrode It is possible to shift to the extent that the end of the drain electrode 46 side of 42 substantially overlaps.

(2) Operation of Embodiment In the above configuration, the display device 21 (FIG. 13) is configured to apply the signal line SIG to the pixels 23 of the pixel unit 22 in units of lines sequentially by driving the scanning lines SCN and SCN1 by the vertical drive circuit 24. A signal level is set, and each pixel 23 emits light according to the signal level set for each pixel 23 to display a desired image.

  In the display device 21, in each pixel 23, a signal level holding capacitor C2 is provided between the gate and source of the transistor TR2 having a source follower circuit configuration for driving the organic EL element 12 (FIG. 13). The source of the transistor TR2 is set to the ground potential which is a reference voltage, and the gate of the transistor TR2 is connected to the signal line SIG by the switch circuit by the transistor TR1, so that the signal level of the signal line SIG is for holding the signal level. Set to capacitor C2. Further, the organic EL element 12 is driven by the transistor TR2 by the gate-source voltage Vgs by the signal level holding capacitor C2 set in this way.

  Thereby, in this display device 21, even when the characteristics of the organic EL element 12 change with time, the organic EL element 12 can be driven by current driving according to the gradation data D1. Further, the organic EL element 12 can be driven from the anode side by a source follower circuit using an n-channel MOS type TFT.

  That is, in each pixel 23, when the terminal voltage of the signal level holding capacitor C2 is set according to the signal level of the signal line SIG in this way, the connection between the signal line by the transistor TR1 and the gate of the transistor TR2 is disconnected. As a result, the transistor TR3 is switched to the OFF state, whereby the source of the transistor TR2 is disconnected from the ground. As a result, in each pixel 23, driving of the organic EL element 12 by the transistor TR2 is started by the gate source voltage Vgs due to the voltage across the terminals of the signal level holding capacitor C2, and the source voltage Vs of the transistor TR2 rises. Since the gate-source voltage Vgs is held in the signal level holding capacitor C2, the gate voltage Vg of the transistor TR2 also rises in conjunction with the rise in the source voltage Vs.

  However, when the gate voltage Vg rises due to the rise in the source voltage Vs of the transistor TR2, the parasitic capacitance Cpgd between the gate and drain of the transistor TR2 and the signal are accordingly increased by the charge held in the signal level holding capacitor C2. It is necessary to charge the parasitic capacitance Cpws between the gate electrode of the transistor TR1 on the line side and the transistor TR2 side electrode. As a result, as shown in the equation (3), the voltage increase ΔVg of the gate voltage Vg becomes smaller than the voltage increase ΔVs of the source voltage Vs.

  However, in this embodiment, in the transistor TR2, the gate electrode 42 is formed to be biased toward the source electrode 47, so that the parasitic capacitance Cpgd between the gate electrode 42 and the drain electrode 46 is normal. By setting the source voltage Vs to be larger than that of this type of transistor, the amount of charge charged by the signal level holding capacitor C2 can be reduced by the increase of the source voltage Vs. Thus, the gate voltage Vg can be raised with high accuracy and the change in the gate source voltage Vgs of the transistor TR2 can be reduced accordingly.

  Further, since the gate electrode 42 is formed so as to be biased toward the source electrode 47 in this way, the parasitic capacitance Cpgs between the gate electrode 42 and the source electrode 47 is smaller than that of this type of normal transistor. Thus, it is possible to obtain the same effect as when the capacitance of the signal level holding capacitor C2 is increased, thereby causing the gate voltage Vg to accurately follow the increase in the source voltage Vs. Therefore, the change in the gate-source voltage Vgs of the transistor TR2 can be reduced accordingly.

  A similar configuration in which the gate electrode 42 is biased is also applied to the transistor TR1 that connects the signal line SIG to the gate of the transistor TR2, and the parasitic capacitance Cpws between the gate of the transistor TR2 and the scanning line SCN for the write signal ws. The gate voltage Vg can be increased by accurately following the increase of the source voltage Vs, and the gate voltage Vgs of the transistor TR2 can be increased accordingly. Changes can be reduced.

  Thus, in this display device, in the configuration in which the light emitting element is driven by the transistor having the source follower circuit configuration by the gate source voltage by the voltage between the terminals of the signal level holding capacitor, the luminance level is prevented from being lowered and the light emitting element is reliably A change with time can be corrected.

(3) Effects of the embodiment According to the above configuration, in the configuration in which the light emitting element is driven by the transistor having the source follower circuit configuration by the gate source voltage by the voltage between the terminals of the signal level holding capacitor, the gate electrode of this transistor is By biasing toward the source side, it is possible to prevent the luminance level from being lowered and reliably correct the temporal change of the light emitting element.

  Furthermore, for the transistor that connects the signal line to the gate of the transistor TR2, the gate electrode is formed to be biased toward the electrode on the signal line side, thereby further preventing the luminance level from decreasing further and reliably correcting the temporal change of the light emitting element. can do.

  FIG. 2 is a cross-sectional view showing a transistor applied to the display device according to the second embodiment of the present invention in comparison with FIG. In the display device according to this embodiment, the transistor TR2 for driving the organic EL element and the transistor TR1 for connecting the gate of the transistor TR2 to the signal line SIG are formed by the configuration shown in FIG. The same configuration as that of the display device 21 described above with reference to FIG. 13 will be described below by using the configuration of FIG. 13, and a duplicate description will be omitted.

  In this display device, the gate electrode 42 of the transistor TR2 for driving the organic EL element 12 is formed shorter on the drain electrode 46 side than this type of normal transistor. As a result, the transistor TR2 is formed such that the gate length is shortened on the drain electrode 46 side and the gate electrode 42 is biased toward the source electrode 47 side in the channel length direction. Accordingly, in the display device according to this embodiment, the parasitic capacitance Cpgd between the gate and the drain is reduced by that amount, and the value of the denominator on the right side of equation (3) is made smaller than that in the conventional case. Thus, the gate voltage is raised while accurately following the increase in the source voltage Vs, and the change in the gate-source voltage Vgs is reduced.

  In this display device, the gate electrode 42 of the transistor TR2 that drives the organic EL element 12 is connected to the signal line SIG in the same manner. It is formed so as to be biased toward the 47 side. As a result, in the signal line transistor TR1, the parasitic capacitance Cpws added to the gate of the transistor TR2 is set to be smaller than that of the conventional one, and this is sufficient to increase the source voltage as compared with the conventional one. The gate voltage is raised by following the above and the change in the gate-source voltage Vgs can be reduced.

  Even if the gate electrode is biased by shortening the gate length in the channel length direction as in this embodiment, the same effect as in the first embodiment can be obtained.

  FIG. 3 is a cross-sectional view showing a transistor applied to the display device according to the third embodiment of the present invention in comparison with FIG. In the display device according to this embodiment, the transistor TR2 for driving the organic EL element is configured in the same manner as the display device 21 described above with reference to FIG. 13 except that the transistor TR2 is formed by the configuration shown in FIG. Accordingly, in the following description, the configuration of FIG. 13 is used, and redundant description is omitted.

  In this display device, the gate electrode 42 of the transistor TR2 for driving the organic EL element 12 is formed so that the source electrode 47 side extends outward as compared with this type of normal transistor, and the shape of the gate electrode 42 is The gate oxide film 43, the amorphous silicon films 44 and 45, and the source electrode 47 are formed so as to extend outward. As a result, the transistor TR2 is formed so that the gate length is increased on the source electrode 47 side in the channel length direction, and the gate electrode 42 is formed biased toward the source electrode 47 side. The parasitic capacitance Cpgs between the gate and the source is increased, and the value of the numerator on the right side of equation (3) is increased as compared with the conventional one, and the gate voltage is raised by sufficiently following the increase of the source voltage Vs. Thus, changes in the gate-source voltage Vgs can be reduced.

  Even if the gate electrode is biased by increasing the gate length in the channel length direction as in this embodiment, the same effect as in the first embodiment can be obtained.

  FIG. 4 is a connection diagram illustrating a display apparatus according to a fourth embodiment of the present invention in comparison with FIG. In the display device 51, the pixel unit 52 is formed by arranging pixels 53 in a matrix, and the scanning lines SCN, SCN1, and SCN2 are provided in the horizontal direction for these pixels 53 in line units. Further, a signal line SIG is provided in the vertical direction for each column so as to be orthogonal to these scanning lines SCN, SCN1, and SCN2. The display device 51 drives the scanning lines SCN, SCN1, and SCN2 by the vertical drive circuit 54 with respect to the pixel portion 52 formed in this manner, and the operation of the pixel circuit provided in the pixel 53 sequentially in line units. And the signal line SIG is driven by the horizontal drive circuit 55 so as to correspond to the control of the pixel circuit, and the gradation of each pixel 53 is set.

  Therefore, the vertical drive circuit 54 generates a write signal ws for sequentially instructing writing to each pixel 53 line by line by the write scan circuit (WSCN) 54A, and the signal level changes in synchronization with the write signal ws. The drive scan signals ds1 and ds2 are generated by the drive scan circuit (DSCN) 54B and the drive scan circuit (DSCN2) 54C, and the write signal ws and the drive scan signals ds1 and ds2 are output to the scan lines SCN, SCN1 and SCN2. Has been made. In the horizontal drive circuit 55, a drive signal is generated according to the gradation data D1 indicating the gradation of each pixel 53, and this drive signal is distributed to each signal line SIG by the horizontal selector (HSEL) 55A and output. Has been made.

  As shown in FIG. 5, in the pixel 53, a signal level holding capacitor C2 is connected to the gate source of the transistor TR2, and a gate-source voltage Vgs is set by the inter-terminal voltage set in the signal level holding capacitor C2. Thus, the organic EL element 12 is driven by the transistor TR2. Further, on / off control of the transistor TR4 provided at the drain of the transistor TR2 controls the supply of the power source Vcc to the transistor TR2, thereby controlling the light emission and non-light emission of the organic EL element 12. Thus, in this embodiment, the transistor TR4 constitutes a light emission control switch circuit for controlling light emission and non-light emission of the organic EL element 12 as a light emitting element. Further, during the period when the organic EL element 12 is not emitting light, the transistor TR3 sets the source side end of the signal level holding capacitor C2 to the ground potential as the reference voltage, and in this state, the transistor TR1 sets the signal level holding capacitor. The gate side end of C2 is connected to the signal line SIG, thereby setting the signal level Vin of the signal line SIG in the signal level holding capacitor C2.

  In the display device 51, the driving transistor TR2 of the organic EL element 12 is formed in the same manner as the transistor TR2 of the display device according to the first to third embodiments. Further, the transistor TR1 that connects the signal line SIG to the gate of the transistor TR2 is formed in the same manner as the transistor TR1 of the display device according to the first or second embodiment.

  Thus, also in this embodiment, in the configuration in which the light emitting element is driven by the transistor having the source follower circuit configuration by the gate source voltage by the voltage between the terminals of the signal level holding capacitor, the power supply of the transistor TR2 for driving the organic EL element 12 is used. By controlling the light emission and non-light emission, the same effect as in the first embodiment can be obtained.

  FIG. 6 is a connection diagram showing a display apparatus according to the fourth embodiment of the present invention in comparison with FIG. In the display device 61, the pixel unit 62 is provided with scanning lines SCN, SCN1, SCN2, and SCN3 in the horizontal direction in units of lines with respect to the pixels 63 arranged in a matrix. A signal line SIG is provided in the vertical direction for each column so as to be orthogonal to the scanning lines SCN, SCN1, SCN2, and SCN3. With respect to the pixel portion 62 formed in this way, the display device 61 sets the gradation of each pixel 63 sequentially in line units by the vertical drive circuit 64 and the horizontal drive circuit 65.

  Therefore, the vertical drive circuit 64 generates the write signal ws and the drive scan signals ds1 and ds2 by the write scan circuit (WSCN) 64A, the drive scan circuit (DSCN) 64B, and the drive scan circuit (DSCN2) 64C to generate the scan line SCN, The signal is output to SCN1 and SCN2, and in the horizontal drive circuit 65, a drive signal is output to each signal line SIG by a horizontal selector (HSEL) 65A.

  In the display device 61, the vertical drive circuit 64 further generates a control signal az instructing correction of the threshold voltage Vth of the transistor TR2 by the auto zero circuit (ZERO) 64D and outputs it to the scanning line SCN3. Yes.

  That is, even if the above-described configuration prevents the deterioration of the image quality due to the aging of the organic EL element 12, if the threshold voltage Vth of the transistor TR2 varies, as can be seen from the above equation (1), Accordingly, the driving current in each pixel 23 varies, and the image quality deteriorates. Therefore, in the display device 61, when the signal level Vin of the signal line SIG is set in the signal level holding capacitor Cs2, the threshold voltage Vth of the transistor TR2 is set in advance to the signal level holding capacitor Cs2. By setting, the variation in threshold voltage Vth is corrected.

  That is, in the pixel 63, the signal level holding capacitor Cs2 is provided at the gate source of the transistor TR2, and the organic EL element 12 is driven by the transistor TR2 by the gate source voltage Vgs based on the voltage across the terminals of the signal level holding capacitor Cs2. . Further, the supply of the power source Vcc to the transistor TR2 is controlled by the on / off control of the transistor TR4 provided at the drain of the transistor TR2, thereby controlling the light emission and non-light emission of the organic EL element 12.

  In the pixel 63, the signal level of the signal line SIG is set by the transistor TR1 via the capacitor Cs1 with respect to the signal level holding capacitor Cs2, and the transistor TR2 is short-circuited between the gate and source of the transistor TR2. A switch circuit by a transistor TR5 that switches to diode connection and a switch circuit by a transistor TR6 that sets the signal line side end of the capacitor Cs1 to a reference potential are provided. Thus, in the display device 61, the terminal voltage of the signal level holding capacitor Cs2 is set by the transistor TR1 through the capacitor Cs1 and the signal level Vin of the signal line SIG. In this case, the voltage between the terminals of the signal level holding capacitor Cs2 due to the connection to the signal line SIG via the capacitor Cs1 is divided by the capacitors Cs1 and Cs2 as shown in the following equation. The voltage ΔVin is increased. Accordingly, the signal line SIG is driven by the horizontal drive circuit 35 in consideration of this relational expression.

これにより図７及び図８に示すように、この場合も、画素６３においては、信号レベル保持用のコンデンサＣｓ２に設定された電圧によるゲートソース間電圧ＶｇｓによりトランジスタＴＲ２で有機ＥＬ素子１２を駆動して、有機ＥＬ素子１２の経時変化による画質劣化が防止される。

As a result, as shown in FIGS. 7 and 8, in this case as well, in the pixel 63, the organic EL element 12 is driven by the transistor TR2 by the gate-source voltage Vgs based on the voltage set in the signal level holding capacitor Cs2. Thus, image quality deterioration due to a change with time of the organic EL element 12 is prevented.

  Thus, immediately before setting the terminal voltage of the capacitor Cs2 for holding the signal level by the signal level Vin of the signal line SIG, the display device 61 sets the transistor TR5 to the ON state by the control signal az and makes the transistor TR2 a diode. At the same time, the signal line side end of the coupling capacitor Cs1 is held at a predetermined reference potential, and then the source of the transistor TR2 is set to the reference potential by switching the drive scan signals ds1 and ds2, and the transistor TR2 Stop supplying power to the unit.

  As a result, in the transistor TR2, the gate voltage Vg that has risen temporarily decreases gradually, and when the gate-source voltage Vgs reaches the threshold voltage Vth, the decrease in the gate voltage Vg is stopped, thereby maintaining the signal level. The threshold voltage Vth of the transistor TR2 is set in the capacitor Cs2.

  As a result, the control signal az is switched to disconnect the signal line side end of the coupling capacitor Cs1 from the reference voltage, and after the diode connection of the transistor TR2 is stopped, the write signal ws is raised and the signal line SIG is passed through the capacitor Cs1. The terminal voltage of the signal level holding capacitor Cs2 is set by the signal level Vin. As a result, the signal level holding capacitor Cs2 is corrected by the threshold voltage Vth of the transistor TR2, and a voltage corresponding to the signal level of the signal line SIG is set. In the transistor TR2, the capacitor Cs2 is set. The organic EL element 12 is current-driven by the gate-source voltage Vgs due to the voltage, and variations due to the threshold voltage of the transistor TR2 can be prevented. 8A to 8E show connection of transistors corresponding to periods TA to TE in FIG. 7, respectively.

  In the pixel 63, the driving transistor TR2 of the organic EL element 12 is formed in the same manner as the transistor TR2 of the display device according to the first to third embodiments. Further, a transistor TR1 that connects the signal line SIG to the coupling capacitor Cs1, a transistor TR6 that connects the signal line side end of the coupling capacitor Cs1 to the reference voltage, and a transistor TR5 that short-circuits the gate drain of the transistor TR2; Similarly to the transistor TR1 of the display device according to the first or second embodiment described above, the gate electrode is formed so as to be biased on the electrode side opposite to the gate side of the driving transistor TR2.

  That is, even when the threshold voltage Vth is set to the signal level holding capacitor Cs2 in this way, the voltage across the terminals of the signal level holding capacitor Cs2 is set to the signal level Vin of the signal line SIG. When the supply of the power source Vcc to the transistor TR2 is started and the driving of the organic EL element 12 is started, the source voltage Vs of the transistor TR2 rises, and the gate voltage Vg of the transistor TR2 is made to accurately follow the rise of the source voltage Vs. In the same way as described above with reference to FIG. 13, parasitic capacitance such as the transistor TR2 impairs the rise of the gate voltage Vg.

  However, if the gate electrode of the transistor TR2 is biased to the source side as in this embodiment, the parasitic capacitance Cpgd that impairs the rise of the gate voltage Vg can be reduced, and the capacitance Cpgd of the capacitor Cs2 for holding the signal level. Can be increased equally to increase the gate voltage Vg. Also, for the transistors TR1, TR5, TR6, if the gate electrode is biased to the electrode side opposite to the gate side of the transistor TR2, the parasitic capacitance that impairs the rise of the gate voltage Vg can be reduced. Thus, the same effect as in the first embodiment can be obtained.

  In the above embodiment, the transistor TR3 sets the source side end for holding the signal level to the reference voltage and sets the terminal voltages of the capacitors C2 and Cs2 for holding the signal level. Although the case where the voltage between the terminals of the signal level holding capacitors C2 and Cs2 is set is described, the present invention is not limited to this, and the threshold voltage of the organic EL element is set to the voltage at the source side end for holding the signal level. You may make it apply to a setting reference | standard. In this case, the supply of power to the driving transistor TR2 is stopped, and the source side end for holding the signal level can be set to the threshold voltage of the organic EL element after a certain time has passed.

  Further, in the above-described embodiments, the case where each pixel is configured by a channel etch type TFT has been described. However, the present invention is not limited to this, and when each pixel is formed by a channel stopper type TFT, the top gate is further formed. The present invention can be widely applied to the case where each pixel is constituted by TFTs based on the method.

  In the above-described embodiment, the case where the organic EL element and the pixel circuit are formed on the glass substrate by applying the amorphous silicon process has been described. However, the present invention is not limited thereto, and the transistor is formed using polysilicon. In this case, the present invention can be widely applied to a case where a driver circuit is formed separately from the pixel portion using a silicon substrate and then connected to the pixel portion to be integrated.

  In the above-described embodiments, the case where the light emitting element by the organic EL element is current-driven has been described. However, the present invention is not limited to this, and can be widely applied to display devices using various light-emitting elements related to current driving. .

  The present invention relates to a display device, and can be applied to a display device using an organic EL element, for example.

It is sectional drawing which shows the transistor applied to the display apparatus which concerns on Example 1 of this invention. It is sectional drawing which shows the transistor applied to the display apparatus which concerns on Example 2 of this invention. It is sectional drawing which shows the transistor applied to the display apparatus which concerns on Example 3 of this invention. It is a connection diagram which shows the display apparatus which concerns on Example 4 of this invention. 5 is a time chart for explaining the operation of the display device of FIG. 4. It is a connection diagram which shows the display apparatus which concerns on Example 5 of this invention. It is a time chart with which it uses for description of operation | movement of the display apparatus of FIG. FIG. 8 is a connection diagram for explaining the time chart of FIG. 7. It is a block diagram which shows the structure of a display apparatus. It is a connection diagram which shows the structure of the display apparatus by an organic EL element. It is a characteristic curve figure which shows the characteristic of an organic EL element. It is a characteristic curve figure with which it uses for description of the change of the operating point of an organic EL element. FIG. 3 is a connection diagram illustrating a pixel circuit having a source follower circuit configuration along with a peripheral configuration. 14 is a time chart for explaining the operation of the pixel circuit of FIG. 13. FIG. 15 is a connection diagram for explaining the time chart of FIG. 14. It is sectional drawing which shows a channel etch type TFT. It is sectional drawing which shows a channel stopper type TFT. It is a time chart used for description of the influence by parasitic capacitance. It is a connection diagram which shows a parasitic capacitance.

Explanation of symbols

1, 11, 21, 51, 61 ... Display device, 2, 22, 52, 62 ... Pixel unit, 3, 23, 53, 63 ... Pixel, 4, 24, 54, 64 ... Vertical drive circuit, 4A, 24A, 54A, 64A ... write scan circuit, 5, 25, 55, 65 ... horizontal drive circuit, 12 ... organic EL element, 24B, 54B, 54C, 64B, 64C ... drive scan circuit, 64D ... ... Auto-zero circuit, 42 ... Gate electrode, 46 ... Drain electrode, 47 ... Source electrode, C1, C2, Cs1, Cs2 ... Capacitor, TR1 to TR6 ... Transistor

Claims (9)

In a display device having a pixel portion in which pixels driven by current are arranged in a matrix and a drive circuit for driving the pixel portion,
The pixel is
A light emitting element;
A transistor for driving by a source follower circuit that holds a signal level holding capacitor between the gate and source, and drives the light emitting element by a gate-source voltage by a voltage between terminals of the signal level holding capacitor;
A signal line transistor for connecting a gate of the driving transistor to a signal line;
A light emission control switch circuit for stopping light emission of the light emitting element,
The drive circuit is
After stopping the light emission of the light emitting element by the switch circuit for light emission control, the voltage between the terminals of the signal level holding capacitor is set by the signal level of the signal line by driving the transistor for the signal line. ,
The driving transistor is:
A display device in which the gate electrode is formed biased toward the source electrode. The transistor for the signal line is
The display device according to claim 1, wherein the gate electrode is formed so as to be biased toward the electrode side on the signal line side. The switch circuit for light emission control,
A switch circuit for a power supply for connecting the driving transistor to a power supply;
The pixel is
A source-side switch circuit for connecting a source of the driving transistor to a source-side reference voltage;
The drive circuit is
The light emission and non-light emission of the light emitting element are controlled by on / off control of the power switch circuit,
While the light emitting element is not emitting light, driving the source side switch circuit sets one end of the signal level holding capacitor to the source side reference voltage and driving the signal line transistor. By setting the voltage at the other end of the signal level holding capacitor according to the signal level of the signal line,
The display device according to claim 1, wherein a voltage between terminals of the signal level holding capacitor is set according to a signal level of the signal line. The switch circuit for light emission control,
A switch circuit for a power supply for connecting the driving transistor to a power supply;
The pixel is
The coupling is disposed between the signal line transistor and the gate of the driving transistor, and mediates connection of the signal line to the gate of the driving transistor by the signal line transistor. A capacitor,
A short-circuit transistor that short-circuits the gate and drain of the driving transistor;
A capacitor side transistor that connects the signal line side end of the coupling capacitor to a reference voltage on the capacitor side;
The drive circuit is
The capacitor-side transistor and the short-circuiting transistor are set to an on state, and the power supply switch circuit is set to an off state, whereby the voltage between terminals of the signal level holding capacitor is set to the driving voltage. After setting the threshold voltage of the transistor,
By driving the signal line transistor, the signal level holding capacitor voltage is set according to the signal level of the signal line,
The capacitor side transistor, the signal line transistor, the short circuit transistor,
The display device according to claim 1, wherein a gate electrode is formed to be biased on an electrode side opposite to a gate side of the driving transistor. In a display device in which pixels driven by current are arranged in a matrix,
The pixel is
A light emitting element;
A transistor for driving by a source follower circuit that holds a signal level holding capacitor between the gate and source, and drives the light emitting element by a gate-source voltage by a voltage between terminals of the signal level holding capacitor;
A signal line transistor for connecting a gate of the driving transistor to a signal line, and setting a voltage between terminals of the signal level holding capacitor according to a signal level of the signal line;
A switch circuit for light emission control for stopping light emission of the light emitting element during a period in which the voltage between the terminals of the signal level holding capacitor is set by the transistor for the signal line,
The driving transistor is:
A display device in which the gate electrode is formed biased toward the source electrode. The transistor for the signal line is
The display device according to claim 5, wherein the gate electrode is formed so as to be biased toward the electrode side on the signal line side. The switch circuit for light emission control,
A switch circuit for power supply that stops supply of power to the drive transistor during at least a period in which the drive transistor is connected to the signal line by the signal line transistor;
The pixel is
A source switch circuit for connecting a source of the driving transistor to a reference voltage on a source side at least during a period in which the driving transistor is connected to the signal line by the signal line transistor;
The coupling is disposed between the signal line transistor and the gate of the driving transistor, and mediates connection of the signal line to the gate of the driving transistor by the signal line transistor. A capacitor,
A shorting transistor that short-circuits the gate drain of the driving transistor during a predetermined period before the gate of the driving transistor is connected to the signal line by the transistor for the signal line;
A capacitor-side transistor that connects the signal line side end of the coupling capacitor to a reference voltage on the capacitor side during a period in which the gate drain of the driving transistor is short-circuited by the short-circuit transistor. And
The capacitor side transistor, the signal line transistor, the short circuit transistor,
The display device according to claim 5, wherein a gate electrode is formed so as to be biased on an electrode side opposite to a gate side of the driving transistor. In a display device in which pixels by organic EL elements are arranged in a matrix,
The pixel is
The organic EL element;
A transistor for driving by a source follower circuit that holds a capacitor for holding a signal level between the gate and source, and drives the organic EL element by a gate-source voltage by a voltage between terminals of the capacitor for holding the signal level;
A signal line transistor for connecting a gate of the driving transistor to a signal line, and setting a voltage between terminals of the signal level holding capacitor according to a signal level of the signal line;
A switch circuit for light emission control for stopping light emission of the organic EL element during a period in which the voltage between the terminals of the signal level holding capacitor is set by the signal line transistor;
The driving transistor is:
A display device in which the gate electrode is formed biased toward the source electrode. The transistor for the signal line is
The display device according to claim 8, wherein the gate electrode is formed to be biased toward the electrode on the signal line side .

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