JP4747528B2 - Pixel circuit and display device - Google Patents

Description

  The present invention relates to a pixel circuit that current-drives an electro-optical element disposed for each pixel. The pixel circuit is a display device arranged in a matrix, and the amount of current supplied to an electro-optical element such as an organic EL light-emitting element is controlled by an insulated gate field effect transistor provided in each pixel circuit. The present invention relates to a so-called active matrix display device.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A

  A conventional pixel circuit is arranged at a portion where a scanning line and a signal line intersect, and includes at least an electro-optical element, a drive transistor, a sampling transistor, a storage capacitor, and a coupling capacitor. The drive transistor is arranged so as to supply a drive current from a predetermined power supply potential toward a predetermined output node, and its gate is connected to a predetermined control node. The electro-optic element has one end connected to the output node and the other end connected to a predetermined ground potential. The sampling transistor is connected between a predetermined input node and a signal line. The storage capacitor is connected to the control node. The coupling capacitance is arranged between the control node and the input node.

  In such a configuration, the sampling transistor operates when selected by the scanning line, samples the input signal from the signal line, and holds the signal potential corresponding to the input signal in the holding capacitor via the coupling capacitor. The drive transistor supplies a drive current to the output node in accordance with the signal potential held in the holding capacitor, thereby driving the electro-optic element with current. In this manner, the gate of the drive transistor receives the source-reference gate voltage by the signal potential held in the holding capacitor. The drive transistor causes a drive current to flow between the source and drain in accordance with the gate voltage, and energizes the electro-optic element. In general, the light emission luminance of an electro-optical element is proportional to the amount of current supplied. Furthermore, the drive current supply amount of the drive transistor is controlled by the gate voltage, that is, the signal potential written in the storage capacitor. As described above, the conventional pixel circuit controls the amount of drive current supplied to the electro-optical element by changing the signal voltage applied to the gate of the drive transistor in accordance with the input video signal.

Here, the operating characteristic of the drive transistor is expressed by the following equation.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ²
In this transistor characteristic formula, Ids represents a drain current flowing between the source and the drain, and is a drive current supplied to the electro-optical element in the pixel circuit. Vgs represents a gate applied voltage applied to the gate with reference to the source. Vth is the threshold voltage of the transistor. Μ represents the mobility of the semiconductor thin film constituting the channel of the transistor. In addition, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from this transistor characteristic equation, when the thin film transistor operates in the saturation region, if the gate voltage Vgs increases beyond the threshold voltage Vth, the thin film transistor is turned on and the drain current Ids flows. In principle, as indicated by the above transistor characteristic equation, the same amount of drain current Ids is always supplied to the electro-optic element if the gate voltage Vgs is constant. Therefore, if an input signal of the same level is supplied to all the pixels constituting the screen, all pixels should emit light with the same luminance, and the uniformity of the screen should be obtained.

  However, in reality, thin film transistors (TFTs) composed of semiconductor thin films such as polysilicon have variations in individual device characteristics. In particular, the threshold voltage Vth is not constant and varies from pixel to pixel. As is apparent from the above transistor characteristic equation, if the threshold voltage Vth of each drive transistor varies, even if the gate applied voltage Vgs is constant, the drain current Ids varies and the luminance varies from pixel to pixel. , Damage the screen uniformity. Conventionally, a pixel circuit incorporating a function for canceling variations in threshold voltages of drive transistors has been developed, and is disclosed in, for example, Patent Document 3 described above.

  A pixel circuit incorporating a function for canceling variations in threshold voltage can improve screen uniformity to some extent. However, the variation in characteristics of the polysilicon thin film transistor varies not only in the threshold voltage but also in the mobility μ from element to element. As is clear from the transistor characteristic equation described above, when the mobility μ varies, the drain current Ids varies even when the gate applied voltage Vgs is constant. As a result, the emission luminance varies from pixel to pixel, and there is a problem that the uniformity of the screen is impaired.

In view of the above-described problems of the related art, an object of the present invention is to provide a pixel circuit and a display device that can compensate for variations in drain current of a drive transistor, and a driving method thereof. In order to achieve this purpose, the following measures were taken. That is, the present invention is arranged at a portion where the scanning line and the signal line intersect, and includes at least an electro-optic element, a drive transistor, a sampling transistor, a storage capacitor, and a coupling capacitor, and the drive transistor has a predetermined power supply potential And a gate connected to a predetermined control node, and one end of the electro-optic element is connected to the output node, and the other end of the electro-optic element. Is connected to a predetermined ground potential, the sampling transistor is connected between a predetermined input node and the signal line, the holding capacitor is connected to the control node, and the coupling capacitor is connected to the control node. The sampling transistor is arranged between the input node and operates when selected by the scanning line, samples the input signal from the signal line, and A signal potential corresponding to the input signal is held in the holding capacitor via the coupling capacitor, and the drive transistor supplies the drive current to the output node according to the signal potential held in the holding capacitor. Therefore, a threshold voltage correction circuit and a drive current correction circuit are incorporated in the pixel circuit for current driving the electro-optic element, and the threshold voltage correction circuit is configured to drive the drive before the current drive of the electro-optic element. In order to detect the threshold voltage of the transistor and cancel the influence in advance, the detected potential is held in the storage capacitor, and the drive current correction circuit starts driving the electro-optic element and then drives the drive transistor. There detecting the variation of the drive current supplied to adjust the signal potential retained in the retention capacitor so as to cancel the variation in accordance with the detection result, the The voltage correction circuit includes a switching transistor that connects the drive transistor and the electro-optic element at the output node, a switching transistor that is connected between the control node and the output side of the drive transistor, and a predetermined fixed potential. And a switching transistor connected between the input node and the drive current correction circuit. The driving current correction circuit includes a capacitor connected between a predetermined power supply potential and the input node, and another capacitor connected to the input node. And a switching transistor connected between the other capacitive element and the output node, and a switching transistor connected between the control node and the coupling capacitor .

Further, the present invention includes a row-shaped scanning line, a column-shaped signal line, and a pixel circuit disposed at each of the intersecting portions. The pixel circuit includes at least an electro-optic element, a drive transistor, a sampling transistor, and the like. The drive transistor includes a storage capacitor and a coupling capacitor, and the drive transistor is arranged to supply a drive current from a predetermined power supply potential toward a predetermined output node, and has a gate connected to a predetermined control node, The electro-optic element has one end connected to the output node, the other end connected to a predetermined ground potential, the sampling transistor connected between a predetermined input node and the signal line, and the storage capacitor Is connected to the control node, the coupling capacitor is connected between the control node and the input node, and the sampling transistor is selected by a scanning line. The input signal is sampled from the signal line, and the signal potential corresponding to the input signal is held in the holding capacitor via the coupling capacitor, and the drive transistor is held in the holding capacitor. In a display device in which the drive current is supplied to the output node according to a signal potential, and the electro-optic element is current-driven, the pixel circuit includes a threshold voltage correction circuit and a drive current correction circuit. The threshold voltage correction circuit detects the threshold voltage of the drive transistor prior to current driving of the electro-optic element, and holds the detected potential in the storage capacitor in order to cancel the influence in advance, and the drive current The correction circuit detects a variation in the drive current supplied by the drive transistor after starting the current drive of the electro-optical element, and performs the detection according to the detection result. For adjusting the signal potential retained in the retention capacitor so as to cancel out the threshold voltage correction circuit includes a switching transistor for connecting the said drive transistor and the electro-optical element in said output node, said control node and said A switching transistor connected between the output side of the drive transistor and a switching transistor connected between the predetermined fixed potential and the input node;
The drive current correction circuit includes a capacitive element connected between a predetermined power supply potential and the input node, another capacitive element connected to the input node, and between the other capacitive element and the output node. The switching transistor is connected, and the switching transistor is connected between the control node and the coupling capacitor .

  According to the present invention, the pixel circuit incorporates a threshold voltage compensation circuit and a drive current compensation circuit. The threshold voltage compensation circuit can improve the uniformity of the screen by correcting the variation of the threshold voltage of the drive transistor formed for each pixel in a circuit. Similarly, the drive current compensation circuit corrects the variation in the mobility of the drive transistor formed for each pixel in a circuit to remove the variation in the drive current for each pixel, thereby improving the uniformity of the screen. . When TFTs composed of semiconductor thin films such as polysilicon are used for drive transistors in this way, even if device technology cannot suppress variations in characteristics such as threshold voltage and mobility, the pixel circuit has a correction function. By incorporating it, variations in threshold voltage and mobility can be absorbed, thereby improving the uniformity of a display device such as an organic EL display to a practical level.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, in order to clarify the background of the present invention, a general configuration of an active matrix display device and a pixel circuit included therein will be described as a reference example with reference to FIG. As shown in the figure, the active matrix display device includes a pixel array 1 as a main part and a peripheral circuit group. The peripheral circuit group includes a horizontal selector 2, a drive scanner 3, a write scanner 4, and the like.

  The pixel array 1 is composed of row-like scanning lines WS and column-like signal lines DL and pixel circuits 5 arranged in a matrix at portions where they intersect. The signal line DL is driven by the horizontal selector 2. The scanning line WS is scanned by the write scanner 4. Note that another scanning line DS is also wired in parallel with the scanning line WS, and this is scanned by the drive scanner 3. Each pixel circuit 5 samples the video signal from the signal line DL when selected by the scanning line WS. Further, when selected by the scanning line DS, the electro-optical element is driven in accordance with the sampled video signal. This electro-optical element is a current-driven light emitting element formed in each pixel circuit 5.

  FIG. 2 is a reference diagram showing a basic configuration of the pixel circuit 5 shown in FIG. The pixel circuit 5 includes a sampling thin film transistor (sampling transistor Tr1), a drive thin film transistor (drive transistor Tr2), a switching thin film transistor (switching transistor Tr3), a storage capacitor C1, an electro-optical element EL, and the like. In this reference example, the transistors Tr1, Tr2, and Tr3 are polysilicon TFTs and are all P-channel type. However, the present invention is not limited to this, and the polysilicon TFT may be an N-channel type instead of the P-channel type, and the pixel circuit 5 may be configured by mixing them. The electro-optical element EL is a light emitting element such as an organic EL element. The pixel circuit 5 constituted by these elements is arranged at the intersection of the signal line DL and the scanning lines WS and DS. The signal line DL is connected to the drain of the sampling transistor Tr1, the scanning line WS is connected to the gate of the sampling transistor Tr1, and the other scanning line DS is connected to the gate of the switching transistor Tr3.

  The drive transistor Tr2, the switching transistor Tr3, and the electro-optical element EL are connected in series between the power supply potential Vcc and the ground potential GND. That is, the source of the drive transistor Tr2 is connected to the power supply potential Vcc, while the cathode of the electro-optical element EL is connected to the ground potential GND. In general, an organic EL element constituting the electro-optic element EL is represented by a diode symbol because it has a rectifying property. On the other hand, the sampling transistor Tr1 and the holding capacitor C1 are connected to the gate of the drive transistor Tr2. The gate-source voltage of the drive transistor Tr2 is represented by Vgs.

  The operation of the pixel circuit 5 is as follows. First, when the scanning line WS is selected (low level here) and an input signal is applied to the signal line DL, the sampling transistor Tr1 is turned on and the input signal is written into the holding capacitor C1. . The signal potential written in the storage capacitor C1 becomes the gate potential Vgs of the drive transistor Tr2. Subsequently, when the scanning line WS is set to a non-selected state (here, high level), the signal line DL and the drive transistor Tr2 are electrically disconnected, but the gate potential Vgs of the drive transistor Tr2 is stably held by the holding capacitor C1. Is done. Subsequently, when another scanning line DS is set to a selected state (here, low level), the switching transistor Tr3 becomes conductive, and a drive current flows through the transistors Tr2 and Tr3 and the electro-optical element EL from the power supply potential Vcc toward the ground potential GND. . When the scanning line DS is in a non-selected state, the switching transistor Tr3 is turned off and the driving current does not flow. The switching transistor Tr3 is inserted to control the light emission time of the electro-optical element EL.

  The current flowing through the drive transistor Tr2 and the electro-optical element EL has a value corresponding to the gate-source voltage Vgs of the drive transistor Tr2, and the electro-optical element EL continues to emit light with luminance corresponding to the current value. As described above, the operation of selecting the scanning line WS and transmitting the input signal applied to the signal line DL to the inside of the pixel circuit 5 is referred to as “writing”. Once the input signal is written as described above, the electro-optical element EL continues to emit light at a constant luminance until the next rewriting.

  As described above, in the pixel circuit 5, the value of the current flowing through the electro-optical element EL is controlled by changing the gate application voltage Vgs of the drive transistor Tr2 according to the input signal. At this time, the source of the P-channel type drive transistor Tr2 is connected to the power supply potential Vcc, and this transistor Tr2 always operates in the saturation region. Therefore, the drive transistor Tr2 is a constant current source that supplies a constant drain current Ids according to Vgs, as shown in the previous transistor characteristic equation.

  However, actually, the threshold voltage of the drive transistor Tr2 varies from pixel to pixel, and it is necessary to correct this. FIG. 3 shows a reference example in which a threshold voltage correction function is incorporated in a pixel circuit, which is described in Patent Document 3, for example. As shown in the figure, this pixel circuit 5 is arranged at a portion where three scanning lines WS, DS, AZ and one signal line DL intersect, and at least the electro-optical element EL, the drive transistor Tr2, and the sampling. A transistor Tr1, a holding capacitor C1, and a coupling capacitor C2 are provided. In this reference example, only the drive transistor Tr2 is a P-channel type, and the remaining transistors are all N-channel types. The drive transistor Tr2 is arranged to supply a drive current Ids from a predetermined power supply potential Vcc toward a predetermined output node B, and its gate is connected to a predetermined control node A. The sampling transistor Tr1 is connected between a predetermined input node C and the signal line DL. The gate of the sampling transistor Tr1 is connected to the scanning line WS. The storage capacitor C1 is connected between the power supply potential Vcc and the control node A. The coupling capacitor C2 is arranged between the control node A and the input node C. An auxiliary capacitor C3 is connected between the power supply potential Vcc and the input node C. A switching transistor Tr3 connects the drive transistor Tr2 and the electro-optical element EL at the output node B. The gate of the switching transistor Tr3 is connected to the scanning line DS.

  In the writing operation of the pixel circuit 5 shown in FIG. 3, first, the sampling transistor Tr1 operates when selected by the scanning line WS, samples the input signal Vsig from the signal line DL, and a signal corresponding to the input signal Vsig. The potential is held in the holding capacitor C1 through the coupling capacitor C2. The drive transistor Tr2 supplies the drive current Ids to the output node B in accordance with the signal potential held in the holding capacitor C1, thereby driving the electro-optic element EL with current. Actually, when the switching transistor Tr3 is turned on via the scanning line DS, the drive current Ids is supplied from the drive transistor Tr2 to the electro-optical element EL via the output node B, and the light emission operation is performed.

  The pixel circuit 5 having such a configuration incorporates a threshold voltage correction circuit in addition to a normal writing function. This threshold voltage correction circuit detects the threshold voltage of the drive transistor Tr2 prior to current driving of the electro-optical element EL, and holds the detected potential in the storage capacitor C1 in order to cancel the influence in advance. In this reference example, this threshold voltage correction circuit is composed of additional switching transistors Tr4 and Tr5. One switching transistor Tr4 is connected between a predetermined fixed potential Vofs and the input node C. The gate of the switching transistor Tr4 is connected to a scanning line AZ provided separately for threshold voltage correction. The switching transistor Tr5 is connected between the control node A and the output side (drain side) of the drive transistor Tr2. The gate of the switching transistor Tr5 is also connected to the scanning line AZ.

  With reference to the timing chart of FIG. 4, the threshold voltage correction operation and the writing operation of the pixel circuit according to the reference example shown in FIG. 3 will be described in detail. The timing chart shown in the figure shows that one field (1f) starts at timing T1 and one field ends at timing T7. Along the time axis T, the level changes of the scanning lines WS, DS and AZ are represented. Further, the potential change of the control node A and the output node B along the same time axis T is shown. The change in potential of the control node A (gate of the drive transistor Tr2) is represented by a solid line, and the change in potential of the output node B (anode of the electro-optical element EL) is represented by a chain line to distinguish it from this.

  At the start timing T1 of the field, the scanning lines WS and AZ are at a low level, while the scanning line DS is at a high level. Accordingly, only the switching transistor Tr3 is in the on state and the electro-optical element EL is caused to emit light, while the remaining transistors Tr1, Tr4 and Tr5 are in the off state. At this time, the control node A is maintained at the signal potential held in the holding capacitor C1. On the other hand, the output node B is located above the ground potential GND by a voltage drop of the electro-optical element EL.

  When the timing T2 is reached, the scanning line AZ is switched from the low level to the high level, and the threshold voltage correction operation is performed. When the scanning line AZ becomes high level, the switching transistors Tr4 and Tr5 are turned on. When the switching transistor Tr4 is turned on, the input node C is set to the fixed potential Vofs, and the standby state for the threshold voltage correction operation is set. At the same time, the switching transistor Tr5 is turned on, whereby the charge held in the holding capacitor C1 is discharged to the drain side of the drive transistor Tr2. As a result, the potential of the control node A decreases toward the ground potential GND.

  When the timing T3 is reached after the timing T2, the scanning line DS changes from the high level to the low level, and the switching transistor Tr3 is turned off. As a result, the electro-optical element EL is disconnected from the output node B, and thus enters a non-light emitting state. On the other hand, the drive current Ids supplied from the drive transistor Tr2 continues to flow into the storage capacitor C1 and the coupling capacitor C2 via the switching transistor Tr5 that is in the on state. As a result, the potential of the control node A starts to rise toward the power supply potential Vcc. When the potential of the control node A coincides with the threshold voltage Vth of the drive transistor Tr2 during this rising process, the gate of the drive transistor Tr2 is cut off. As a result, the drain current Ids does not flow, and the potential corresponding to the drive transistor Vth is held in the holding capacitor C1. In this way, the threshold voltage Vth of the drive transistor Tr2 is held in the holding capacitor C1.

  When the timing T3a is reached, the scanning line AZ returns from the high level to the low level, and the threshold voltage Vth correction period ends. That is, the switching transistor Tr4 is turned off, and the input node C is disconnected from the fixed potential Vofs. The switching transistor Tr5 is also turned off, and the control node A is disconnected from the output side (drain side) of the drive transistor Tr2. Thus, a standby state is prepared for the next signal writing operation.

  At timing T4, a selection pulse is applied to the scanning line WS and rises from a low level to a high level. As a result, the sampling transistor Tr1 is turned on. The input signal Vsig supplied from the signal line DL is sampled by the sampling transistor Tr1 and coupled to the holding capacitor C1 through the coupling capacitor C2. As a result, the signal potential Vin corresponding to the capacitance division ratio of the coupling capacitor C2 and the holding capacitor C1 is held in the holding capacitor C1. This signal potential Vin is held in a form that is added to the threshold voltage Vth of the drive transistor previously held in the holding capacitor C1. As a result, the potential of the control node A is lowered by Vth + Vin with respect to the power supply potential Vcc. Vth + Vin is applied to the gate of the drive transistor Tr2 as the gate potential Vgs. At this time, since Vth is always added to the gate potential Vgs, even if the threshold voltage Vth of the drive transistor Tr2 varies for each pixel, this can be canceled. In all the pixels, the drive transistor Tr2 is eventually driven by the net signal potential Vin, so that the uniformity can be improved.

  When the time allocated for signal writing (one horizontal period 1H) elapses from timing T4, the selection pulse is released at timing T5, and the scanning line WS returns to the low level again. As a result, the sampling transistor WS is turned off and enters a standby state in preparation for the next light emission operation.

  At timing T6, the scanning line DS rises from low level to high level, and the switching transistor Tr3 is turned on. As a result, the drive current Ids supplied from the drive transistor Tr2 flows into the electro-optical element EL via the output node B, and the light emission operation is performed. At this time, a voltage drop ΔVel is caused by the drive current passing through the electro-optical element EL. This voltage drop ΔVel is proportional to the drive current Ids.

  Thereafter, when the timing T7 is reached, the field is completed and the process proceeds to the next field.

  As described above, the pixel circuit of the reference example shown in FIG. 3 and FIG. 4 incorporates a threshold voltage correction circuit, can absorb variations in the threshold voltage of the drive transistor, and can improve screen uniformity to some extent. However, drive transistors have variations in mobility in addition to variations in threshold voltage, and it is impossible to ensure uniformity at a practical level unless they are absorbed. FIG. 5 shows a pixel circuit according to the present invention, in which a driving current correction circuit is incorporated in addition to the threshold voltage correction circuit described above.

  FIG. 5 is a circuit diagram showing a pixel circuit according to the present invention. For easy understanding, portions corresponding to the pixel circuit of the reference example shown in FIG. 3 are given corresponding reference numbers. This pixel circuit incorporates a drive current correction circuit in addition to the threshold voltage correction function. As shown in the figure, the pixel circuit 5 is arranged at a portion where five scanning lines WS, DS, AZ, X, and Y intersect with one signal line DL, and at least the electro-optic element EL and the drive A transistor Tr2, a sampling transistor Tr1, a holding capacitor C1, and a coupling capacitor C2 are provided. The drive transistor Tr2 is arranged to supply a drive current Ids from a predetermined power supply potential Vcc toward a predetermined output node B, and its gate is connected to a predetermined control node A. The sampling transistor Tr1 is connected between a predetermined input node C and the signal line DL. The gate of the sampling transistor Tr1 is connected to the scanning line WS. The storage capacitor C1 is connected between the power supply potential Vcc and the control node A. The coupling capacitor C2 is arranged between the control node A and the input node C. An auxiliary capacitor C3 is connected between the power supply potential Vcc and the input node C. A switching transistor Tr3 connects the drive transistor Tr2 and the electro-optical element EL at the output node B. The gate of the switching transistor Tr3 is connected to the scanning line DS.

  In the writing operation of the pixel circuit 5 shown in FIG. 5, the sampling transistor Tr1 operates when it is selected by the scanning line WS, samples the input signal Vsig from the signal line DL, and a signal corresponding to the input signal Vsig. The potential is held in the holding capacitor C1 through the coupling capacitor C2. The drive transistor Tr2 supplies the drive current Ids to the output node B in accordance with the signal potential held in the holding capacitor C1, thereby driving the electro-optic element EL with current. Actually, when the switching transistor Tr3 is turned on via the scanning line DS, the drive current Ids is supplied from the drive transistor Tr2 to the electro-optical element EL via the output node B, and the light emission operation is performed.

  The pixel circuit 5 having such a configuration incorporates a threshold voltage correction circuit in addition to a normal writing function. This threshold voltage correction circuit detects the threshold voltage of the drive transistor Tr2 prior to current driving of the electro-optical element EL, and holds the detected potential in the storage capacitor C1 in order to cancel the influence in advance. In the present embodiment, this threshold voltage correction circuit includes additional switching transistors Tr4 and Tr5. One switching transistor Tr4 is connected between a predetermined fixed potential Vofs and the input node C. The gate of the switching transistor Tr4 is connected to a scanning line AZ provided separately for threshold voltage correction. The switching transistor Tr5 is connected between the control node A and the output side (drain side) of the drive transistor Tr2. The gate of the switching transistor Tr5 is also connected to the scanning line AZ.

  The pixel circuit 5 having such a configuration incorporates a drive current correction circuit in addition to the threshold voltage correction circuit. This drive current correction circuit detects the variation in the drain current Ids supplied from the drive transistor Tr2 after starting the current drive of the electro-optic element EL, and is held in the storage capacitor C1 so as to cancel this variation according to the result. Adjust the signal potential. More specifically, the drive current correction circuit detects a voltage drop of the electro-optical element EL that fluctuates according to variations in the drive current Ids, and is held in the holding capacitor C1 so as to cancel the detected voltage drop fluctuation. Adjust the signal potential. The mobility of the drive transistor Tr2 varies from pixel to pixel. The drive current Ids varies according to the mobility variation. Accordingly, the voltage drop amount of the electro-optical element EL varies. By detecting this voltage drop amount and feeding it back to the control node A side of the drive transistor Tr2, the variation in mobility is canceled.

  The drive current correction circuit having the function of absorbing the variation in the mobility μ of the drive transistor Tr2 is composed of additional switching transistors Tr6 and Tr7 and an additional coupling capacitor C4. The coupling capacitor C4 is connected to the input node C. The switching transistor Tr7 is connected between the coupling capacitor C4 and the output node B. The gate of the switching transistor Tr7 is connected to the additional scanning line X. The switching transistor Tr6 is connected between the control node A and the coupling capacitor C2. The gate of the switching transistor Tr6 is further connected to another additional scanning line Y.

  The operation of the pixel circuit according to the present invention shown in FIG. 5 will be described in detail with reference to the timing chart of FIG. In order to facilitate understanding, corresponding reference numerals are used for portions corresponding to the timing chart according to the reference example shown in FIG. The timing chart of FIG. 6 shows that one field (1f) starts at timing T1 and one field ends at timing T7. A change in level of the scanning lines WS, DS, AZ, X, and Y is represented along the time axis T. In addition, potential changes at the control node A, the output node B, the input node C, and the intermediate node D are shown along the same time axis. The change in potential at the control node A and the input node C is represented by a solid line, and the change in potential at the output node B and the intermediate node D is represented by a chain line for distinction from this. Here, the control node A is the gate of the drive transistor Tr2, the output node B is the anode of the electro-optical element EL, and the input node C and the intermediate node D are both terminals of the coupling capacitor C2.

  When the field starts at timing T1, the scanning lines DS and Y are at the high level, while the scanning lines WS, AZ, and X are at the low level. Therefore, at this time T1, the switching transistors Tr3 and Tr6 are in the on state, while the sampling transistor Tr1, the switching transistors Tr4, Tr5, and Tr7 are in the off state. Since the switching transistor Tr6 is on, the intermediate node D and the control node A are connected. Further, since the switching transistor Tr3 is in the ON state, the drive current Ids supplied from the drive transistor Tr2 is sent to the electro-optical element EL through the output node B and is in the light emitting state.

  When proceeding to the next timing T2, the scanning lines AZ and X are switched from the low level to the high level. When the scanning line X becomes high level, the switching transistor Tr7 is turned on, and the coupling capacitor C4 is connected to the output node B side. Further, when the switching transistors Tr4 and Tr5 are turned on, the threshold voltage correction operation of the drive transistor is started. When the switching transistor Tr4 is turned on, the input node C is set to the fixed potential Vofs, and the standby state for the threshold voltage correction operation is set. At the same time, the switching transistor Tr5 is turned on, whereby the charge held in the holding capacitor C1 is discharged to the drain side of the drive transistor Tr2. As a result, the potential of the control node A decreases toward the ground potential GND.

  When the timing T3 is reached after the timing T2, the scanning line DS changes from the high level to the low level, and the switching transistor Tr3 is turned off. As a result, the electro-optical element EL is disconnected from the output node B, and thus enters a non-light emitting state. On the other hand, the drive current Ids supplied from the drive transistor Tr2 continues to flow into the storage capacitor C1 and the coupling capacitor C2 via the switching transistor Tr5 that is in the on state. As a result, the potential of the control node A starts to rise toward the power supply potential Vcc. When the potential of the control node A coincides with the threshold voltage Vth of the drive transistor Tr2 during this rising process, the gate of the drive transistor Tr2 is cut off. As a result, the drain current Ids does not flow, and the potential corresponding to the drive transistor Vth is held in the holding capacitor C1. In this way, the threshold voltage Vth of the drive transistor Tr2 is held in the holding capacitor C1.

  When the timing T3a is reached, the scanning line AZ returns from the high level to the low level, and the threshold voltage Vth correction period ends. That is, the switching transistor Tr4 is turned off, and the input node C is disconnected from the fixed potential Vofs. The switching transistor Tr5 is also turned off, and the control node A is disconnected from the output side (drain side) of the drive transistor Tr2. Thus, a standby state is prepared for the next signal writing operation.

  At timing T4, a selection pulse is applied to the scanning line WS and rises from a low level to a high level. As a result, the sampling transistor Tr1 is turned on. The input signal Vsig supplied from the signal line DL is sampled by the sampling transistor Tr1 and coupled to the holding capacitor C1 through the coupling capacitor C2. As a result, the signal potential Vin corresponding to the capacitance division ratio of the coupling capacitor C2 and the holding capacitor C1 is held in the holding capacitor C1. This signal potential Vin is held in a form that is added to the threshold voltage Vth of the drive transistor previously held in the holding capacitor C1. As a result, the potential of the control node A is lowered by Vth + Vin with respect to the power supply potential Vcc. Vth + Vin is applied to the gate of the drive transistor Tr2 as the gate potential Vgs. At this time, since Vth is always added to the gate potential Vgs, even if the threshold voltage Vth of the drive transistor Tr2 varies for each pixel, this can be canceled. In all the pixels, the drive transistor Tr2 is eventually driven by the net signal potential Vin, so that the uniformity can be improved.

  When the time allocated for signal writing (one horizontal period 1H) elapses from timing T4, the selection pulse is released at timing T5, and the scanning line WS returns to the low level again. As a result, the sampling transistor WS is turned off and enters a standby state in preparation for the next light emission operation.

  When the timing T6 is reached, the scanning line DS rises again from the low level to the high level, and the switching transistor Tr3 is turned on. As a result, the drive current Ids supplied from the drive transistor Tr2 flows into the electro-optical element EL via the output node B. As a result, a voltage drop ΔVel occurs in the electro-optical element EL, and the potential of the output node B, which is the anode of the electro-optical element EL, rises with respect to the ground potential GND. The potential drop ΔVel appearing at the output node B is coupled to the coupling capacitor C4 via the switching transistor Tr7 in the on state. At this time, since the switching transistor Tr6 is turned off, the intermediate node D is disconnected from the control node A.

  Thereafter, at timing T6a, the scanning line Y rises again to the high level, while the scanning line X falls to the low level. As a result, the switching transistor Tr6 is turned on while the switching transistor Tr7 is turned off. As a result of the switching transistor Tr6 being turned on, the charges stored in the capacitors C3 and C4 are distributed to the holding capacitor C1 via the coupling capacitor C2. As a result, the potential of the intermediate node D rises by ΔVel ′, and the potential of the control node A also rises by ΔVel ″ corresponding to the charge distribution. In this way, when the drive current Ids varies in the positive direction, only that much. The voltage drop ΔVel generated in the electro-optical element EL increases. The amount corresponding to the increased voltage drop ΔVel is written in the storage capacitor C1, and the potential of the control node A is increased by ΔVel ″. In other words, the gate voltage Vgs of the drive transistor Tr2 is reduced by ΔVel ″, and the drive current Ids that varies in the positive direction is pulled back in the negative direction. This can cancel the variation in mobility of the drive transistor Tr2. .

  Thereafter, when the timing T7 is reached, the field is completed and the process proceeds to the next field.

It is a block diagram which shows the general structure of an active matrix display apparatus and a pixel circuit. It is a circuit diagram which shows the prior art example of a pixel circuit. It is a circuit diagram which shows the reference example of a pixel circuit. 4 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 3. It is a circuit diagram which shows the structure of the pixel circuit which concerns on this invention. 6 is a timing chart for explaining the operation of the pixel circuit according to the present invention shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array, 2 ... Horizontal selector, 3 ... Drive scanner, 4 ... Write scanner, 5 ... Pixel circuit, Tr1 ... Sampling transistor, Tr2 ... Drive transistor, Tr3 ... Switching transistor, Tr4 ... Switching transistor, Tr5 ... Switching transistor, Tr6 ... Switching transistor, Tr7 ... Switching transistor, C1 ... Retention capacitor, C2 ... Coupling capacitor, C3. ..Auxiliary capacitance, C4 ... coupling capacitance, EL ... electro-optic element

Claims (2)

It is arranged at a portion where the scanning line and the signal line intersect, and includes at least an electro-optical element, a drive transistor, a sampling transistor, a storage capacitor, and a coupling capacitor
The drive transistor is arranged to supply a drive current from a predetermined power supply potential toward a predetermined output node, and has a gate connected to a predetermined control node,
The electro-optic element has one end connected to the output node and the other end connected to a predetermined ground potential,
The sampling transistor is connected between a predetermined input node and the signal line,
The holding capacity is connected to the control node,
The coupling capacitance is arranged between the control node and the input node,
The sampling transistor operates when selected by a scanning line, samples an input signal from the signal line, and holds a signal potential corresponding to the input signal in the holding capacitor via the coupling capacitor,
In the pixel circuit for supplying the drive current to the output node in accordance with the signal potential held in the holding capacitor, and thereby driving the electro-optic element by current.
A threshold voltage correction circuit and a drive current correction circuit are incorporated,
The threshold voltage correction circuit detects the threshold voltage of the drive transistor prior to current driving of the electro-optic element and holds the detected potential in the storage capacitor in order to cancel the influence in advance.
The drive current correction circuit detects a variation in the drive current supplied by the drive transistor after starting the current drive of the electro-optic element, and is held in the storage capacitor so as to cancel the variation according to the detection result Adjust the signal potential ,
The threshold voltage correction circuit includes: a switching transistor that connects the drive transistor and the electro-optic element at the output node; a switching transistor that is connected between the control node and the output side of the drive transistor; A switching transistor connected between a fixed potential and the input node;
The drive current correction circuit includes a capacitive element connected between a predetermined power supply potential and the input node, another capacitive element connected to the input node, and between the other capacitive element and the output node. A pixel circuit comprising: a connected switching transistor; and a switching transistor connected between the control node and the coupling capacitor . It consists of a row-shaped scanning line, a column-shaped signal line, and a pixel circuit arranged at each of the intersecting portions,
The pixel circuit includes at least an electro-optic element, a drive transistor, a sampling transistor, a storage capacitor, and a coupling capacitor.
The drive transistor is arranged to supply a drive current from a predetermined power supply potential toward a predetermined output node, and has a gate connected to a predetermined control node,
The electro-optic element has one end connected to the output node and the other end connected to a predetermined ground potential,
The sampling transistor is connected between a predetermined input node and the signal line,
The holding capacity is connected to the control node,
The coupling capacitor is connected between the control node and the input node;
The sampling transistor operates when selected by a scanning line, samples an input signal from the signal line, and holds a signal potential corresponding to the input signal in the holding capacitor via the coupling capacitor,
In the display device in which the drive transistor supplies the drive current to the output node in accordance with the signal potential held in the holding capacitor, thereby driving the electro-optic element in current.
The pixel circuit includes a threshold voltage correction circuit and a drive current correction circuit,
The threshold voltage correction circuit detects the threshold voltage of the drive transistor prior to current driving of the electro-optic element and holds the detected potential in the storage capacitor in order to cancel the influence in advance.
The drive current correction circuit detects a variation in the drive current supplied by the drive transistor after starting the current drive of the electro-optic element, and is held in the storage capacitor so as to cancel the variation according to the detection result Adjust the signal potential ,
The threshold voltage correction circuit includes: a switching transistor that connects the drive transistor and the electro-optic element at the output node; a switching transistor that is connected between the control node and the output side of the drive transistor; A switching transistor connected between a fixed potential and the input node;
The drive current correction circuit includes a capacitive element connected between a predetermined power supply potential and the input node, another capacitive element connected to the input node, and between the other capacitive element and the output node. A display device comprising: a connected switching transistor; and a switching transistor connected between the control node and the coupling capacitor .

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