JP4501429B2 - Pixel circuit and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pixel circuit in which change over time in the threshold voltage of a driving transistor is suppressed. <P>SOLUTION: In a sampling transistor Tr1, when a gate is selected by a scanning line WS, a line between a source and a drain becomes conductive and a signal Vsig from a signal line DL is sampled and held in a holding capacitance C1. In a drive transistor Tr2, a gate G receives forward bias that is a positive polarity, with reference to the source S by a signal potential held in the holding capacitance C1, and current Ids, flowing between the source and the drain according to the forward bias, is caused to flow to a load device EL. A reverse bias applying means 9 is composed of a switching transistor Tr4 for writing a negative potential Vmb to the capacitance C1, applies the negative potential Vmb as the reverse bias, that is a negative polarity with reference to the source S, and performs downward adjustment of an upward change of the threshold voltage generated by applying the forward bias. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

  The present invention relates to a pixel circuit that current-drives a load element arranged for each pixel. The pixel circuit is a display device in which the pixel circuits are arranged in a matrix. In particular, a so-called field-effect transistor provided in each pixel circuit controls the amount of current supplied to a load element such as an organic EL light-emitting element. The present invention relates to an active matrix display device.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and a high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a liquid crystal display or the like in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit.
USP 5,684,365 JP-A-8-234683

  A conventional pixel circuit is disposed at a portion where a row scanning line and a column signal line intersect each other. Each pixel circuit includes at least a thin film type sampling transistor, a storage capacitor, a thin film type drive transistor, and a load element such as a light emitting element. When the gate of the sampling transistor is selected by the scanning line, the source / drain is made conductive and the video signal is sampled from the signal line. The sampled signal is written and held in the holding capacitor. The drive transistor has a gate connected to a storage capacitor, and one source / drain connected to a load element such as a light emitting element. The gate of the drive transistor receives a forward bias that is positive with respect to the source by the signal potential held in the holding capacitor. The drive transistor causes a current to flow between the source and drain in accordance with the forward bias, and energizes the light emitting element. In general, the luminance of a light-emitting element is proportional to the amount of current supplied. Further, the energization amount of the drive transistor is controlled by the signal potential written in the storage capacitor. Therefore, the light emitting element emits light with a luminance corresponding to the video signal.

The operating characteristic of the drive transistor is expressed by the following equation.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ²
In this transistor characteristic formula, Ids represents the drain current. Vgs represents a voltage applied to the gate with reference to the source, and when this is a positive value, it is called the forward bias. Vth is the threshold voltage of the transistor. In addition, μ represents the mobility of the semiconductor thin film constituting the channel of the transistor, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from this transistor characteristic equation, when the thin film transistor operates in the saturation region, if the gate voltage Vgs exceeds the threshold voltage Vth and increases to the positive side, the transistor is turned on and the drain current Ids flows. In other words, when the forward bias (Vgs) exceeds the threshold voltage (Vth), it is turned on. Conversely, when Vgs falls below Vth, the thin film transistor is cut off and the drain current Ids does not flow.

  Incidentally, the threshold voltage Vth of the thin film transistor is not necessarily constant and tends to vary with time. As is apparent from the transistor characteristic equation described above, when the threshold voltage Vth of the drive transistor varies, the drain current Ids varies even if the gate voltage Vgs is constant. As a result, the amount of current applied to the light emitting element changes, which causes a problem in that the light emission luminance changes. That is, there is a problem that even if a predetermined video signal is sent, the intended display cannot be obtained because the actual light emission luminance changes.

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a pixel circuit and a display device capable of suppressing a change with time of a threshold voltage of a drive transistor, and a driving method thereof. In order to achieve this purpose, the following measures were taken. That is, the present invention relates to a pixel circuit arranged at each intersection of a row scanning line and a column signal line, and includes at least a thin film type sampling transistor, a storage capacitor, a thin film type drive transistor, and a load element. Including. When the gate is selected by the scanning line, the sampling transistor conducts between the source and the drain, samples a signal from the signal line, and holds the sampled signal in the storage capacitor. The drive transistor receives a forward bias having a positive polarity on the basis of a source by a signal potential held in the holding capacitor, and energizes the load element with a current flowing between the source / drain in accordance with the forward bias. . As a characteristic feature, there is provided reverse bias application means for applying a reverse bias having a negative polarity with respect to the source to the gate of the drive transistor for a predetermined time, and the threshold voltage fluctuation of the drive transistor caused by the application of the forward bias is detected. Correction is performed by applying the reverse bias for a predetermined time. The reverse bias applying means includes a thin film type switching transistor that is driven on / off to apply a reverse bias to the gate of the drive transistor. The switching transistor is turned on in response to a forward-biased gate pulse, and starts applying a reverse bias to the gate of the drive transistor. The time during which the switching transistor is in the ON state is set to be shorter than a predetermined time during which the reverse bias is applied, and the fluctuation of the threshold voltage of the switching transistor itself due to the application of the forward bias gate pulse is reduced.

The switching transistor has a drain connected to the gate of the drive transistor, a source connected to a negative potential power source set lower than the source potential of the drive transistor, and when the gate pulse is input, between the drain and the source Is turned on and the negative potential is applied as a reverse bias to the gate of the drive transistor, and the negative potential is written to the storage capacitor. The holding capacitor maintains a reverse bias applied to the drive transistor for a predetermined time by the held negative potential after the switching transistor is turned off.
Further, a threshold voltage cancel circuit for detecting a threshold voltage of the drive transistor prior to energization of the load element and holding a potential necessary for canceling the fluctuation in the holding capacitor in advance and applying it to the gate of the drive transistor It has. The threshold voltage cancellation circuit includes a detection transistor for detecting the threshold voltage of the drive transistor. The detection transistor has its source / drain connected between the drain and gate of the drive transistor, and the gate is maintained at a negative potential except when the threshold voltage of the drive transistor is detected. The switching transistor has a source connected to the gate of the detection transistor, and uses a negative potential applied thereto as a reverse bias.

  In addition, the present invention includes a display device including row-like scanning lines, column-like signal lines, and pixel circuits arranged at portions where they intersect each other. Each pixel circuit includes at least a thin film sampling transistor, a storage capacitor, a thin film drive transistor, and a light emitting element. When the gate is selected by the scanning line, the sampling transistor conducts between the source and the drain, samples the video signal from the signal line, and holds the sampled video signal in the storage capacitor. The drive transistor receives a forward bias having a positive polarity with respect to a source based on a signal potential held in the holding capacitor, and energizes the light emitting element with a current flowing between the source and drain in accordance with the forward bias. To display. As a feature, each pixel circuit includes reverse bias applying means for applying a reverse bias having a negative polarity with respect to the source to the gate of the drive transistor for a predetermined time, and the drive transistor generated by the application of the forward bias The variation of the threshold voltage is corrected by applying the reverse bias for a predetermined time. The reverse bias applying means includes a thin film type switching transistor that is driven on / off to apply a reverse bias to the gate of the drive transistor. The switching transistor is turned on in response to a forward-biased gate pulse, and starts applying a reverse bias to the gate of the drive transistor. The time during which the switching transistor is in the ON state is set to be shorter than a predetermined time during which the reverse bias is applied, and the fluctuation of the threshold voltage of the switching transistor itself due to the application of the forward bias gate pulse is reduced.

The switching transistor has a drain connected to the gate of the drive transistor, a source connected to a negative potential power source set lower than the source potential of the drive transistor, and when the gate pulse is input, between the drain and the source Is turned on and the negative potential is applied as a reverse bias to the gate of the drive transistor, and the negative potential is written to the storage capacitor. The holding capacitor maintains a reverse bias applied to the drive transistor for a predetermined time by the held negative potential after the switching transistor is turned off.
Further, a threshold voltage cancel circuit for detecting the threshold voltage of the drive transistor prior to energization of the light emitting element and holding the potential necessary for canceling the fluctuation in the holding capacitor in advance and applying it to the gate of the drive transistor It has. The threshold voltage cancel circuit includes a detection transistor for detecting a threshold voltage of the drive transistor. The detection transistor has its source / drain connected between the drain and gate of the drive transistor, and the gate is maintained at a negative potential except when the threshold voltage of the drive transistor is detected. The switching transistor has a source connected to the gate of the detection transistor, and uses a negative potential applied thereto as a reverse bias.

The upward fluctuation of the threshold voltage of the drive transistor caused by applying the forward bias can be corrected downward by applying the reverse bias, thereby suppressing the fluctuation of the threshold voltage.

A malfunction of the switching transistor can be prevented, and a reverse bias can always be reliably applied to the drive transistor at an appropriate timing.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, in order to clarify the background of the present invention, a general configuration of an active matrix display device and a pixel circuit included therein will be described as a reference example with reference to FIG. As shown in the figure, the active matrix display device includes a pixel array 1 as a main part and a peripheral circuit group. The peripheral circuit group includes a horizontal selector 2, a drive scanner 3, a write scanner 4, and the like.

  The pixel array 1 is composed of row-like scanning lines WS and column-like signal lines DL and pixel circuits 5 arranged in a matrix at portions where they intersect. The signal line DL is driven by the horizontal selector 2. The scanning line WS is scanned by the write scanner 4. Note that another scanning line DS is also wired in parallel with the scanning line WS, and this is scanned by the drive scanner 3. Each pixel circuit 5 samples a signal from the signal line DL when selected by the scanning line WS. Further, when selected by the scanning line DS, the load element is driven according to the sampled signal. This load element is a current drive type light emitting element formed in each pixel circuit 5.

  FIG. 2 is a reference diagram showing a basic configuration of the pixel circuit 5 shown in FIG. The pixel circuit 5 includes a sampling thin film transistor (sampling transistor Tr1), a drive thin film transistor (drive transistor Tr2), a switching thin film transistor (switching transistor Tr3), a holding capacitor C1, a load element (organic EL light emitting element), and the like. Yes.

  The sampling transistor Tr1 becomes conductive when selected by the scanning line WS, samples the video signal from the signal line DL, and holds it in the holding capacitor C1. The drive transistor Tr2 controls the amount of current supplied to the light emitting element EL according to the signal potential held in the holding capacitor C1. The switching transistor Tr3 is controlled by the scanning line DS, and turns on / off energization to the light emitting element EL. That is, the drive transistor Tr2 controls the light emission luminance (brightness) of the light emitting element EL according to the energization amount, while the switching transistor Tr3 controls the light emission time of the light emitting element EL. With these controls, the light emitting element EL included in each pixel circuit 5 exhibits luminance corresponding to the video signal, and a desired display is displayed on the pixel array 1.

  FIG. 3 is a timing chart for explaining operations of the pixel array 1 and the pixel circuit 5 shown in FIG. At the beginning of one field period (1f), a selection pulse ws [1] is applied to the pixel circuits 5 in the first row during one horizontal period (1H) via the scanning line WS, and the sampling transistor Tr1 is turned on. As a result, the video signal is sampled from the signal line DL and written to the storage capacitor C1. One end of the storage capacitor C1 is connected to the gate of the drive transistor Tr2. Therefore, when the video signal is written into the storage capacitor C1, the gate potential of the drive transistor Tr2 rises according to the written signal potential. At this time, the selection pulse ds [1] is applied to the switching transistor Tr3 via another scanning line DS. During this time, the light emitting element EL continues to emit light. In the second half of the one-field period 1f, ds [1] is at a low level, so that the light emitting element EL is in a non-light emitting state. By adjusting the duty of the pulse ds [1], the ratio between the light emission period and the non-light emission period can be adjusted, and a desired screen luminance can be obtained. In the next horizontal period, scanning signal pulses ws [2] and ds [2] are applied to the pixel circuits in the second row from the scanning lines WS and DS, respectively.

  FIG. 4 is a graph showing a change with time of current-voltage (IV) characteristics of an organic EL element incorporated in the pixel circuit 5 as a light emitting element. In the graph, the curve indicated by the solid line indicates the characteristic in the initial state, and the curve indicated by the broken line indicates the characteristic after change with time. Generally, the IV characteristic of an organic EL element deteriorates over time as shown in the graph. The pixel circuit of the reference example shown in FIG. 2 has a problem that the drive transistor has a source follower configuration and cannot cope with a change in the IV characteristic of the EL element with time, resulting in deterioration of light emission luminance.

  FIG. 5A is a graph showing operating points of the drive transistor Tr2 and the light emitting element EL in the initial state. In the figure, the vertical axis represents the drain-source voltage Vds of the drive transistor Tr2, and the vertical axis represents the drain-source current Ids. As illustrated, the source potential is determined by the operating point of the drive transistor Tr2 and the light emitting element EL, and the voltage value varies depending on the gate voltage. Since the drive transistor Tr2 operates in the saturation region, the drive current Ids having a current value defined by the above-described transistor characteristic equation is supplied with respect to Vgs corresponding to the source voltage at the operating point.

  However, the IV characteristic of the light emitting element EL deteriorates with time as shown in FIG. As shown in FIG. 5B, the operating point changes due to the deterioration with time, and the source voltage of the transistor changes even when the same gate voltage is applied. As a result, the gate-source voltage Vgs of the drive transistor Tr2 changes, and the flowing current value fluctuates. At the same time, the value of the current flowing through the light emitting element EL also changes. When the IV characteristic of the light emitting element EL changes in this way, the luminance of the light emitting element EL changes with time in the pixel circuit having the source follower configuration of the reference example shown in FIG.

  FIG. 6 shows another reference example of the pixel circuit, which addresses the problems of the previous reference example shown in FIG. In order to facilitate understanding, parts corresponding to those in the reference example of FIG. The improvement is that the connection of the switching transistor Tr3 is changed, thereby realizing a bootstrap function. Specifically, the source of the switching transistor Tr3 is grounded, the drain is connected to the source (S) of the drive transistor Tr2 and one electrode of the storage capacitor C1, and the scanning line DS is connected to the gate. The other electrode of the storage capacitor C1 is connected to the gate (G) of the drive transistor Tr2.

  FIG. 7 is a timing chart for explaining the operation of the pixel circuit 5 shown in FIG. In the first horizontal period 1H in the field period 1f, the selection pulse ws [1] is sent from the write scanner 4 to the pixel circuit 5 in the first row via the scanning line WS. The numbers in [] correspond to the row numbers of the pixel circuits arranged in a matrix. When the selection pulse is applied, the sampling transistor Tr1 is turned on, and the input signal Vin is sampled from the signal line DL and written to the storage capacitor C1. At this time, the selection pulse ds [1] is applied to the switching transistor Tr3 from the drive scanner 3 via the scanning line DS, and the switching transistor Tr3 is in the ON state. Therefore, one electrode of the storage capacitor C1 and the source (S) of the drive transistor Tr2 are at the GND level. Since the input signal Vin is written to the holding capacitor C1 with the GND level as a reference, the gate potential (G) of the drive transistor Tr2 becomes Vin.

  Thereafter, the selection pulse ws [1] for the sampling transistor Tr1 is released, and then the selection pulse ds [1] for the switching transistor Tr3 is also released. As a result, the sampling transistor Tr1 and the switching transistor Tr3 are turned off. Therefore, the source (S) of the drive transistor Tr2 is disconnected from the GND and becomes a connection node for the anode of the light emitting element EL.

  The drive transistor Tr2 receives the input signal Vin held in the holding capacitor C1 at the gate, and causes a drain current to flow from the Vcc side toward the GND side according to the value. By this energization, the light emitting element EL emits light. At this time, a voltage drop occurs due to energization of the light emitting element EL, but the source potential (S) rises from the GND side toward the Vcc side accordingly. In the timing chart of FIG. 7, this increase is represented by ΔV. One end of the storage capacitor C1 is connected to the source (S) of Tr2, and the other end is connected to a high impedance gate (G). Therefore, when the source potential (S) is increased by ΔV, the gate potential (G) is increased by that amount, and the net input signal Vin is maintained as it is. Therefore, even if the source potential (S) varies by ΔV according to the current-voltage characteristics of the light emitting element EL, the gate voltage Vgs = Vin is always established, and the drain current is kept constant. That is, the drive transistor Tr2 functions as a constant current source for the light emitting element EL by the bootstrap function described above, despite the source follower configuration.

  Thereafter, when the selection pulse ds [1] returns to the high level, the switching transistor Tr3 is turned on, and the current to be supplied to the light emitting element EL is bypassed, so that the light emitting state is turned off. When the field period 1f ends in this way, the next field period starts, and the selection pulse ws [1] is applied to the sampling transistor Tr1 again to sample the input video signal Vin *. Since the level of the sampled video signal may be different between the previous field period and the current field period, the input video signal Vin is marked with an asterisk (*) to distinguish it. Note that such video signal writing and light emission operations are performed line-sequentially (in units of rows). Therefore, the selection pulses ws [1], ws [2]... Are sequentially applied to each row of pixels. Similarly, selection pulses ds [1], ds [2]... Are sequentially applied.

  As described above, the pixel circuit of FIG. 6 can drive the light-emitting element EL at a constant current even when the drive transistor Tr2 is an N-channel type, and can prevent luminance deterioration due to the time-dependent change of the IV characteristic of the light-emitting element EL. It was. However, the change with time due to aging causes the threshold voltage Vth to vary not only in the light emitting element EL but also in a thin film transistor having an amorphous silicon or polysilicon thin film element region. In the pixel circuit 5 shown in FIG. 6, the drive transistor Tr2 has the most significant Vth variation. This is because the drive transistor Tr2 is maintained in the on state while the gate is forward biased in order to keep the current flowing through the light emitting element EL for one field period (1f). In general, the Vth variation of a thin film transistor tends to increase in proportion to a function of the time during which the ON state lasts (the time during which the forward bias is applied) and the forward bias value. As is apparent from the transistor characteristic equation described above, when Vth varies, the current Ids for driving the light emitting element EL changes even if the gate voltage Vgs is constant. For this reason, luminance degradation of the light emitting element EL occurs. In the present invention, in order to cope with this Vth variation, a reverse bias is applied to the gate of the drive transistor to correct it in a circuit.

  FIG. 8 is a graph showing the relationship between the gate bias and threshold voltage fluctuation of a thin film transistor. As shown in the graph of FIG. 8, the device characteristics of the amorphous silicon thin film transistor and the polysilicon thin film transistor are as follows. Vth shifts positively. Conversely, when Vgs is applied with a negative value (that is, when a reverse bias is applied), the Vth variation has a characteristic of shifting to a negative value. It has been found that the absolute value of Vth tends to increase as the absolute value of Vgs increases. In the present invention, this device characteristic is positively utilized so that a forward bias is applied to the light emission period and a reverse bias is applied to the non-light emission period in one field. That is, −Vgs is applied to the drive transistor in a non-light emission period other than the light emission period in which + Vgs is applied to the drive transistor. And the voltage value of Vgs and the voltage application time are adjusted, and the Vth fluctuation | variation is suppressed as a result. That is, in the light emission period, the threshold voltage Vth of the drive transistor is shifted upward by the forward bias repeatedly applied. In order to correct this downward, a reverse bias is applied to the drive transistor during the non-light emitting period, thereby suppressing threshold voltage fluctuations.

  9A and 9B show a prototype on which the present invention is based. FIG. 9A is a circuit diagram showing the configuration, and FIG. 9B is a timing chart showing the operation. This prototype solves the problem of the pixel circuit of the reference example shown in FIG. 6 and is obtained by introducing reverse bias applying means into the pixel circuit based on the above-described principle.

  As shown in (A), the pixel circuit 5 is arranged at a portion where the row-shaped scanning lines WS and the column-shaped signal lines DL intersect. The pixel circuit 5 includes a thin film type drive transistor Tr2 and a load element (light emitting element EL) as well as a thin film type sampling transistor Tr1 and a storage capacitor C1. When the gate is selected by the scanning line WS, the sampling transistor Tr1 conducts between the source and the drain, samples the video signal Vsig from the signal line DL, and holds the sampled signal Vsig in the holding capacitor C1. The drive transistor Tr2 receives a forward bias having a positive polarity with respect to the source (S) based on the signal potential of which the gate (G) is held in the holding capacitor C1, and a current flowing between the source / drain in accordance with the forward bias. The light emitting element EL is energized with Ids.

  As a feature of this prototype, the pixel circuit 5 includes reverse bias applying means 9. The reverse bias applying means 9 applies a reverse bias having a negative polarity with respect to the source (S) to the gate (G) of the drive transistor Tr2, and the threshold voltage of the drive transistor Tr2 generated by applying the forward bias. The variation in Vth is corrected by applying a reverse bias. The reverse bias applying means 9 sets the reverse bias voltage value and the application time according to the operating characteristics and operating point of the drive transistor Tr2, thereby correcting the fluctuation of the threshold voltage Vth without excess or deficiency. For example, the reverse bias applying means 9 can set the absolute value of the reverse bias larger than the absolute value of the forward bias as the reverse bias application time is shorter than the forward bias application time.

  According to this prototype, the reverse bias applying means 9 includes a thin-film switching transistor Tr4 that is turned on / off to apply a reverse bias to the gate (G) of the drive transistor Tr2. The switching transistor Tr4 has a drain connected to the gate (G) of the drive transistor Tr2, a source connected to the power supply of the negative potential Vmb set lower than the source (S) potential of the drive transistor Tr2, and a gate connected to the control line. When a pulse is input via the MBS, the drain / source is turned on and the negative potential Vmb is applied as a reverse bias to the gate (G) of the drive transistor Tr2. The application time and amplitude of the pulse input to the gate of the switching transistor Tr4 and the level of the negative potential Vmb supplied to the source of the switching transistor Tr4 are optimally set to suppress fluctuations in the threshold voltage Vth of the drive transistor Tr2. ing. In addition, the amplitude of the pulse supplied from the control line MBS and the level of the negative potential Vmb are set so as to suppress the fluctuation of the threshold voltage of the switching transistor Tr4 itself. The load element is composed of an organic EL element that emits light when energized, and the switching transistor Tr4 controls on / off of the drive transistor Tr2 in response to a pulse input to the gate via the control line MBS. The light emission time and non-light emission time are defined.

  With reference to (B), the operation of the pixel circuit 5 according to this prototype will be described. In the horizontal period (1H) located at the head of the field period 1f, a selection pulse is applied to the scanning line WS, and the sampling transistor Tr1 becomes conductive. In the present embodiment, this selection pulse is applied simultaneously to the gate of the switching transistor Tr3. As a result, the sampled video signal Vsig is held as the input signal Vin in the holding capacitor C1. Immediately after the selection pulse is released, the drive transistor Tr2 causes the drain current Ids to flow in response to Vin and drives the light emitting element EL to be energized. The bootstrap operation works at the beginning of the light emission period, and the source (S) of the drive transistor Tr2 rises by the characteristic variation ΔV of the light emitting element EL. Along with this, the gate (G) potential also rises, so that the input signal Vin is kept constant. During this light emission period, a forward bias is applied to the gate (G) of the drive transistor Tr2.

  Subsequently, the switching transistor Tr4 constituting the reverse bias applying means 9 is turned on at the time when the non-light emitting period starts or at a time in the vicinity thereof. By this operation, the gate potential (G) of the drive transistor Tr2 becomes a voltage of Vmb when the transistor Tr4 is on. Further, the source value of the source (S) of the drive transistor Tr2 is lowered because the gate voltage is lowered, and a voltage drop of the light emitting element EL is caused accordingly, and finally the cathode potential (GND) is lowered. As a result, a reverse bias of −Vmb can be applied between the gate / source of the drive transistor Tr2. In this way, a reverse bias is applied between the gate and source of the drive transistor Tr2 where the Vth variation is most likely to occur, thereby correcting the Vth variation. The Vmb voltage, the MBS pulse amplitude, and the accompanying WS pulse amplitude are set to voltages and amplitudes that can correct the normal operation of the transistor and Vth variation. Even if the threshold voltage of an amorphous silicon TFT or polysilicon TFT changes due to this prototype, it can be automatically corrected on the circuit, so that the luminance degradation of the EL light emitting element can be prevented and high quality can be achieved. An organic EL display can be provided.

  Incidentally, the prototype shown in FIG. 9 includes a switching transistor Tr4 as the reverse bias applying means 9. As is apparent from the timing chart of FIG. 9B, the switching transistor Tr4 is turned on during the reverse bias period (within the non-emission period) when the gate pulse MBS is at a high level. That is, the forward bias is applied to the switching transistor Tr4 itself during the non-light emitting period. Eventually, the threshold voltage of the switching transistor Tr4 may change. If this is left unattended, the threshold voltage will fluctuate upward, and in the worst case, the switching transistor Tr4 will not turn on, and a reverse bias may not be applied to the drive transistor Tr2. In order to avoid this, if the amplitude of the gate pulse MBS applied to the switching transistor Tr4 is increased and the low side potential is set to a large negative potential, the switching transistor Tr4 can also be reverse-biased. The problem of voltage upward fluctuation can be solved. However, in order to make the low side of the gate pulse have a large negative potential, the dynamic range must be increased, which affects the withstand voltage of the pulse driver that supplies the gate pulse to the switching transistor Tr4 and increases the cost.

  FIG. 10 is an embodiment of the present invention in which the prototype shown in FIG. 9 is improved, in which (A) is a circuit diagram showing the configuration, and (B) is a timing chart showing the operation. This embodiment basically has many points in common with the prototype shown in FIG. 9, and corresponding portions are given corresponding reference numbers for easy understanding.

  As shown in FIG. 10A, the pixel circuit 5 of this embodiment includes a sampling transistor Tr1, a storage capacitor C1, a drive transistor Tr2, and a load element EL. When the gate is selected by the scanning line WS, the sampling transistor Tr1 conducts between the source and the drain, samples the signal Vsig from the signal line DL, and holds the sampled signal Vsig in the holding capacitor C1. The drive transistor Tr2 receives a forward bias (Vgs) having a positive polarity with respect to the source (S) by the signal potential held at the holding capacitor C1, and flows between the source / drain in accordance with the forward bias (Vgs). The load element EL is energized with the current IDS. As a feature of the present embodiment, reverse bias applying means 9 is provided, and a reverse bias Vmb having a negative polarity with respect to the source (S) is applied to the gate (G) of the drive transistor Tr2 for a predetermined time. In this way, the fluctuation of the threshold voltage of the drive transistor Tr2 caused by the application of the forward bias is corrected by the application of the reverse bias Vmb for a predetermined time.

  The reverse bias applying means 9 includes a thin film type switching transistor Tr4 that is driven on / off to apply a reverse bias Vmb to the gate (G) of the drive transistor Tr2. The switching transistor Tr4 is turned on in response to the forward-biased gate pulse MBS and starts applying the reverse bias Vmb to the gate (G) of the drive transistor Tr2. Here, as is apparent from the timing chart of FIG. 10B, the time for which the switching transistor Tr4 is in the ON state (reverse bias write time) is set shorter than the predetermined time (reverse bias period) for applying the reverse bias. Thus, the fluctuation of the threshold voltage of the switching transistor Tr4 itself due to the application of the forward bias gate pulse MBS is reduced.

  Specifically, the switching transistor Tr4 has a drain connected to the gate (G) of the drive transistor Tr2 and a source connected to a negative potential (Vmb) power source set lower than the source (S) potential of the drive transistor Tr2. When the gate pulse MBS is input, the drain / source is turned on and applied to the gate (G) of the drive transistor Tr2 with the negative potential Vmb as a reverse bias, and the negative potential Vmb is applied to the storage capacitor C1. I try to write. Here, as is clear from reference to the timing chart of FIG. 10B again, after the switching transistor Tr4 is turned off, the storage capacitor C1 applies a reverse bias to the drive transistor Tr2 for a predetermined time (at a predetermined time (with a negative potential Vmb). (Non-luminous period). In other words, the reverse bias application period is divided into a reverse bias writing period in which the switching transistor Tr4 is in an on state and a reverse bias holding period in which the switching transistor Tr4 is in an off state. As apparent from comparison with the prototype shown in FIG. 9, in the present embodiment, the time during which the switching transistor Tr4 is in the ON state is shortened, so that the upward fluctuation of the threshold voltage due to forward bias application can be reduced or ignored. .

  In the prototype of FIG. 9, since the switching transistor Tr4 is always turned on during the reverse bias period, the gate pulse MBS is at a high level. On the other hand, in the improved form of FIG. 10, the ON time of the switching transistor Tr4 is shortened as shown in the timing chart. That is, it is turned off except for the shortened on-time. For this reason, since a forward bias is applied to the switching transistor Tr4 only for a short time, the threshold voltage fluctuation is small. Here, in a state where the switching transistor Tr4 is turned off during the reverse bias application period, the gate (G) potential of the drive transistor Tr2 is Vmb by the storage capacitor C1. This is because when the switching transistor Tr4 is first turned on, the storage capacitor C1 is charged with the negative potential Vmb. That is, the reverse bias Vmb is held even when the switching transistor Tr4 is off, and as a result, the necessary reverse bias can be continuously applied to the drive transistor Tr2. In this manner, the pixel circuit of the present invention can reduce the threshold fluctuation of the switching transistor itself for applying the reverse bias while correcting the threshold fluctuation of the drive transistor by the reverse bias applying means.

  FIG. 11 shows a pixel circuit according to another reference example in which the simple pixel circuit shown in FIG. 2 is improved. (A) is a circuit diagram showing the configuration, and (B) shows the operation. It is a timing chart.

  As shown in (A), this reference example has a configuration in which a bootstrap circuit 6 and a threshold voltage cancel circuit 7 are added to the simple pixel circuit of FIG. Note that the reference example shown in FIG. 6 has a configuration in which only a bootstrap circuit is added to a simple pixel circuit. As shown in FIG. 11, the bootstrap circuit 6 automatically controls the level of the signal potential applied to the gate (G) of the drive transistor Tr2 so as to absorb the characteristic variation of the light emitting element EL. A switching transistor Tr3 is included. The scanning transistor WS is connected to the gate of the switching transistor Tr3, the source is connected to the power supply potential Vss, the drain is connected to one end of the storage capacitor C1, and the source (S) of the drive transistor Tr2. When a selection pulse is applied to the scanning line WS, the sampling transistor Tr1 is turned on and the switching transistor Tr3 is also turned on. As a result, the video signal Vsig is written to the holding capacitor C1 via the coupling capacitor C2. Thereafter, when the selection pulse is released from the scanning line WS, the switching transistor Tr3 is turned off, so that the storage capacitor C1 is disconnected from the power supply potential Vss and coupled to the source (S) of the drive transistor Tr2. Thereafter, when a selection pulse is applied to the scanning line DS, the switching transistor Tr7 is turned on, and the drive current is supplied to the light emitting element EL through the drive transistor Tr2. The light emitting element EL starts to emit light, and the anode potential rises according to the current / voltage characteristics, thereby causing the source potential of the drive transistor Tr2 to rise. At this time, since the holding capacitor C1 is disconnected from Vss, the held signal potential also rises (bootstrap) as the source potential rises, leading to an increase in the potential of the gate (G) of the drive transistor Tr2. That is, the gate voltage Vgs of the drive transistor Tr2 always matches the net signal potential held in the holding capacitor C1 even if the characteristics of the light emitting element EL change. By such a bootstrap operation, the drain current of the drive transistor Tr2 is always kept constant by the signal potential held in the holding capacitor C1 even if the characteristics of the light emitting element EL are changed, and the luminance of the light emitting element EL is changed. Does not occur. By adding such a bootstrap means 6, the drive transistor Tr2 can function as an accurate constant current source for the light emitting element EL.

  The threshold voltage cancel circuit 7 adjusts the level of the signal potential applied to the gate (G) of the drive transistor Tr2 so as to cancel the fluctuation of the threshold voltage of the drive transistor Tr2, and includes switching transistors Tr5 and Tr6. Yes. The gate of the switching transistor Tr5 is connected to another scanning line AZ, and the drain / source is connected between the gate and drain of the drive transistor Tr2. Similarly, the switching transistor Tr6 has a gate connected to the scanning line AZ, a source connected to a predetermined offset voltage Vofs, and a drain connected to one electrode of the coupling capacitor C2. In the illustrated example, the offset voltage Vofs, the power supply potential Vss, and the cathode voltage (GND) can take different potentials, but they may all be set to a common potential (for example, GND) depending on circumstances.

  When a control pulse is applied to the scanning line AZ, the switching transistor Tr5 is turned on, and a current flows from the Vcc side toward the gate of the drive transistor Tr2, so that the gate (G) potential rises. As a result, drain current flows out to the drive transistor Tr2, and the potential of the source (S) rises. When the potential difference Vgs between the gate potential (G) and the source potential (S) coincides with the threshold voltage Vth of the drive transistor Tr2, the drain current stops flowing according to the above-described transistor characteristic equation. The source / gate voltage Vgs at this time is written into the storage capacitor C1 as the threshold voltage Vth of the transistor Tr2. Since Vth written in the storage capacitor C1 is applied to the gate of the drive transistor Tr2 over the signal potential Vsig, the effect of the threshold voltage Vth is cancelled. Therefore, even if the threshold voltage Vth of the drive transistor Tr2 varies with time, the threshold voltage cancel circuit 7 can cancel this variation.

  (B) is a timing chart showing the scanning pulse waveform applied to each scanning line WS, DS, AZ and the potential waveform of the gate (G) and source (S) of the drive transistor Tr2. As shown in the figure, when the Vth cancel period starts, a pulse is applied to the scanning line AZ, the switching transistor Tr5 is turned on, and the gate potential of Tr2 rises. Thereafter, since the pulse of the scanning line DS falls, the current supply from the power supply Vcc side is cut off. As a result, the difference between the gate potential and the source potential is reduced, and the current becomes 0 when it becomes just Vth. As a result, Vth is written into the holding capacitor C1 connected between the gate / source of Tr2. Next, when a selection pulse is applied to the scanning line WS, the sampling transistor Tr1 is turned on, and the signal Vsig is written to the holding capacitor C1 via the coupling capacitor C2. As a result, the signal Vin input to the gate of the drive transistor Tr2 is the sum of the previously written Vth and Vsig held at a predetermined gain. Further, a pulse is applied to the scanning line DS, and the switching transistor Tr7 is turned on. Accordingly, the drive transistor Tr2 supplies a drain current to the light emitting element EL according to the input gate signal Vin, and light emission starts. As a result, the anode potential of the light emitting element EL increases by ΔV, but this ΔV is added to the input signal Vin to the drive transistor Tr2 by the bootstrap effect. With the above threshold voltage canceling function and bootstrap function, even if there is a threshold voltage fluctuation of the drive transistor Tr2 or a characteristic fluctuation of the light emitting element EL, it is possible to cancel these and keep the light emission luminance constant.

  By the way, a voltage higher than that of the source is applied to the gate of the drive transistor Tr2 throughout the one-field period 1f, so that the forward bias is always applied. By continuously applying a forward bias to the gate, the threshold voltage Vth of the drive transistor Tr2 varies upward. This variation can be canceled by the threshold voltage cancel circuit 7. However, if the variation exceeds the degree, the cancel function cannot catch up, and there is a possibility that the luminance of the light emitting element EL is changed. The switching transistor Tr7 is turned on during the light emission period and is forward biased. As a result, the threshold voltage of the switching transistor Tr7 fluctuates upward, and in the worst case, the switching transistor Tr7 may always be in a cut-off state.

  FIG. 12 shows another embodiment of the pixel circuit according to the present invention. In order to cope with the problem of the pixel circuit of FIG. 11, reverse bias application for suppressing threshold voltage fluctuation is applied to the drive transistor Tr2 and the switching transistor Tr7, respectively. It has a means.

  The reverse bias applying means for the drive transistor Tr2 is composed of a switching transistor Tr4. The additional scanning line WS2 is connected to the gate of Tr4, the negative power supply Vmb is connected to the source, and the drain is connected to the gate (G) of the drive transistor Tr2. Since this scanning line WS2 is different in scanning timing from the scanning line WS1 connected to the sampling transistor Tr1 and the switching transistor Tr3, they are divided into WS1 and WS2 separately. Here, the potential of the negative power supply Vmb is set lower than the ground potential GND. Therefore, when a selection pulse is applied to WS2 at a timing that does not affect the operation of the pixel circuit, Tr4 is turned on and a reverse bias (Vmb) can be applied to the gate (G) of the drive transistor Tr2. Thereby, the threshold voltage Vth of the transistor Tr2 shifted upward by continuous application of forward bias can be corrected downward.

  The reverse bias applying means for the switching transistor Tr7 is incorporated in the drive scanner 3 (see FIG. 1) connected to the scanning line DS. In the light emission period, a forward bias is applied to the gate of the switching transistor Tr7 via the scanning line DS, and the drain current flows from Vcc toward GND. When the non-light emission period starts, the potential of the scanning line DS becomes GND or lower, and a reverse bias is applied to the switching transistor Tr7. Thereby, the upward fluctuation of the threshold voltage of Tr7 can be corrected downward.

  FIG. 13 is a timing chart for explaining the operation of the pixel circuit shown in FIG. The pulse applied to the scanning line WS1 is represented by ws1, the pulse applied to the scanning line WS2 is represented by ws2, the pulse applied to the scanning line AZ is represented by az, and the pulse applied to the scanning line DS is represented by ds. It represents. Further, fluctuations in the gate potential (G), drain potential (D), and source potential (S) of the drive transistor Tr2 are shown superimposed on the level change of the pulse ds. Note that the drain potential (D) of the drive transistor Tr2 is simultaneously the source potential of the switching transistor Tr7.

  In the Vth cancel period, the pulse az is applied to the transistors Tr5 and Tr6, and the threshold voltage Vth of the drive transistor Tr2 is detected. This detected Vth is held in the holding capacitor C1 as a difference between the gate potential (G) and the source potential (S) of Tr2. Next, when the pulse ws1 is applied to the sampling transistor Tr1 and the switching transistor Tr3, the video signal Vsig is sampled and written to the holding capacitor C1 via the coupling capacitor C2. The sum of Vth and Vsig written in the storage capacitor C1 is shown in the timing chart as the difference between the gate potential (G) and the source potential (S) of Tr2. Further, when the pulse ds is applied to the switching transistor Tr7 during the light emission period, a drain current flows to the light emitting element EL through the drive transistor Tr2. As a result, the source potential (S) rises, but the potential difference from the gate potential (G) is kept constant by the bootstrap function. As the source potential (S) increases, the drain potential (D) also increases. Although this drain potential (D) is the source potential of the switching transistor Tr7, the amplitude of the pulse DS is set sufficiently higher than the drain potential (D), so that the forward bias necessary for the on operation of the transistor Tr7 is set. Va can be applied. Thereafter, when the non-light emission period starts, the pulse DS is switched to the low level, and the transistor Tr7 is cut off. The drain potential (D) of the drive transistor Tr2 drops from the Vcc side to GND due to the interruption of the drain current. At this time, since the low level of the pulse ds is set lower than GND, the reverse bias Vb is applied to the gate of the switching transistor Tr7. In the non-light emitting period, the pulse ws2 is applied to the gate of the transistor Tr4. As a result, Tr4 becomes conductive and the reverse bias Vmb is applied to the gate (G) of the drive transistor Tr2. As is clear from the above description, since reverse bias is applied to the drive transistor Tr2 and the switching transistor Tr7 at appropriate timings, fluctuations in the respective threshold voltages can be suppressed.

  FIG. 14 shows another embodiment of the pixel circuit according to the present invention, which is an improved version of the previous embodiment shown in FIG. For ease of understanding, parts corresponding to those in the embodiment shown in FIG. 12 are given corresponding reference numerals. Similar to the previous embodiment, this embodiment also includes a threshold voltage cancel circuit. As described above, this threshold voltage cancel circuit detects the threshold voltage of the drive transistor Tr2 prior to energization of the load element EL, and holds the potential necessary for canceling the influence in the holding capacitor C1 in advance. This is applied to the gate of the drive transistor Tr2. This threshold voltage cancel circuit includes a detection transistor Tr5 for detecting the threshold voltage of the drive transistor Tr2. The source / drain of the detection transistor Tr5 is connected between the drain (D) and the gate (G) of the drive transistor Tr2, and the gate is maintained at a negative potential except when the threshold voltage of the drive transistor Tr2 is detected. ing. In other words, a pulse is applied to the gate of the detection transistor Tr5 via the scanning line AZ, and the threshold voltage of the drive transistor Tr2 is detected and written to the storage capacitor C1. The reference level of the scanning line AZ is set to a negative potential. Therefore, the gate of the detection transistor Tr5 is maintained at a negative potential except when the threshold voltage of the drive transistor Tr2 is detected. As a feature of the present embodiment, the switching transistor Tr4 for applying a reverse bias has a source connected to the gate of the detection transistor Tr5 and uses a negative potential applied thereto as a reverse bias. In other words, the scanning line AZ is connected to the source of the switching transistor Tr4 for applying reverse bias. As a result, it is not necessary to prepare a separate power supply line with a negative potential Vmb, and the layout of the pixel circuit can be simplified. Thus, in this improved version, the node on the source side of the switching transistor Tr4 is not connected to the negative potential Vmb, but is connected to the scanning line AZ. Since the scanning line AZ is at a negative potential when the switching transistor Tr4 is on during the reverse bias application period, the same effect as the embodiment of FIG. 12 can be obtained, and the threshold fluctuation of the drive transistor Tr2 can be easily changed. It is possible to suppress.

It is a block diagram which shows the general structure of an active matrix display apparatus and a pixel circuit. It is a circuit diagram which shows the reference example of a pixel circuit. 3 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 2. It is a graph which shows the time-dependent change of the IV characteristic of an organic EL element. It is a graph which shows a time-dependent change of the operating point of a drive transistor and an organic EL element. It is a circuit diagram which shows the other reference example of a pixel circuit. 7 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 6. It is a graph which shows the device characteristic of a thin-film transistor. It is a schematic diagram showing an embodiment of a pixel circuit according to the present invention. 2 is a circuit diagram and a timing chart showing a prototype of a pixel circuit according to the present invention. It is a schematic diagram which shows another reference example of a pixel circuit. It is a circuit diagram which shows other embodiment of the pixel circuit which concerns on this invention. It is a timing chart with which it uses for operation | movement description of embodiment shown in FIG. FIG. 6 is a circuit diagram showing a further improved form of the pixel circuit according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array, 2 ... Horizontal selector, 3 ... Drive scanner, 4 ... Write scanner, 5 ... Pixel circuit, 9 ... Reverse bias application means

Claims (2)

A pixel circuit disposed at each of the intersections of the row-shaped scanning lines and the column-shaped signal lines,
Including at least a thin film type sampling transistor, a storage capacitor, a thin film type drive transistor and a load element,
When the gate is selected by the scanning line, the sampling transistor conducts between the source and the drain, samples the signal from the signal line, and holds the sampled signal in the storage capacitor,
The drive transistor receives a forward bias having a positive polarity with respect to a source based on a signal potential held in the storage capacitor, and energizes the load element with a current flowing between the source / drain in accordance with the forward bias. ,
A reverse bias applying means for applying a reverse bias having a negative polarity with respect to the source to the gate of the drive transistor for a predetermined time, and changing a threshold voltage of the drive transistor caused by the application of the forward bias for a predetermined time; Correct by applying reverse bias,
The reverse bias applying means includes a thin film type switching transistor that is driven on / off to apply a reverse bias to the gate of the drive transistor,
The switching transistor is turned on in response to a forward-biased gate pulse, and starts applying a reverse bias to the gate of the drive transistor,
The time during which the switching transistor is in an on state is set shorter than a predetermined time for applying a reverse bias, to reduce fluctuations in the threshold voltage of the switching transistor itself due to application of a forward bias gate pulse ,
The switching transistor has a drain connected to the gate of the drive transistor, a source connected to a negative potential power source set lower than the source potential of the drive transistor, and when the gate pulse is input, between the drain and the source Is turned on and the negative potential is applied as a reverse bias to the gate of the drive transistor, and the negative potential is written to the storage capacitor,
The holding capacitor maintains a reverse bias applied to the drive transistor for a predetermined time by the held negative potential after the switching transistor is turned off,
A threshold voltage cancel circuit for detecting the threshold voltage of the drive transistor prior to energization of the load element and holding the potential necessary for canceling the fluctuation in the holding capacitor and applying the potential to the gate of the drive transistor; And
The threshold voltage cancellation circuit includes a detection transistor for detecting a threshold voltage of the drive transistor,
The detection transistor has its source / drain connected between the drain and gate of the drive transistor, and the gate is maintained at a negative potential except when detecting the threshold voltage of the drive transistor,
The switching transistor has a source connected to the gate of the detection transistor and uses a negative potential applied thereto as a reverse bias.
Pixel circuit. The pixel circuit is composed of a row-shaped scanning line, a column-shaped signal line, and a pixel circuit disposed at each of the intersections. The pixel circuit includes at least a thin-film sampling transistor, a storage capacitor, and a thin-film drive transistor. And the light emitting element, and when the gate is selected by the scanning line, the sampling transistor conducts between the source and the drain, samples the video signal from the signal line, and holds the sampled video signal in the storage capacitor The drive transistor receives a forward bias having a positive polarity with respect to a source based on a signal potential held in the storage capacitor, and the light emitting element is driven by a current flowing between the source / drain in accordance with the forward bias. In a display device that performs energization and displays,
The pixel circuit includes reverse bias applying means for applying a reverse bias having a negative polarity with respect to the source to the gate of the drive transistor for a predetermined time, and the threshold voltage fluctuation of the drive transistor caused by the application of the forward bias Is corrected by applying the reverse bias for a predetermined time,
The reverse bias applying means includes a thin film type switching transistor that is driven on / off to apply a reverse bias to the gate of the drive transistor,
The switching transistor is turned on in response to a forward-biased gate pulse, and starts applying a reverse bias to the gate of the drive transistor,
The time during which the switching transistor is in an ON state is set shorter than a predetermined time for applying a reverse bias, and the variation in threshold voltage of the switching transistor itself due to the application of a forward bias gate pulse is reduced .
The switching transistor has a drain connected to the gate of the drive transistor, a source connected to a negative potential power source set lower than the source potential of the drive transistor, and when the gate pulse is input, between the drain and the source Is turned on and the negative potential is applied as a reverse bias to the gate of the drive transistor, and the negative potential is written to the storage capacitor,
The holding capacitor maintains a reverse bias applied to the drive transistor for a predetermined time by the held negative potential after the switching transistor is turned off,
A threshold voltage cancel circuit for detecting a threshold voltage of the drive transistor prior to energization of the light-emitting element, holding a potential necessary for canceling the fluctuation in the storage capacitor, and applying the potential to the gate of the drive transistor; And
The threshold voltage cancellation circuit includes a detection transistor for detecting a threshold voltage of the drive transistor,
The detection transistor has its source / drain connected between the drain and gate of the drive transistor, and the gate is maintained at a negative potential except when detecting the threshold voltage of the drive transistor,
The switching transistor has a source connected to the gate of the detection transistor and uses a negative potential applied thereto as a reverse bias.
Display device.

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