JP4501059B2 - Pixel circuit and display device - Google Patents

Description

  The present invention relates to a pixel circuit that current-drives a load element arranged for each pixel. The pixel circuit is a display device in which the pixel circuits are arranged in a matrix. In particular, a so-called field-effect transistor provided in each pixel circuit controls the amount of current supplied to a load element such as an organic EL light-emitting element. The present invention relates to an active matrix display device.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and a high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a liquid crystal display or the like in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit.
USP 5,684,365 JP-A-8-234683

  A conventional pixel circuit is disposed at a portion where a row scanning line and a column signal line intersect each other. Each pixel circuit includes at least a thin film type sampling transistor, a storage capacitor, a thin film type drive transistor, and a load element such as a light emitting element. When the gate of the sampling transistor is selected by the scanning line, the source / drain is made conductive and the video signal is sampled from the signal line. The sampled signal is written and held in the holding capacitor. The drive transistor has a gate connected to a storage capacitor, and one source / drain connected to a load element such as a light emitting element. The gate of the drive transistor receives a forward bias that is positive with respect to the source by the signal potential held in the holding capacitor. The drive transistor causes a current to flow between the source and drain in accordance with the forward bias, and energizes the light emitting element. In general, the luminance of a light-emitting element is proportional to the amount of current supplied. Further, the energization amount of the drive transistor is controlled by the signal potential written in the storage capacitor. Therefore, the light emitting element emits light with a luminance corresponding to the video signal.

The operating characteristic of the drive transistor is expressed by the following equation.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ²
In this transistor characteristic formula, Ids represents the drain current. Vgs represents a voltage applied to the gate with reference to the source. Vth is the threshold voltage of the transistor. In addition, μ represents the mobility of the semiconductor thin film constituting the channel of the transistor, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from this transistor characteristic equation, when the thin film transistor operates in the saturation region, if the gate voltage Vgs exceeds the threshold voltage Vth and increases to the positive side, the transistor is turned on and the drain current Ids flows. In other words, when the forward bias (Vgs) exceeds the threshold voltage (Vth), it is turned on. Conversely, when Vgs falls below Vth, the thin film transistor is cut off and the drain current Ids does not flow.

  By the way, light-emitting elements such as organic EL elements are not necessarily stable in current-voltage characteristics and tend to deteriorate over time. Due to this deterioration over time, the operating point of the drive transistor varies, and the source potential varies even when the same signal voltage is applied to the gate. This is because the constant current source composed of the drive transistor is a source follower circuit. Since the source potential fluctuates, the gate voltage Vgs of the drive transistor eventually changes, and the value of the drain current Ids fluctuates. As a result, since the amount of current applied to the light emitting element changes, the light emission luminance also changes. As described above, when the current-voltage characteristics of the light emitting element deteriorate, there is a problem that the light emission luminance changes with time in the source follower circuit.

  SUMMARY OF THE INVENTION In view of the above-described problems of the prior art, an object of the present invention is to provide a pixel circuit, a display device, and a driving method thereof capable of correcting a temporal deterioration of current-voltage characteristics of a load element such as a light emitting element. To do. In order to achieve this purpose, the following measures were taken. That is, the present invention is arranged at each portion where the row-shaped scanning line and the column-shaped signal line intersect each other, and includes at least a sampling transistor, a holding capacitor, a drive transistor, a load element, and a switching transistor. When the gate is selected by the scanning line, the source / drain is conducted to sample the signal from the signal line and hold the sampled signal in the holding capacitor, and the drive transistor holds the gate in the holding capacitor The load element is energized with a current flowing between the source and drain in accordance with the signal potential, and one end of the storage capacitor is connected to the source of the sampling transistor and the gate of the drive transistor, One end of the switching transistor is connected to the source of the drive transistor. The transistor is turned on during sampling to connect the other end of the storage capacitor together with the source of the drive transistor to the ground potential, and is turned off when the load element is energized to ground the other end of the storage capacitor together with the source of the drive transistor. A pixel circuit that performs a bootstrap operation that feeds back a change in the source potential of the drive transistor that is separated from the potential and thus increases with energization of the load element, to the gate of the drive transistor, A field effect type first capacitor element and a second capacitor element are connected in series with each other at an intermediate node, and are necessary for maintaining the field effect of the first capacitor element and the second capacitor element at the time of sampling. It has a transistor for setting that sets the potential at the intermediate node And features.

  In one aspect, the first capacitor element has a positive electrode connected to the gate of the drive transistor, a negative electrode connected to the intermediate node, and the second capacitor element has a positive electrode connected to the source of the drive transistor. One negative electrode connected to the intermediate node is connected to the intermediate node, and the setting transistor has a predetermined negative potential required to maintain the field effect of the first capacitor element and the second capacitor element. set. In another aspect, the first capacitor element has a negative electrode connected to the gate of the drive transistor, a positive electrode connected to the intermediate node, and the second capacitor element has a negative electrode connected to the source of the drive transistor. One positive electrode connected to the intermediate node is connected to the intermediate node, and the setting transistor has a predetermined positive potential necessary for maintaining the field effect of the first and second capacitive elements. Set to.

  According to another aspect of the present invention, there is provided a display device comprising a row-shaped scanning line, a column-shaped signal line, and a pixel circuit disposed at each of the intersecting portions. The sampling transistor comprises a capacitor, a drive transistor, a light emitting element, a switching transistor, and a setting transistor. When the gate is selected by the scanning line, the source / drain conducts and the signal is sampled and sampled from the signal line. And the drive transistor receives the signal potential held in the holding capacitor and energizes the light emitting element with a current flowing between the source / drain according to the signal potential, One end of the storage capacitor is the source of the sampling transistor and the drive transistor. The switching transistor is turned on during sampling and the other end of the storage capacitor is connected to the ground potential together with the source of the drive transistor, and the light emitting element And the other end of the storage capacitor together with the source of the drive transistor is disconnected from the ground potential, so that the fluctuation of the source potential of the drive transistor that rises when the light emitting element is energized is reduced. A bootstrap operation for feeding back to the gate is performed, and the storage capacitor is composed of a field effect type first capacitor element and a second capacitor element connected in series at an intermediate node, and the setting transistor operates in accordance with sampling. The first capacitor element and the second capacitor element Characterized by setting the intermediate node potential required to maintain the field effect.

  In one aspect, the first capacitor element has a positive electrode connected to the gate of the drive transistor, a negative electrode connected to the intermediate node, and the second capacitor element has a positive electrode connected to the source of the drive transistor. One negative electrode connected to the intermediate node is connected to the intermediate node, and the setting transistor has a predetermined negative potential required to maintain the field effect of the first capacitor element and the second capacitor element. set. In another aspect, the first capacitor element has a negative electrode connected to the gate of the drive transistor, a positive electrode connected to the intermediate node, and the second capacitor element has a negative electrode connected to the source of the drive transistor. One positive electrode connected to the intermediate node is connected to the intermediate node, and the setting transistor has a predetermined positive potential necessary for maintaining the field effect of the first and second capacitive elements. Set to.

  According to the present invention, the bootstrap function is incorporated in the pixel circuit. That is, the switching transistor is turned on when the video signal is sampled, and the holding capacitor is connected to the ground potential together with the source of the drive transistor, and the sampled video signal is written to the holding capacitor, while the switching transistor is turned off when the load element is energized At the same time, the storage capacitor is disconnected from the ground potential. As a result, the fluctuation of the source potential of the drive transistor that rises with energization of the load element is fed back to the gate of the drive transistor. With this bootstrap function, a load element such as an organic EL light emitting element can be driven with a constant current, and luminance deterioration due to a change with time of the current-voltage characteristic of the light emitting element can be prevented. At this time, as the storage capacitor, a field effect type first capacitor element and second capacitor element connected in series at an intermediate node is used. In accordance with the sampling, a potential necessary for maintaining the field effect of the first capacitor element and the second capacitor element is set at the intermediate node. As a result, it is possible to use a field-effect capacitive element that is advantageous in terms of cost instead of a normal thin-film storage capacitor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, in order to clarify the background of the present invention, a general configuration of an active matrix display device and a pixel circuit included therein will be described as a reference example with reference to FIG. As shown in the figure, the active matrix display device includes a pixel array 1 as a main part and a peripheral circuit group. The peripheral circuit group includes a horizontal selector 2, a drive scanner 3, a write scanner 4, and the like.

  The pixel array 1 is composed of row-like scanning lines WS and column-like signal lines DL and pixel circuits 5 arranged in a matrix at portions where they intersect. The signal line DL is driven by the horizontal selector 2. The scanning line WS is scanned by the write scanner 4. Note that another scanning line DS is also wired in parallel with the scanning line WS, and this is scanned by the drive scanner 3. Each pixel circuit 5 samples a signal from the signal line DL when selected by the scanning line WS. Further, when selected by the scanning line DS, the load element is driven according to the sampled signal. This load element is a current drive type light emitting element formed in each pixel circuit 5.

  FIG. 2 is a reference diagram showing a basic configuration of the pixel circuit 5 shown in FIG. The pixel circuit 5 includes a sampling thin film transistor (sampling transistor Tr1), a drive thin film transistor (drive transistor Tr2), a switching thin film transistor (switching transistor Tr3), a storage capacitor Cs, a load element (organic EL light emitting element), and the like. Yes.

  The sampling transistor Tr1 becomes conductive when selected by the scanning line WS, samples the video signal from the signal line DL, and holds it in the holding capacitor Cs. The drive transistor Tr2 controls the energization amount to the light emitting element EL according to the signal potential held in the holding capacitor Cs. The switching transistor Tr3 is controlled by the scanning line DS, and turns on / off energization to the light emitting element EL. That is, the drive transistor Tr2 controls the light emission luminance (brightness) of the light emitting element EL according to the energization amount, while the switching transistor Tr3 controls the light emission time of the light emitting element EL. With these controls, the light emitting element EL included in each pixel circuit 5 exhibits luminance corresponding to the video signal, and a desired display is displayed on the pixel array 1.

  FIG. 3 is a timing chart for explaining operations of the pixel array 1 and the pixel circuit 5 shown in FIG. At the beginning of one field period (1f), a selection pulse ws [1] is applied to the pixel circuits 5 in the first row during one horizontal period (1H) via the scanning line WS, and the sampling transistor Tr1 is turned on. As a result, the video signal is sampled from the signal line DL and written into the storage capacitor Cs. One end of the storage capacitor Cs is connected to the gate of the drive transistor Tr2. Therefore, when the video signal is written into the storage capacitor Cs, the gate potential of the drive transistor Tr2 rises according to the written signal potential. At this time, the selection pulse ds [1] is applied to the switching transistor Tr3 via another scanning line DS. During this time, the light emitting element EL continues to emit light. In the second half of the one-field period 1f, ds [1] is at a low level, so that the light emitting element EL is in a non-light emitting state. By adjusting the duty of the pulse ds [1], the ratio between the light emission period and the non-light emission period can be adjusted, and a desired screen luminance can be obtained. In the next horizontal period, scanning signal pulses ws [2] and ds [2] are applied to the pixel circuits in the second row from the scanning lines WS and DS, respectively.

  FIG. 4 is a graph showing a change with time of current-voltage (IV) characteristics of an organic EL element incorporated in the pixel circuit 5 as a light emitting element. In the graph, the curve indicated by the solid line indicates the characteristic in the initial state, and the curve indicated by the broken line indicates the characteristic after change with time. Generally, the IV characteristic of an organic EL element deteriorates over time as shown in the graph. The pixel circuit of the reference example shown in FIG. 2 has a problem that the drive transistor has a source follower configuration and cannot cope with a change in the IV characteristic of the EL element with time, resulting in deterioration of light emission luminance.

  FIG. 5A is a graph showing operating points of the drive transistor Tr2 and the light emitting element EL in the initial state. In the figure, the vertical axis represents the drain-source voltage Vds of the drive transistor Tr2, and the vertical axis represents the drain-source current Ids. As illustrated, the source potential is determined by the operating point of the drive transistor Tr2 and the light emitting element EL, and the voltage value varies depending on the gate voltage. Since the drive transistor Tr2 operates in the saturation region, the drive current Ids having a current value defined by the above-described transistor characteristic equation is supplied with respect to Vgs corresponding to the source voltage at the operating point.

  However, the IV characteristic of the light emitting element EL deteriorates with time as shown in FIG. As shown in FIG. 5B, the operating point changes due to the deterioration with time, and the source voltage of the transistor changes even when the same gate voltage is applied. As a result, the gate-source voltage Vgs of the drive transistor Tr2 changes, and the flowing current value fluctuates. At the same time, the value of the current flowing through the light emitting element EL also changes. When the IV characteristic of the light emitting element EL changes in this way, the luminance of the light emitting element EL changes with time in the pixel circuit having the source follower configuration of the reference example shown in FIG.

  FIG. 6 shows another reference example of the pixel circuit, which addresses the problems of the previous reference example shown in FIG. In order to facilitate understanding, parts corresponding to those in the reference example of FIG. The improvement is that the connection of the switching transistor Tr3 is changed, thereby realizing a bootstrap function. Specifically, the source of the switching transistor Tr3 is grounded, the drain is connected to the source (S) of the drive transistor Tr2 and one electrode of the storage capacitor Cs, and the scanning line DS is connected to the gate. The other electrode of the storage capacitor Cs is connected to the gate (G) of the drive transistor Tr2.

  FIG. 7 is a timing chart for explaining the operation of the pixel circuit 5 shown in FIG. In the first horizontal period 1H in the field period 1f, the selection pulse ws [1] is sent from the write scanner 4 to the pixel circuit 5 in the first row via the scanning line WS. The numbers in [] correspond to the row numbers of the pixel circuits arranged in a matrix. When the selection pulse is applied, the sampling transistor Tr1 is turned on, and the input signal Vin is sampled from the signal line DL and written to the storage capacitor Cs. At this time, the selection pulse ds [1] is applied to the switching transistor Tr3 from the drive scanner 3 via the scanning line DS, and the switching transistor Tr3 is in the ON state. Accordingly, one electrode of the storage capacitor Cs and the source (S) of the drive transistor Tr2 are at the GND level. Since the input signal Vin is written to the storage capacitor Cs with reference to the GND level, the gate potential (G) of the drive transistor Tr2 becomes Vin.

  Thereafter, the selection pulse ws [1] for the sampling transistor Tr1 is released, and then the selection pulse ds [1] for the switching transistor Tr3 is also released. As a result, the sampling transistor Tr1 and the switching transistor Tr3 are turned off. Therefore, the source (S) of the drive transistor Tr2 is disconnected from the GND and becomes a connection node for the anode of the light emitting element EL.

  The drive transistor Tr2 receives the input signal Vin held in the holding capacitor Cs at the gate, and causes a drain current to flow from the Vcc side toward the GND side according to the value. By this energization, the light emitting element EL emits light. At this time, a voltage drop occurs due to energization of the light emitting element EL, but the source potential (S) rises from the GND side toward the Vcc side accordingly. In the timing chart of FIG. 7, this increase is represented by ΔV. One end of the storage capacitor Cs is connected to the source (S) of Tr2, and the other end is connected to a high impedance gate (G). Therefore, when the source potential (S) is increased by ΔV, the gate potential (G) is increased by that amount, and the net input signal Vin is maintained as it is. Therefore, even if the source potential (S) varies by ΔV according to the current-voltage characteristics of the light emitting element EL, the gate voltage Vgs = Vin is always established, and the drain current is kept constant. That is, the drive transistor Tr2 functions as a constant current source for the light emitting element EL by the bootstrap function described above, despite the source follower configuration.

  Thereafter, when the selection pulse ds [1] returns to the high level, the switching transistor Tr3 is turned on, and the current to be supplied to the light emitting element EL is bypassed, so that the light emitting state is turned off. When the field period 1f ends in this way, the next field period starts, and the selection pulse ws [1] is applied to the sampling transistor Tr1 again to sample the input video signal Vin *. Since the level of the sampled video signal may be different between the previous field period and the current field period, the input video signal Vin is marked with an asterisk (*) to distinguish it. Note that such video signal writing and light emission operations are performed line-sequentially (in units of rows). Therefore, the selection pulses ws [1], ws [2]... Are sequentially applied to each row of pixels. Similarly, selection pulses ds [1], ds [2]... Are sequentially applied.

  FIG. 8A shows a cross-sectional structure of the storage capacitor Cs shown in FIG. In addition, the structure of the sampling transistor Tr1 connected to the storage capacitor Cs is also shown. As shown, the sampling transistor Tr1 is a thin film field effect transistor (TFT). The storage capacitor Cs has a thin film structure so that it can be produced by the same process as this TFT. Specifically, a gate electrode 11 is formed of a metal film on an insulating substrate 10 such as glass. A gate insulating film 12 such as silicon dioxide is formed so as to cover this, and a semiconductor film 13 such as an amorphous silicon film or a polysilicon film is formed thereon. Further thereon, a drain electrode 14 and a source electrode 15 are formed of aluminum or the like. A bottom gate type sampling transistor Tr1 is configured by such a stacked structure.

  On the other hand, the storage capacitor Cs is composed of a pair of electrodes 16 and 17 and an insulating film 12 as a dielectric layer held therebetween. At that time, the lower electrode 16 is patterned simultaneously with the gate electrode 11. The insulating film 12 functions as a gate insulating film on the transistor Tr1 side and functions as a dielectric film on the storage capacitor Cs side. The upper electrode 17 is formed simultaneously with the source electrode 15.

  However, when forming the upper electrode 17, it is necessary to previously remove the unnecessary semiconductor film 13 from the portion where the storage capacitor Cs is formed by etching. In order to perform this etching process, an additional process is required, which is a problem from the viewpoint of process rationalization.

  (B) shows an example in which a field effect type storage capacitor Cs is used instead of the thin film type storage capacitor Cs shown in FIG. For easy understanding, the parts corresponding to the parts shown in FIG. As shown in the figure, the field effect type storage capacitor Cs includes a positive electrode 16, a negative electrode 17, and an insulating film 12 held between the two electrodes. The positive electrode 16 is patterned simultaneously with the gate electrode 11 of the transistor Tr1, and the negative electrode 17 is patterned simultaneously with the drain electrode 14 and the source electrode 15 of the transistor Tr1. Unlike the normal storage capacitor Cs shown in (A), the field-effect storage capacitor Cs does not need to remove the semiconductor thin film 13, and therefore does not require an additional etching step. Therefore, it is possible to rationalize the manufacturing process as compared with a normal thin film type storage capacitor.

  By the way, the field effect type storage capacitor Cs shown in (B) has an N-type semiconductor film 13 interposed between the positive electrode 16 and the negative electrode 17 in addition to the insulating film 12 functioning as a dielectric. Yes. In order to make the field effect type storage capacitor having such a structure electrically function, the N type semiconductor film 13 needs to be formed into an electrode. In other words, it is necessary to invert the semiconductor film 13 to form a depletion layer. Therefore, it is necessary to apply a negative potential lower than a predetermined threshold voltage required for inversion of the semiconductor film 13 to the negative electrode 17 with respect to the positive electrode 16.

  However, when the pixel circuit according to the reference example shown in FIG. 6 is viewed, a predetermined video signal is written in the storage capacitor Cs. This video signal changes between 0V and several tens of volts. In such a situation, even if the normal thin film storage capacitor is replaced with a field effect storage capacitor, if the level of the video signal to be written is close to 0 V, the required potential difference between the positive electrode and the negative electrode is increased. Since it cannot be secured, the field effect type storage capacitor not only functions as an electrical capacitor but also leaks, resulting in a reduction in image quality.

  The present invention has been made based on such a situation, and an object of the present invention is to replace a storage capacitor with a field effect type advantageous in manufacturing process in a pixel circuit having a bootstrap function. FIG. 9 shows a pixel circuit according to an embodiment of the present invention, which is made to achieve such an object. As shown in the figure, this pixel circuit is arranged at a portion where the row scanning lines WS and DS intersect with the column signal line DL, and at least the sampling transistor Tr1, the holding capacitor Cs, the drive transistor Tr2, and the load element EL. And a switching transistor Tr3. When the gate is selected by the scanning line WS, the sampling transistor Tr1 conducts between the source and the drain, samples the video signal Vsig from the signal line DL, and holds the sampled video signal Vsig in the storage capacitor Cs. In the drive transistor Tr2, the gate (G) receives the signal potential held in the holding capacitor Cs, and energizes the load element EL with a current flowing between the source (S) / drain according to the signal potential. The holding capacitor Cs has one end connected to the source of the sampling transistor Tr1 and the gate (G) of the drive transistor Tr2, and the other end connected to the source (S) of the drive transistor Tr2. The switching transistor Tr3 is turned on during sampling and connects the other end of the storage capacitor Cs to the ground potential Vss together with the source (S) of the drive transistor Tr2. The switching transistor Tr3 is turned off when the load element EL is energized, disconnects the other end of the storage capacitor Cs together with the source (S) of the drive transistor Tr2 from the ground potential Vss, and thus rises as the load element EL is energized. A bootstrap operation is performed to feed back the fluctuation of the source (S) potential of the drive transistor Tr2 to the gate (G) of the drive transistor Tr2.

  As a feature of the present invention, the storage capacitor Cs includes a field effect type first capacitor element Cs1 and a second capacitor element Cs2 connected in series with each other at an intermediate node (X). The setting transistor Tr4 is connected to the intermediate node (X). The transistor Tr4 operates in accordance with the sampling, and sets a potential −Vx necessary for maintaining the field effect of the first capacitor element Cs1 and the second capacitor element Cs2 to the intermediate node (X). Focusing on the first capacitor element Cs1, the setting potential -Vx is set lower than a value obtained by subtracting the threshold voltage of Cs1 from the potential of the video signal Vsig. Focusing on the second capacitive element Cs2, the setting voltage -Vx is set to a voltage lower than the value obtained by subtracting the threshold voltage of Cs2 from the ground potential Vss.

  Looking specifically at FIG. 9, in the first capacitor element Cs1, the positive electrode (+) is connected to the gate (G) of the drive transistor Tr2, while the negative electrode (−) is connected to the intermediate node (X). . The second capacitor element Cs2 has a positive electrode (+) connected to the source (S) of the drive transistor Tr2, and a negative electrode (−) connected to the intermediate node (X). The setting transistor Tr4 sets a predetermined negative potential −Vx necessary for maintaining the field effect of the first capacitor element Cs1 and the second capacitor element Cs2 at the intermediate node (X).

  FIG. 10 is a timing chart for explaining the operation of the pixel circuit shown in FIG. For easy understanding, portions corresponding to the timing chart of the reference example shown in FIG. In the timing chart of FIG. 10, in addition to the gate potential (G) and source potential (S) of the drive transistor, the intermediate potential (X) of the storage capacitor is also listed. First, in the signal writing period, the sampling transistor Tr1 is turned on in response to the pulse ws, and the input signal Vin = Vgs is written to the storage capacitor Cs. At the same time, the transistor Tr4 is turned on in response to the gate pulse ws, and a predetermined setting potential -Vx is written to the intermediate node (X) of the storage capacitor Cs. Thereafter, when the light emission period starts, the gate pulse ds falls and a bootstrap operation is performed. As a result, both the source potential (S) and the gate potential (G) of the drive transistor Tr2 rise by ΔV. At the same time, the intermediate potential (X) also increases by ΔV. In this manner, the relative level relationship among the gate potential, the source potential, and the intermediate potential is maintained even when the bootstrap operation is started. As a result, the field effect capacitive elements Cs1 and Cs2 electrically function as capacitors at all timings and all operating points.

  FIG. 11 is a cross-sectional view of a principal part showing a specific configuration of the pixel circuit shown in FIG. As illustrated, a sampling transistor Tr1, a first capacitor element Cs1, and a second capacitor element Cs2 are formed on an insulating substrate 10 such as glass. The sampling transistor Tr1 includes a gate electrode 11, a gate insulating film 12 formed thereon, a semiconductor film 13 formed thereon, and a drain electrode 14 and a source electrode 15 formed thereon. The first capacitor element Cs1 includes a positive electrode 16 and a negative electrode 17 and an insulating film 12 and a semiconductor film 13 held between the positive electrode 16 and the negative electrode 17. The positive electrode 16 is connected to the source electrode 15 of the sampling transistor Tr1 through a contact hole opened in the semiconductor film 13 and the insulating film 12. The negative electrode 17 of the first capacitive element Cs1 is extended to be the negative electrode of the second capacitive element Cs2. Although not shown, the negative electrode 17 is connected to the setting transistor Tr4 via an intermediate node (X). A positive electrode 16 is formed below the negative electrode 17 of the second capacitor element Cs2 with the semiconductor thin film 13 and the insulating film 12 therebetween. Although not shown, the positive electrode 16 is connected to the drain of the switching transistor Tr3.

  As is apparent from FIG. 11, the gate electrode 11 of the transistor Tr1, the positive electrode 16 of the first capacitor element Cs1, and the positive electrode 16 of the second capacitor element Cs2 are all formed of the same metal film. The drain electrode 14 and the source electrode 15 of the sampling transistor Tr1 and the negative electrodes 17 of the first capacitor element Cs1 and the second capacitor element Cs2 are both formed of the same metal layer.

  FIG. 12 is a circuit diagram showing another embodiment of the pixel circuit according to the present invention. In order to facilitate understanding, parts corresponding to those of the previous embodiment shown in FIG. 9 are given corresponding reference numerals. The difference is that the polarity of the connection of the field effect type capacitive elements Cs1, Cs2 is reversed. That is, in the first capacitive element Cs1, the negative electrode (−) is connected to the gate (G) of the drive transistor Tr2, while the positive electrode (+) is connected to the intermediate node (X). The second capacitor element Cs2 has a negative electrode (−) connected to the source (S) of the drive transistor Tr2, while a positive electrode (+) connected to the intermediate node (X). The setting transistor Tr4 sets a predetermined positive potential + Vx necessary for maintaining the field effect of the first capacitor element Cs1 and the second capacitor element Cs2 to the intermediate node (X).

  FIG. 13 is a cross-sectional view of a main part showing a specific configuration of the pixel circuit shown in FIG. 12, and shows the sampling transistor Tr1, the first capacitor element Cs1, and the second capacitor element Cs2. In order to facilitate understanding, portions corresponding to those of the previous embodiment shown in FIG. 11 are denoted by corresponding reference numerals. The source electrode 15 of the transistor Tr1 is extended to constitute the negative electrode 17 of the first capacitor element Cs1. Below that, the positive electrode 16 of Cs1 is arranged via the semiconductor film 13 and the insulating film 12. The positive electrode 16 is extended and serves as the positive electrode 16 of the second capacitor element Cs2. The positive electrode 16 common to Cs1 and Cs2 is electrically connected to the intermediate node (X) through a contact hole opened in the semiconductor film 13 and the insulating film 12. A negative electrode 17 is formed above the positive electrode 16 of the second capacitor element Cs2 via the insulating film 12 and the semiconductor film 13. Although not shown, the negative electrode 17 is electrically connected to the drain of the switching transistor Tr3.

It is a block diagram which shows the general structure of an active matrix display apparatus and a pixel circuit. It is a circuit diagram which shows the reference example of a pixel circuit. 3 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 2. It is a graph which shows the time-dependent change of the IV characteristic of an organic EL element. It is a graph which shows a time-dependent change of the operating point of a drive transistor and an organic EL element. It is a circuit diagram which shows the other reference example of a pixel circuit. 7 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 6. It is typical sectional drawing which shows the structural example of a storage capacity. 1 is a circuit diagram illustrating an embodiment of a pixel circuit according to the present invention. 10 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 9. FIG. 10 is a partial cross-sectional view illustrating a specific configuration of the pixel circuit illustrated in FIG. 9. It is a circuit diagram which shows other embodiment of the pixel circuit which concerns on this invention. FIG. 13 is a schematic partial cross-sectional view showing a specific configuration of the pixel circuit shown in FIG. 12.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array, 2 ... Horizontal selector, 3 ... Drive scanner, 4 ... Write scanner, 5 ... Pixel circuit, Tr1 ... Sampling transistor, Tr2 ... Drive transistor, Tr3 ... Switching transistor, Tr4 ... Setting transistor, Cs ... Retention capacitor, Cs1 ... First capacitor element, Cs2 ... Second capacitor element, EL ... Load element

Claims (6)

Each of the row-shaped scanning lines and the column-shaped signal lines is arranged at each intersection, and at least includes a sampling transistor, a storage capacitor, a drive transistor, a load element, and a switching transistor.
When the gate is selected by the scanning line, the sampling transistor conducts between the source and the drain, samples a signal from the signal line, and holds the sampled signal in the storage capacitor,
The drive transistor receives a signal potential held in the storage capacitor at the gate, and energizes the load element with a current flowing between the source / drain according to the signal potential,
The storage capacitor has one end connected to the source of the sampling transistor and the gate of the drive transistor, and the other end connected to the source of the drive transistor,
The switching transistor is turned on during sampling and the other end of the storage capacitor is connected to the ground potential together with the source of the drive transistor, and is turned off when the load element is energized together with the source of the drive transistor. Is a pixel circuit that performs a bootstrap operation that feeds back a change in the source potential of the drive transistor to the gate of the drive transistor that rises with energization of the load element.
The storage capacitor comprises a field effect type first capacitor element and a second capacitor element connected in series with each other at an intermediate node,
A pixel circuit comprising a setting transistor for setting a potential necessary for maintaining the field effect of the first capacitor element and the second capacitor element at the intermediate node in accordance with sampling. The first capacitive element has a positive electrode connected to the gate of the drive transistor, a negative electrode connected to the intermediate node, and the second capacitive element has a positive electrode connected to the source of the drive transistor while negative Side electrodes connect to the intermediate node;
2. The pixel circuit according to claim 1, wherein the setting transistor sets a predetermined negative potential necessary for maintaining the field effect of the first capacitor element and the second capacitor element at the intermediate node. . The first capacitor element has a negative electrode connected to the gate of the drive transistor, while a positive electrode is connected to the intermediate node, and the second capacitor element has a negative electrode connected to the source of the drive transistor. Side electrodes connect to the intermediate node;
2. The pixel circuit according to claim 1, wherein the setting transistor sets a predetermined positive potential necessary for maintaining the field effect of the first capacitor element and the second capacitor element to the intermediate node. . A display device comprising a row-shaped scanning line, a column-shaped signal line, and a pixel circuit arranged at each of the intersecting portions,
The pixel circuit includes at least a sampling transistor, a storage capacitor, a drive transistor, a light emitting element, a switching transistor, and a setting transistor.
When the gate is selected by the scanning line, the sampling transistor conducts between the source and the drain, samples the signal from the signal line, and holds the sampled signal in the storage capacitor,
The drive transistor receives a signal potential held in the storage capacitor at the gate, and energizes the light emitting element with a current flowing between the source / drain according to the signal potential,
The storage capacitor has one end connected to the source of the sampling transistor and the gate of the drive transistor, and the other end connected to the source of the drive transistor,
The switching transistor is turned on at the time of sampling and the other end of the storage capacitor is connected to the ground potential together with the source of the drive transistor, and is turned off when the light emitting element is energized together with the source of the drive transistor and the other end of the storage capacitor. Performing a bootstrap operation of feeding back to the gate of the drive transistor the fluctuation of the source potential of the drive transistor that rises with energization of the light emitting element.
The storage capacitor comprises a field effect type first capacitor element and a second capacitor element connected in series with each other at an intermediate node,
The display device is characterized in that the setting transistor operates at the time of sampling and sets a potential necessary for maintaining the field effect of the first capacitor element and the second capacitor element to the intermediate node. The first capacitive element has a positive electrode connected to the gate of the drive transistor, a negative electrode connected to the intermediate node, and the second capacitive element has a positive electrode connected to the source of the drive transistor while negative Side electrodes connect to the intermediate node;
5. The display device according to claim 4, wherein the setting transistor sets a predetermined negative potential necessary for maintaining the field effect of the first capacitor element and the second capacitor element at the intermediate node. . The first capacitor element has a negative electrode connected to the gate of the drive transistor, while a positive electrode is connected to the intermediate node, and the second capacitor element has a negative electrode connected to the source of the drive transistor. Side electrodes connect to the intermediate node;
5. The display device according to claim 4, wherein the setting transistor sets a predetermined positive potential necessary for maintaining the field effect of the first capacitor element and the second capacitor element at the intermediate node. .

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