JP2006018168A - Pixel circuit, display apparatus and drive method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pixel circuit which compensates change with time of a drain current in a drive transistor. <P>SOLUTION: A sampling transistor Tr1 samples an input signal Vsig and holds in a holding capacitance C1. A drive transistor Tr2 supplies a drive current Ids to a light emitting element EL in accordance with the signal voltage held by the holding capacitance C1. A compensation circuit 7 includes means so as to detect a decrease in the drive current Ids through the output node B side and to feedback the detection result to the input node A side as follows: a detecting means which has a resistance component inserted between an output node B and a ground potential Vss and a capacitance component to hold a voltage drop as a detected potential induced in the resistance component by the drive current Ids passing from the output node B to the ground potential Vss; and a feedback means which compares the level of the input signal Vsig with the level of the detected potential to obtain a difference and adds the a potential in accordance with the difference to the signal potential held in the holding capacitance C1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a pixel circuit that current-drives a load element arranged for each pixel. The pixel circuit is a display device arranged in a matrix, and the amount of current supplied to a load element such as an organic EL light emitting element is controlled by an insulated gate field effect transistor provided in each pixel circuit. The present invention relates to a so-called active matrix display device.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and a high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a liquid crystal display or the like in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, the current flowing in the light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A

  A conventional pixel circuit is disposed at a portion where a row scanning line and a column signal line intersect each other. Each pixel circuit includes at least a thin film type sampling transistor, a storage capacitor, a thin film type drive transistor, and a load element such as a light emitting element. When the gate of the sampling transistor is selected by the scanning line, the source / drain is made conductive and the video signal is sampled from the signal line. The sampled signal is written and held in the holding capacitor. The drive transistor has a gate connected to a storage capacitor, and one source / drain connected to a load element such as a light emitting element. The gate of the drive transistor receives a source-referenced gate voltage by the signal potential held in the holding capacitor. The drive transistor causes a current to flow between the source and the drain in accordance with the gate voltage and energizes the light emitting element. In general, the luminance of a light-emitting element is proportional to the amount of current supplied. Further, the energization amount of the drive transistor is controlled by the gate voltage, that is, the signal potential written in the storage capacitor. Therefore, the light emitting element emits light with a luminance corresponding to the video signal.

The operating characteristic of the drive transistor is expressed by the following equation.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ²
In this transistor characteristic formula, Ids represents the drain current. Vgs represents a voltage applied to the gate with reference to the source. Vth is the threshold voltage of the transistor. In addition, μ represents the mobility of the semiconductor thin film constituting the channel of the transistor, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from this transistor characteristic equation, when the thin film transistor operates in the saturation region, if the gate voltage Vgs increases beyond the threshold voltage Vth, the thin film transistor is turned on and the drain current Ids flows. As apparent from the above transistor characteristic equation, if the gate voltage Vgs is constant, the same amount of drain current Ids should always flow through the light emitting element. However, the characteristics of the drive transistor change with time, and the drain current Ids tends to gradually decrease even when the gate voltage Vgs is constant. For this reason, there is a problem that luminance deterioration occurs with time. Since the drain current tends to decrease for each pixel, there is a problem that the uniformity of the screen is impaired.

  Currently, polysilicon transistors and amorphous silicon transistors are widely used as thin film transistors constituting drive transistors and sampling transistors. From the viewpoint of cost, an amorphous silicon transistor is more advantageous than a polysilicon transistor. However, in the case where a pixel circuit is configured with amorphous silicon transistors, all N-channel transistors are used due to limitations such as mobility. However, the mobility μ of the amorphous silicon transistor tends to decrease with time. As is apparent from the transistor characteristic equation described above, when the mobility μ decreases, the drain current Ids decreases even if the gate voltage Vgs is constant, resulting in luminance degradation. A pixel circuit formed of an amorphous silicon transistor is advantageous in terms of cost, but there is a problem that luminance deterioration occurs with a change in mobility with time and the uniformity of the screen is impaired.

  SUMMARY OF THE INVENTION In view of the above-described problems of the related art, an object of the present invention is to provide a pixel circuit and a display device that can compensate for a change with time in the drain current of a drive transistor, and a driving method thereof. In order to achieve this purpose, the following measures were taken. That is, the present invention is arranged at a portion where the scanning line and the signal line intersect, and includes at least an electro-optic element, a drive transistor, a sampling transistor, and a storage capacitor, and the gate of the drive transistor is connected to the input node. The source is connected to the output node, the drain is connected to a predetermined power supply potential, the electro-optic element has one end connected to the output node, the other end connected to the predetermined potential, and the sampling transistor is Connected between the input node and the signal line, the storage capacitor is connected to the input node, and the sampling transistor operates when selected by a scanning line and samples an input signal from the signal line And the drive transistor has the electro-optic element in accordance with the signal potential held in the storage capacitor. In the pixel circuit for supplying a driving current to, and a compensation circuit for compensating the reduction in the driving current due to temporal change of the drive transistor. The compensation circuit detects a decrease in the drive current from the output node side, and feeds back the result to the input node side, so that a resistance component inserted between the output node and a predetermined ground potential and the A detection means having a capacitance component that holds a voltage drop generated in the resistance component by the drive current flowing from the output node to the ground potential as a detection potential, and a difference between the level of the input signal and the level of the detection potential And a feedback means for adding a potential corresponding to the difference to the signal potential held in the holding capacitor.

  Specifically, the compensation circuit includes a switching transistor inserted between the output node and the electro-optic element, another switching transistor connected to the output node, the switching transistor and a predetermined ground potential. A detection transistor that is diode-connected between the output node, a detection capacitor connected in parallel with the detection transistor, a feedback capacitor connected between the output node and a predetermined intermediate node, and the intermediate node and the signal line A switching transistor inserted between the terminal node and the output node, a switching transistor inserted between the terminal node connected to one end of the storage capacitor and a predetermined ground potential, and the output node. A switching transistor inserted between the switching transistor and the terminal node and the intermediate node. It is composed of a register.

  In addition, the present invention includes a display device including row-like scanning lines, column-like signal lines, and pixel circuits arranged at portions where they intersect each other. Each pixel circuit includes at least an electro-optic element, a drive transistor, a sampling transistor, and a storage capacitor. The drive transistor has a gate connected to an input node, a source connected to an output node, and a drain connected to a predetermined power supply potential. The electro-optic element has one end connected to the output node, the other end connected to a predetermined potential, the sampling transistor connected between the input node and the signal line, and the holding A capacitor is connected to the input node, and the sampling transistor operates when selected by a scanning line, samples an input signal from the signal line and holds it in the holding capacitor, and the drive transistor holds the holding transistor A display device that performs display by supplying a drive current to the electro-optic element in accordance with a signal potential held in a capacitor Oite, the pixel circuit includes a compensation circuit to compensate for the decrease in drive current caused by the variation with time of the drive transistor. The compensation circuit detects a decrease in the drive current from the output node side, and feeds back the result to the input node side, so that a resistance component inserted between the output node and a predetermined ground potential and the A detection means having a capacitance component that holds a voltage drop generated in the resistance component by the drive current flowing from the output node to the ground potential as a detection potential, and a difference between the level of the input signal and the level of the detection potential And a feedback means for adding a potential corresponding to the difference to the signal potential held in the holding capacitor.

  Specifically, the compensation circuit includes a switching transistor inserted between the output node and the electro-optic element, another switching transistor connected to the output node, the switching transistor and a predetermined ground potential. A detection transistor that is diode-connected between the output node, a detection capacitor connected in parallel with the detection transistor, a feedback capacitor connected between the output node and a predetermined intermediate node, and the intermediate node and the signal line A switching transistor inserted between the terminal node and the output node, a switching transistor inserted between the terminal node connected to one end of the storage capacitor and a predetermined ground potential, and the output node. A switching transistor inserted between the switching transistor and the terminal node and the intermediate node. It is composed of a register.

  The present invention is arranged at a portion where the scanning line and the signal line intersect, and includes at least an electro-optic element, a drive transistor, a sampling transistor, and a storage capacitor, and the gate of the drive transistor is connected to the input node. The source is connected to the output node, the drain is connected to a predetermined power supply potential, the electro-optic element has one end connected to the output node, the other end connected to the predetermined potential, and the sampling transistor is The storage capacitor is connected between the input node and the signal line, and the storage capacitor is a driving method of a pixel circuit connected to the input node, and the sampling transistor operates when selected by a scanning line, The input signal is sampled from the signal line and held in the holding capacitor, and the drive transistor is a signal held in the holding capacitor. Supplying a driving current to the electro-optical device according to position. In order to detect a decrease in the drive current from the output node side and feed back the result to the input node side to compensate for a decrease in the drive current due to a change with time of the drive transistor, the output node and a predetermined ground A voltage drop generated in the resistance component due to the drive current flowing in the resistance component inserted between the potential and the potential is obtained as a detection potential, and the level of the input signal is compared with the level of the detection potential to obtain a difference. A potential according to the difference is added to the signal potential held in the holding capacitor.

  Further, the present invention includes a row-shaped scanning line, a column-shaped signal line, and a pixel circuit disposed at each of the intersecting portions. The pixel circuit includes at least an electro-optic element, a drive transistor, a sampling transistor, and the like. The drive transistor has a gate connected to the input node, a source connected to the output node, a drain connected to a predetermined power supply potential, and the electro-optic element having one end connected to the output node. The other end is connected to a predetermined potential, the sampling transistor is connected between the input node and the signal line, and the storage capacitor is connected to the input node. The sampling transistor operates when selected by a scanning line, samples an input signal from the signal line and holds it in the storage capacitor, The drive transistor detects a decrease in the drive current from the output node side when performing display by supplying a drive current to the electro-optic element according to the signal potential held in the storage capacitor, The drive current flowing in the resistance component inserted between the output node and a predetermined ground potential in order to feed back the result to the input node side and compensate for the decrease in drive current due to the change of the drive transistor with time. The voltage drop generated in the resistance component is obtained as a detection potential, the level of the input signal is compared with the level of the detection potential, a difference is obtained, and the potential corresponding to the difference is held in the holding capacitor It is characterized by being applied to an electric potential.

  According to the present invention, the pixel circuit incorporates a compensation circuit to compensate for a decrease in drive current accompanying a change with time of the drive transistor. The compensation circuit detects a decrease in the drive current from the output node side, and feeds back the result to the input node side, thereby canceling the decrease in the drive current in a circuit manner. Therefore, even if the mobility of the drive transistor is lowered and the driving capability is lowered, feedback is applied to the input node so as to compensate for this. As a result, the driving current can be maintained at a constant level as in the initial period for a long time. . As a result, luminance deterioration due to the drive transistor can be prevented, and the uniformity of the screen can be maintained over a long period of time.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, in order to clarify the background of the present invention, a general configuration of an active matrix display device and a pixel circuit included therein will be described as a reference example with reference to FIG. As shown in the figure, the active matrix display device includes a pixel array 1 as a main part and a peripheral circuit group. The peripheral circuit group includes a horizontal selector 2, a drive scanner 3, a write scanner 4, and the like.

  The pixel array 1 is composed of row-like scanning lines WS and column-like signal lines DL and pixel circuits 5 arranged in a matrix at portions where they intersect. The signal line DL is driven by the horizontal selector 2. The scanning line WS is scanned by the write scanner 4. Note that another scanning line DS is also wired in parallel with the scanning line WS, and this is scanned by the drive scanner 3. Each pixel circuit 5 samples a signal from the signal line DL when selected by the scanning line WS. Further, when selected by the scanning line DS, the load element is driven according to the sampled signal. This load element is a current drive type light emitting element formed in each pixel circuit 5.

  FIG. 2 is a reference diagram showing a basic configuration of the pixel circuit 5 shown in FIG. The pixel circuit 5 includes a sampling thin film transistor (sampling transistor Tr1), a drive thin film transistor (drive transistor Tr2), a switching thin film transistor (switching transistor Tr3), a storage capacitor C1, a load element (organic EL light emitting element), and the like. Yes.

  The sampling transistor Tr1 becomes conductive when selected by the scanning line WS, samples the video signal from the signal line DL, and holds it in the holding capacitor C1. The drive transistor Tr2 controls the amount of current supplied to the light emitting element EL according to the signal potential held in the holding capacitor C1. The switching transistor Tr3 is controlled by the scanning line DS, and turns on / off energization to the light emitting element EL. That is, the drive transistor Tr2 controls the light emission luminance (brightness) of the light emitting element EL according to the energization amount, while the switching transistor Tr3 controls the light emission time of the light emitting element EL. With these controls, the light emitting element EL included in each pixel circuit 5 exhibits luminance corresponding to the video signal, and a desired display is displayed on the pixel array 1.

  FIG. 3 is a timing chart for explaining operations of the pixel array 1 and the pixel circuit 5 shown in FIG. At the beginning of one field period (1f), a selection pulse ws [1] is applied to the pixel circuits 5 in the first row during one horizontal period (1H) via the scanning line WS, and the sampling transistor Tr1 is turned on. As a result, the video signal is sampled from the signal line DL and written to the storage capacitor C1. One end of the storage capacitor C1 is connected to the gate of the drive transistor Tr2. Therefore, when the video signal is written into the storage capacitor C1, the gate potential of the drive transistor Tr2 rises according to the written signal potential. At this time, the selection pulse ds [1] is applied to the switching transistor Tr3 via another scanning line DS. During this time, the light emitting element EL continues to emit light. In the second half of the one-field period 1f, ds [1] is at a low level, so that the light emitting element EL is in a non-light emitting state. By adjusting the duty of the pulse ds [1], the ratio between the light emission period and the non-light emission period can be adjusted, and a desired screen luminance can be obtained. In the next horizontal period, scanning signal pulses ws [2] and ds [2] are applied to the pixel circuits in the second row from the scanning lines WS and DS, respectively.

  FIG. 4 is a graph showing a change with time of current-voltage (IV) characteristics of an organic EL element incorporated in the pixel circuit 5 as a light emitting element. In the graph, the curve indicated by the solid line indicates the characteristic in the initial state, and the curve indicated by the broken line indicates the characteristic after change with time. Generally, the IV characteristic of an organic EL element deteriorates over time as shown in the graph. The pixel circuit of the reference example shown in FIG. 2 has a problem that the drive transistor has a source follower configuration and cannot cope with a change in the IV characteristic of the EL element with time, resulting in deterioration of light emission luminance.

  FIG. 5A is a graph showing operating points of the drive transistor Tr2 and the light emitting element EL in the initial state. In the figure, the vertical axis represents the drain-source voltage Vds of the drive transistor Tr2, and the vertical axis represents the drain-source current Ids. As illustrated, the source potential is determined by the operating point of the drive transistor Tr2 and the light emitting element EL, and the voltage value varies depending on the gate voltage. Since the drive transistor Tr2 operates in the saturation region, the drive current Ids having a current value defined by the above-described transistor characteristic equation is supplied with respect to Vgs corresponding to the source voltage at the operating point.

  However, the IV characteristic of the light emitting element EL deteriorates with time as shown in FIG. As shown in FIG. 5B, the operating point changes due to the deterioration with time, and the source voltage of the transistor changes even when the same gate voltage is applied. As a result, the gate-source voltage Vgs of the drive transistor Tr2 changes, and the flowing current value fluctuates. At the same time, the value of the current flowing through the light emitting element EL also changes. When the IV characteristic of the light emitting element EL changes in this way, the luminance of the light emitting element EL changes with time in the pixel circuit having the source follower configuration of the reference example shown in FIG.

  FIG. 6 shows another reference example of the pixel circuit, which addresses the problems of the previous reference example shown in FIG. In order to facilitate understanding, parts corresponding to those in the reference example of FIG. The improvement is that the connection of the switching transistor Tr3 is changed, thereby realizing a bootstrap function. Specifically, the source of the switching transistor Tr3 is grounded, the drain is connected to the source (S) of the drive transistor Tr2 and one electrode of the storage capacitor C1, and the scanning line DS is connected to the gate. The other electrode of the storage capacitor C1 is connected to the gate (G) of the drive transistor Tr2.

  FIG. 7 is a timing chart for explaining the operation of the pixel circuit 5 shown in FIG. In the first horizontal period 1H in the field period 1f, the selection pulse ws [1] is sent from the write scanner 4 to the pixel circuit 5 in the first row via the scanning line WS. The numbers in [] correspond to the row numbers of the pixel circuits arranged in a matrix. When the selection pulse is applied, the sampling transistor Tr1 is turned on, and the input signal Vin is sampled from the signal line DL and written to the storage capacitor C1. At this time, the selection pulse ds [1] is applied to the switching transistor Tr3 from the drive scanner 3 via the scanning line DS, and the switching transistor Tr3 is in the ON state. Therefore, one electrode of the storage capacitor C1 and the source (S) of the drive transistor Tr2 are at the GND level. Since the input signal Vin is written to the holding capacitor C1 with the GND level as a reference, the gate potential (G) of the drive transistor Tr2 becomes Vin.

  Thereafter, the selection pulse ws [1] for the sampling transistor Tr1 is released, and then the selection pulse ds [1] for the switching transistor Tr3 is also released. As a result, the sampling transistor Tr1 and the switching transistor Tr3 are turned off. Therefore, the source (S) of the drive transistor Tr2 is disconnected from the GND and becomes a connection node for the anode of the light emitting element EL.

  The drive transistor Tr2 receives the input signal Vin held in the holding capacitor C1 at the gate, and causes a drain current to flow from the Vcc side toward the GND side according to the value. By this energization, the light emitting element EL emits light. At this time, a voltage drop occurs due to energization of the light emitting element EL, but the source potential (S) rises from the GND side toward the Vcc side accordingly. In the timing chart of FIG. 7, this increase is represented by ΔV. One end of the storage capacitor C1 is connected to the source (S) of Tr2, and the other end is connected to a high impedance gate (G). Therefore, when the source potential (S) is increased by ΔV, the gate potential (G) is increased by that amount, and the net input signal Vin is maintained as it is. Therefore, even if the source potential (S) varies by ΔV according to the current-voltage characteristics of the light emitting element EL, the gate voltage Vgs = Vin is always established, and the drain current is kept constant. That is, the drive transistor Tr2 functions as a constant current source for the light emitting element EL by the bootstrap function described above, despite the source follower configuration.

  Thereafter, when the selection pulse ds [1] returns to the high level, the switching transistor Tr3 is turned on, and the current to be supplied to the light emitting element EL is bypassed, so that the light emitting state is turned off. When the field period 1f ends in this way, the next field period starts, and the selection pulse ws [1] is applied to the sampling transistor Tr1 again to sample the input video signal Vin *. Since the level of the sampled video signal may be different between the previous field period and the current field period, the input video signal Vin is marked with an asterisk (*) to distinguish it. Note that such video signal writing and light emission operations are performed line-sequentially (in units of rows). Therefore, the selection pulses ws [1], ws [2]... Are sequentially applied to each row of pixels. Similarly, selection pulses ds [1], ds [2]... Are sequentially applied.

  As described above, the pixel circuit of FIG. 6 can drive the light-emitting element EL at a constant current even when the drive transistor Tr2 is an N-channel type, and can prevent luminance deterioration due to a change in the IV characteristic of the light-emitting element EL with time. It was. However, the time-dependent change due to aging changes not only the light emitting element EL but also the thin film transistor having an amorphous silicon thin film element region as the operating characteristics. In particular, in the case of an N-channel thin film transistor, the mobility μ tends to decrease with time. As a result, the drive capability of the drive transistor Tr2 is reduced, so that even if the level of the input signal applied to the gate is constant, the drain current supplied to the light emitting element is reduced, and there is a risk of luminance deterioration. Therefore, the present invention improves the pixel circuit shown in FIG. 6 and incorporates a drive current compensation function. Hereinafter, embodiments of the pixel circuit according to the present invention will be described in detail. This pixel circuit can be incorporated as a pixel circuit of the display device shown in FIG.

  FIG. 8 is a schematic circuit diagram showing an embodiment of a pixel circuit according to the present invention. In order to facilitate understanding, portions corresponding to those of the pixel circuit according to the reference example illustrated in FIG. As shown in the drawing, the pixel circuit 5 is arranged at a portion where the scanning line and the signal line intersect. The number of signal lines DL is one, but the number of scanning lines WS, X, and Y is bundled and arranged in parallel. The pixel circuit 5 includes an electro-optical element EL, a drive transistor Tr2, a sampling transistor Tr1, and a storage capacitor C1 as basic components. The drive transistor Tr2 is composed of an N-channel thin film transistor, its gate (G) is connected to the input node A, its source (S) is connected to the output node B, and its drain is connected to a predetermined power supply potential Vcc. The gate voltage of the drive transistor Tr2 is represented by Vgs and the drain current is represented by Ids. The electro-optic element EL is composed of a two-terminal light emitting element such as an organic EL element, one end of which is connected to the output node B side, and the other end of the cathode is connected to a predetermined cathode potential Vcath. The sampling transistor Tr1 is connected between the input node A and the signal line DL. The gate of the sampling transistor Tr1 is connected to the scanning line WS. The storage capacitor C1 is connected to the input node A.

  In this configuration, the sampling transistor Tr1 operates when selected by the scanning line WS, samples the input signal Vsig from the signal line DL, and holds it in the holding capacitor C1. The drive transistor Tr2 supplies a drive current (drain current Ids) to the electro-optical element EL according to the signal potential Vin held in the holding capacitor C1.

  As a feature of the present invention, the pixel circuit 5 includes a compensation circuit 7 for compensating for a decrease in drive current (drain current Ids) accompanying a change with time of the drive transistor Tr2. The compensation circuit 7 includes a detecting unit and a feedback unit for detecting a decrease in the drain current Ids from the output node B side and feeding back the result to the input node A side. The detection means is a capacitor that holds a resistance component inserted between the output node B and a predetermined ground potential Vss and a voltage drop generated in the resistance component due to the drain current Ids flowing from the output node B to the ground potential Vss as a detection potential. Contains ingredients. The feedback means compares the level Vin of the input signal Vsig with the level of the detection potential to obtain a difference ΔVμ, and adds a potential corresponding to the difference to the signal potential Vin held in the holding capacitor C1.

  Specifically, the compensation circuit 7 shown in FIG. 8 includes two capacitance elements C2 and C3 and seven transistors Tr3 to Tr9. The switching transistor Tr8 is inserted between the output node B and the anode of the electro-optic element EL. The switching transistor Tr7 is also connected to the output node B. The transistor Tr9 is diode-connected between the switching transistor Tr7 and a predetermined ground potential Vss and functions as a detection transistor. The capacitive element C3 is connected in parallel with the detection transistor Tr9 and functions as a detection capacitor. The diode-connected detection transistor Tr9 corresponds to the resistance component provided in the detection means of the compensation circuit 7, and the detection capacitor C3 corresponds to the capacitance component provided in the detection means of the compensation circuit 7 as well.

  The other capacitor element C2 is connected between the output node B and a predetermined intermediate node C, and constitutes a feedback capacitor. The switching transistor Tr6 is inserted between the intermediate node C and the signal line DL. The switching transistor Tr3 is inserted between a terminal node D connected to one end of the storage capacitor C1 and a predetermined ground potential Vss. The switching transistor Tr4 is inserted between the terminal node D and the output node B. The switching transistor Tr5 is inserted between the terminal node D and the intermediate node C.

  Note that the gate of the switching transistor Tr3 is connected to the scanning line WS like the sampling transistor Tr1. The gates of the switching transistors Tr4, Tr6, Tr7 are all connected to the scanning line X. The gates of the switching transistors Tr5 and Tr8 are connected to the scanning line Y.

  The operation of the pixel circuit shown in FIG. 8 will be described in detail with reference to the timing chart of FIG. In the illustrated timing chart, one field (1f) starts at timing T1 and one field ends at timing T6. Along the time axis T, waveforms of a pulse ws applied to the scanning line WS, a pulse x applied to the scanning line X, and a pulse y applied to the scanning line Y are shown. In addition, along the same time axis T, potential changes of the input node A, the intermediate node C, and the output node B are shown. The change in potential at the input node A and the change in potential at the output node B are indicated by solid lines, and the change in potential at the intermediate node C is indicated by dotted lines in order to distinguish them.

  At timing T0 before entering the field, the scanning lines WS and X are held at the low level, while the scanning line Y is at the high level. Therefore, the sampling transistor Tr1, the switching transistors Tr3, Tr4, Tr6, and Tr7 are off, and only the switching transistors Tr5 and Tr8 are on. At this time, as shown in the timing chart, there is a potential difference substantially equal to the input potential Vin between the potential of the input node A and the potential of the output node B. Therefore, the drive transistor Tr2 is in the on state, and the drive current (drain) (Current) Ids is supplied to the light emitting element EL.

  When entering the field, the scanning line Y is switched to the low level at the timing T1. As a result, the switching transistors Tr5 and Tr8 are turned off. Accordingly, since the light emitting element EL is disconnected from the output node B, the light emitting element EL enters a non-light emitting state. At timing T1, in addition to the switching transistor Tr5, the switching transistors Tr3 and Tr4 are also turned off. Accordingly, the terminal node D of the holding capacitor C1 has a high impedance. This operation at timing T1 corresponds to preparation for sampling of the input signal in the field.

  At timing T2, the selection pulse ws is applied to the scanning line WS, and the selection pulse x is also applied to the scanning line X. As a result, the scanning line WS becomes high level, and the switching transistors Tr1 and Tr3 are turned on. At the same time, since the scanning line X also changes from the low level to the high level, the transistors Tr4, Tr6, and Tr7 are turned on.

  When the switching transistor Tr3 is turned on, the terminal node D is connected to the ground potential Vss. Further, when the switching transistor Tr4 is turned on, the output node B is directly connected to the terminal node D. As a result, the potential of the output node B is suddenly lowered to the ground potential Vss. At this time, since the sampling transistor Tr1 is also turned on, the input signal Vsig supplied to the signal line DL is written to the storage capacitor C1. The magnitude of the written signal potential Vin is substantially equal to the voltage of the input signal Vsig. Since the terminal node D is fixed at Vss, the potential of the input node A is just Vin as shown in the timing chart. Since the input potential Vin is applied between the gate G and the source S of the drive transistor Tr2, the drain current Ids corresponding to the signal potential Vin flows out from the output node B.

  However, as described above, since the switching transistor Tr8 is in an off state, the switching transistor Tr8 is not supplied to the electro-optical element EL and continues to maintain a non-light emitting state.

  When one horizontal period (1H) assigned to the input signal writing operation elapses, the selection pulse ws is released at timing T3, and the scanning line WS becomes low level. As a result, the N-channel sampling transistor Tr1 is turned off and the switching transistor Tr3 is also turned off. As a result, the input node A is disconnected from the signal line DL and becomes a high impedance state. The terminal node D and the output node B are disconnected from the ground potential Vss while being connected to each other. In response to this, since the drive transistor Tr2 starts to flow the drain current Ids in accordance with the signal potential Vin applied between the gate G and the source S, the potential of the output node B rises. In conjunction with this, the potential of the input node A also rises by exactly Vin. At this time, since the switching transistor Tr8 is still in the OFF state, the drain current Ids does not flow through the electro-optical element EL and remains in the non-light emitting state. However, since the switching transistor Tr7 is on, the drain current Ids flows from the output node B to the ground potential Vss via the switching transistors Tr7 and Tr9. When the drain current Ids flows through the detection transistor composed of the diode-connected transistor Tr9, a voltage drop ΔVTr9 corresponding to the magnitude of the drain current Ids occurs. This voltage drop ΔVTr9 is sampled across the capacitor C3 as a detection potential. Since the output node B is connected to the detection capacitor C3 when the switching transistor Tr7 is on, the potential of the output node B is at the level of ΔVTr9 as shown in the timing chart.

  On the other hand, since the sampling transistor Tr6 is also on, the intermediate node C is connected to the signal line DL. As a result, the intermediate node C located on the left side of the feedback capacitor C2 becomes the signal potential Vin of the input signal Vsig. On the other hand, the output node B on the right side of the feedback capacitor C2 has a potential of ΔVTr9 as described above. Therefore, a potential difference of ΔVμ = Vin−ΔVTr9 is generated at both ends of the feedback capacitor C2. Thus, the feedback capacitor C2 compares the level Vin of the input signal Vsig with the level of the detection potential ΔVTr9 described above to obtain a difference ΔVμ. ΔVTr9 is a voltage drop due to the drain current Ids. Therefore, when the mobility and the like of the drive transistor Tr2 deteriorate with time and the drain current Ids decreases, ΔVTr9 also decreases. Conversely, when ΔVTr9 becomes smaller, ΔVμ becomes larger. By feeding back this ΔVμ to the input node A side, it is possible to cancel the decrease in the drain current Ids. Even if the supply capability of the drain current Ids is reduced due to the deterioration of the drive transistor Tr2 with the passage of time, this feedback operation can ensure a drive current at the same level as the initial drain current.

  Thereafter, at timing T4, the selection pulse x is canceled and the scanning line X becomes low level. As a result, the switching transistors Tr4, Tr6, Tr7 are turned off. The feedback capacitor C2 is disconnected from the signal line DL and the ground potential Vss and holds the above-described difference ΔVμ.

  Thereafter, when proceeding to timing T5, the selection pulse y is applied, and the scanning line Y is switched from the low level to the high level. As a result, the switching transistors Tr5 and Tr8 are turned on. When the switching transistor Tr8 is turned on, the anode of the electro-optic element EL is directly connected to the output node B. Further, the intermediate node C is directly connected to the terminal node D by turning on the switching transistor Tr5. Between the input node A and the output node B, ΔVμ held in C2 is applied in addition to Vin held in C1. The drive transistor Tr2 supplies the drain current Ids corresponding to Vin + ΔVμ to the light emitting element EL and starts light emission. The output node B rises due to a voltage drop generated in the light emitting element EL. In conjunction with this, the potential of the input node A also rises. By this bootstrap operation, the potential difference between the input node A and the output node B is held at a value of Vin + ΔVμ. As described above, when the drain current Ids decreases due to the deterioration of the drive transistor Tr2, ΔVμ increases to compensate for this. By this feedback operation, the fluctuation of the drain current Ids is suppressed, and the drain current Ids at the same level as the initial level can be flowed regardless of the change in the mobility μ of the drive transistor Tr2.

  Thereafter, when the timing T6 is reached, the scanning line Y falls to the low level, the switching transistor Tr8 is turned off, and the light emission ends. Thus, a series of operations in the field is completed, and the next field starts.

  As described above, the compensation circuit of the present invention includes a resistance component inserted between the output node and the ground potential and a capacitance component that holds a voltage drop generated in the resistance component due to the drive current flowing from the output node to the ground potential as the detection potential. The detection means provided is adopted. Since the voltage drop generated in the resistance component is detected, the detection itself can be completed in a short time and the timing margin is sufficient. On the other hand, it is possible to employ a detection means for accumulating the charge carried by the drive current for a certain time and outputting a detection potential corresponding to the amount of accumulated charge. However, since the method using the detection potential corresponding to the amount of accumulated charge requires a predetermined time for charge accumulation, there is a possibility that the timing margin in the entire sequence is compressed. For comparison, a method of using a detection potential corresponding to the amount of accumulated charge will be described below with reference to FIGS.

  FIG. 10 is a schematic circuit diagram showing an embodiment of a pixel circuit according to a comparative example. In order to facilitate understanding, portions corresponding to the pixel circuit according to the present invention shown in FIG. As shown in the drawing, the pixel circuit 5 is arranged at a portion where the scanning line and the signal line intersect. The number of signal lines DL is one, but the number of scanning lines WS, X, and Y is bundled and arranged in parallel. The pixel circuit 5 includes an electro-optical element EL, a drive transistor Tr2, a sampling transistor Tr1, and a storage capacitor C1 as basic components. The drive transistor Tr2 is composed of an N-channel thin film transistor, its gate (G) is connected to the input node A, its source (S) is connected to the output node B, and its drain is connected to a predetermined power supply potential Vcc. The gate voltage of the drive transistor Tr2 is represented by Vgs and the drain current is represented by Ids. The electro-optic element EL is composed of a two-terminal light emitting element such as an organic EL element, one end of which is connected to the output node B side, and the other end of the cathode is connected to a predetermined cathode potential Vcath. The sampling transistor Tr1 is connected between the input node A and the signal line DL. The gate of the sampling transistor Tr1 is connected to the scanning line WS. The storage capacitor C1 is connected to the input node A.

  In this configuration, the sampling transistor Tr1 operates when selected by the scanning line WS, samples the input signal Vsig from the signal line DL, and holds it in the holding capacitor C1. The drive transistor Tr2 supplies a drive current (drain current Ids) to the electro-optical element EL according to the signal potential Vin held in the holding capacitor C1.

  As a feature of the comparative example, the pixel circuit 5 includes a compensation circuit 7 for compensating for a decrease in drive current (drain current Ids) accompanying a change with time of the drive transistor Tr2. The compensation circuit 7 detects a decrease in the drain current Ids of the drive transistor Tr2 from the output node B side and feeds back the result to the input node A side. For this purpose, the compensation circuit 7 detects the level of the input signal Vsig and the level of this detection potential by detecting means for accumulating the charge carried by the drain current Ids for a certain period of time and outputting a detection potential corresponding to the amount of accumulated charge. Feedback means for obtaining a difference ΔVμ by comparison and adding a potential corresponding to the difference to the signal potential Vin held in the holding capacitor C1.

  Specifically, the compensation circuit 7 includes six transistors Tr3 to Tr8 and two capacitors C2 and C3. The switching transistor Tr8 is inserted between the output node B and the electro-optical element EL. The switching transistor Tr7 is also connected to the output node B. The detection capacitor C3 is connected between the switching transistor Tr7 and a predetermined ground potential Vss. The switching transistors Tr7 and Tr8 and the detection capacitor C3 constitute the detection means of the compensation circuit 7 described above.

  The feedback capacitor C2 is connected between the output node B and a predetermined intermediate node C. The switching transistor Tr6 is inserted between the intermediate node C and the signal line DL. The switching transistor Tr3 is inserted between a terminal node D connected to one end of the storage capacitor C1 and a predetermined ground potential Vss. The switching transistor Tr4 is inserted between the terminal node D and the output node B. The switching transistor Tr5 is inserted between the terminal node D and the intermediate node C. The feedback capacitor C2 and the switching transistors Tr5 and Tr6 constitute the feedback means of the compensation circuit 7 described above.

  The gate of the switching transistor Tr3 is connected to the scanning line WS, the gates of the switching transistors Tr4, Tr6, Tr7 are connected to another scanning line X, and the switching transistors Tr5 and Tr8 are further connected to another scanning line Y. .

  The operation of the pixel circuit shown in FIG. 10 will be described in detail with reference to the timing chart of FIG. In the illustrated timing chart, one field (1f) starts at timing T1 and one field ends at timing T6. Along the time axis T, waveforms of a pulse ws applied to the scanning line WS, a pulse x applied to the scanning line X, and a pulse y applied to the scanning line Y are shown. In addition, along the same time axis T, potential changes of the input node A, the intermediate node C, and the output node B are shown. The change in potential at the input node A and the change in potential at the output node B are indicated by solid lines, and the change in potential at the intermediate node C is indicated by dotted lines in order to distinguish them.

  At timing T0 before entering the field, the scanning lines WS and X are held at the low level, while the scanning line Y is at the high level. Therefore, the sampling transistor Tr1, the switching transistors Tr3, Tr4, Tr6, and Tr7 are off, and only the switching transistors Tr5 and Tr8 are on. At this time, as shown in the timing chart, there is a potential difference substantially equal to the input potential Vin between the potential of the input node A and the potential of the output node B. Therefore, the drive transistor Tr2 is in the on state, and the drive current (drain) (Current) Ids is supplied to the light emitting element EL.

  When entering the field, the scanning line Y is switched to the low level at the timing T1. As a result, the switching transistors Tr5 and Tr8 are turned off. Accordingly, since the light emitting element EL is disconnected from the output node B, the light emitting element EL enters a non-light emitting state. At timing T1, in addition to the switching transistor Tr5, the switching transistors Tr3 and Tr4 are also turned off. Accordingly, the terminal node D of the holding capacitor C1 has a high impedance. This operation at timing T1 corresponds to preparation for sampling of the input signal in the field.

  At timing T2, the selection pulse ws is applied to the scanning line WS, and the selection pulse x is also applied to the scanning line X. As a result, the scanning line WS becomes high level, and the switching transistors Tr1 and Tr3 are turned on. At the same time, since the scanning line X also changes from the low level to the high level, the transistors Tr4, Tr6, and Tr7 are turned on.

  When the switching transistor Tr3 is turned on, the terminal node D is connected to the ground potential Vss. Further, when the switching transistor Tr4 is turned on, the output node B is directly connected to the terminal node D. As a result, the potential of the output node B is suddenly lowered to the ground potential Vss. At this time, since the sampling transistor Tr1 is also turned on, the input signal Vsig supplied to the signal line DL is written to the storage capacitor C1. The magnitude of the written signal potential Vin is substantially equal to the voltage of the input signal Vsig. Since the terminal node D is fixed at Vss, the potential of the input node A is just Vin as shown in the timing chart. Since the input potential Vin is applied between the gate G and the source S of the drive transistor Tr2, the drain current Ids corresponding to the signal potential Vin flows out from the output node B.

  However, as described above, since the switching transistor Tr8 is in an off state, the switching transistor Tr8 is not supplied to the electro-optical element EL and continues to maintain a non-light emitting state.

  When one horizontal period (1H) assigned to the input signal writing operation elapses, the selection pulse ws is released at timing T3, and the scanning line WS returns from the high level to the low level. As a result, the sampling transistor Tr1 and the switching transistor Tr3 are turned off. As a result, the terminal node D and the output node B are disconnected from the ground potential Vss. In response to this, the potential of the output node B starts to rise, and the drain current Ids starts to flow into the detection capacitor C3 via the switching transistor Tr7 in the on state. The potential of the output node B continues to rise as the charge is accumulated. At this time, since the terminal node D is disconnected from the ground potential Vss, the potential of the input node A also rises in conjunction with the potential of the output node B, and the potential difference Vin between them is kept constant.

  At a timing T4 after the elapse of a predetermined time t from the timing T3, the selection pulse x is canceled and the scanning line X returns from the high level to the low level. As a result, the transistors Tr4, Tr7, Tr6 are turned off. When the switching transistor Tr7 is turned off, the charge accumulation in the detection capacitor C3 is completed. The potential of the detection capacitor C3 corresponding to the accumulated charge is given by ΔVC3 = (Ids / C3) · t. As apparent from this equation, the detection potential ΔVC3 is proportional to the drain current Ids because the capacitance value C3 and the accumulation time t are fixed. That is, the detection potential ΔVC3 has a value proportional to the drain current Ids of the drive transistor Tr2. As the mobility μ of the drive transistor Tr2 decreases with time, the detection potential ΔVC3 also decreases accordingly.

  The switching transistors Tr6 and Tr7 are in the on state until immediately before the scanning line X falls to the low level at the timing T4. Accordingly, the intermediate node C side of the feedback capacitor C2 is at the potential Vin of the input signal Vsig. The potential on the output node B side of the feedback capacitor C2 is just ΔVC3. Therefore, when the selection pulse x is released and the switching transistors Tr6 and Tr7 are turned off, the potential ΔVμ corresponding to the difference between Vin and ΔVC3 is held in the feedback resistor C2. That is, ΔVμ = Vin−ΔVC3. As described above, when the drain current Ids decreases due to deterioration of the drive transistor Tr2, ΔVC3 also decreases. Therefore, ΔVμ increases. By feeding back the potential ΔVμ held in the feedback capacitor C2 to the input node A side, it is possible to cancel the decrease in the drain current Ids. By this feedback operation, the drive transistor Tr2 can continue to supply the drain current Ids at the same level as the initial level even if the operation characteristics such as mobility deteriorate.

  In this comparative example, the magnitude of the detection potential ΔVC3 is compared and determined based on the signal potential Vin of the input signal Vsig. The signal potential Vin varies within a predetermined range (for example, 0 to 5 V). Accordingly, the drain current Ids also changes, and ΔVC3 becomes a corresponding level. In this manner, Vin and ΔVC3 change in the same direction, so that a dynamic comparison is possible. As a premise, it is necessary to make the Vin dynamic range and the ΔVC3 dynamic range substantially equal. When the dynamic range of Vin is 0 to 5 V as described above, it is preferable that ΔVC3 also changes within a range of approximately 0 to 5 V. In order to set the dynamic range of ΔVC3 to a desired range, it is necessary to appropriately set the accumulation time t and the capacitance of the detection capacitor C3.

  Thereafter, when proceeding to timing T5, the selection pulse y is applied, and the scanning line Y is switched from the low level to the high level. As a result, the switching transistors Tr5 and Tr8 are turned on. When the switching transistor Tr8 is turned on, the anode of the electro-optic element EL is directly connected to the output node B. Further, the intermediate node C is directly connected to the terminal node D by turning on the switching transistor Tr5. Between the input node A and the output node B, ΔVμ held in C2 is applied in addition to Vin held in C1. The drive transistor Tr2 supplies the drain current Ids corresponding to Vin + ΔVμ to the light emitting element EL and starts light emission. The output node B rises due to a voltage drop generated in the light emitting element EL. In conjunction with this, the potential of the input node A also rises. By this bootstrap operation, the potential difference between the input node A and the output node B is held at a value of Vin + ΔVμ. As described above, when the drain current Ids decreases due to the deterioration of the drive transistor Tr2, ΔVμ increases to compensate for this. By this feedback operation, the fluctuation of the drain current Ids is suppressed, and the drain current Ids at the same level as the initial level can be flowed regardless of the change in the mobility μ of the drive transistor Tr2.

  Thereafter, when the timing T6 is reached, the scanning line Y falls to the low level, the switching transistor Tr8 is turned off, and the light emission ends. Thus, a series of operations in the field is completed, and the next field starts.

It is a block diagram which shows the general structure of an active matrix display apparatus and a pixel circuit. It is a circuit diagram which shows the reference example of a pixel circuit. 3 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 2. It is a graph which shows the time-dependent change of the IV characteristic of an organic EL element. It is a graph which shows a time-dependent change of the operating point of a drive transistor and an organic EL element. It is a circuit diagram which shows the other reference example of a pixel circuit. 7 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 6. 1 is a circuit diagram illustrating an embodiment of a pixel circuit according to the present invention. It is a timing chart with which it uses for operation | movement description of embodiment shown in FIG. It is a circuit diagram which shows the pixel circuit which concerns on a comparative example. 11 is a timing chart for explaining the operation of the comparative example shown in FIG. 10.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array, 2 ... Horizontal selector, 3 ... Drive scanner, 4 ... Write scanner, 5 ... Pixel circuit, 7 ... Compensation circuit

Claims (6)

It is arranged at a portion where the scanning line and the signal line intersect, and includes at least an electro-optic element, a drive transistor, a sampling transistor, and a storage capacitor,
The drive transistor has a gate connected to an input node, a source connected to an output node, a drain connected to a predetermined power supply potential,
The electro-optic element has one end connected to the output node and the other end connected to a predetermined potential,
The sampling transistor is connected between the input node and the signal line;
The holding capacitor is connected to the input node;
The sampling transistor operates when selected by a scanning line, samples an input signal from the signal line and holds it in the storage capacitor,
The drive transistor is a pixel circuit that supplies a drive current to the electro-optic element in accordance with a signal potential held in the holding capacitor.
A compensation circuit for compensating for a decrease in drive current accompanying a change with time of the drive transistor;
The compensation circuit detects a decrease in the drive current from the output node side and feeds back the result to the input node side.
The compensation circuit includes a resistance component inserted between the output node and a predetermined ground potential, and a capacitance component that holds a voltage drop generated in the resistance component due to the drive current flowing from the output node to the ground potential as a detection potential. And a feedback means for comparing the level of the input signal with the level of the detection potential to obtain a difference and adding a potential corresponding to the difference to the signal potential held in the holding capacitor. A pixel circuit characterized by that. The compensation circuit includes a switching transistor inserted between the output node and the electro-optic element;
Another switching transistor connected to the output node, a detection transistor diode-connected between the switching transistor and a predetermined ground potential, a detection capacitor connected in parallel with the detection transistor,
A feedback capacitor connected between the output node and a predetermined intermediate node;
A switching transistor inserted between the intermediate node and the signal line;
A switching transistor inserted between a terminal node connected to one end of the storage capacitor and a predetermined ground potential;
A switching transistor inserted between the terminal node and the output node;
The pixel circuit according to claim 1, comprising a switching transistor inserted between the terminal node and the intermediate node. It consists of a row-shaped scanning line, a column-shaped signal line, and a pixel circuit arranged at each of the intersecting portions,
The pixel circuit includes at least an electro-optic element, a drive transistor, a sampling transistor, and a storage capacitor.
The drive transistor has a gate connected to an input node, a source connected to an output node, a drain connected to a predetermined power supply potential,
The electro-optic element has one end connected to the output node and the other end connected to a predetermined potential,
The sampling transistor is connected between the input node and the signal line;
The holding capacitor is connected to the input node;
The sampling transistor operates when selected by a scanning line, samples an input signal from the signal line and holds it in the storage capacitor,
In the display device in which the drive transistor supplies a drive current to the electro-optic element in accordance with a signal potential held in the storage capacitor and performs display.
The pixel circuit includes a compensation circuit for compensating for a decrease in drive current accompanying a change with time of the drive transistor,
The compensation circuit detects a decrease in the drive current from the output node side and feeds back the result to the input node side.
Detection means comprising a resistance component inserted between the output node and a predetermined ground potential, and a capacitance component for holding a voltage drop generated in the resistance component due to the drive current flowing from the output node to the ground potential as a detection potential And a feedback means for comparing the level of the input signal and the level of the detection potential to obtain a difference and adding a potential corresponding to the difference to the signal potential held in the holding capacitor. Display device. The compensation circuit includes a switching transistor inserted between the output node and the electro-optic element;
Another switching transistor connected to the output node, a detection transistor diode-connected between the switching transistor and a predetermined ground potential, a detection capacitor connected in parallel with the detection transistor,
A feedback capacitor connected between the output node and a predetermined intermediate node;
A switching transistor inserted between the intermediate node and the signal line;
A switching transistor inserted between a terminal node connected to one end of the storage capacitor and a predetermined ground potential;
A switching transistor inserted between the terminal node and the output node;
4. The display device according to claim 3, comprising a switching transistor inserted between the terminal node and the intermediate node. The scanning line and the signal line are arranged at a crossing portion, and include at least an electro-optical element, a drive transistor, a sampling transistor, and a storage capacitor. The drive transistor has a gate connected to an input node and a source output. The electro-optic element has one end connected to the output node, the other end connected to the predetermined potential, and the sampling transistor connected to the input node and the node. The pixel capacitor is connected to the signal line, and the storage capacitor is a driving method of the pixel circuit connected to the input node,
The sampling transistor operates when selected by a scanning line, samples an input signal from the signal line and holds it in the storage capacitor,
The drive transistor supplies a drive current to the electro-optic element in accordance with a signal potential held in the holding capacitor,
In order to detect the decrease in the drive current from the output node side and feed back the result to the input node side to compensate for the decrease in the drive current due to the change over time of the drive transistor,
A voltage drop generated in the resistance component due to the drive current flowing in the resistance component inserted between the output node and a predetermined ground potential is obtained as a detection potential,
A pixel circuit driving method comprising: comparing a level of the input signal with a level of the detection potential to obtain a difference, and adding a potential corresponding to the difference to the signal potential held in the holding capacitor. The pixel circuit includes a row-shaped scanning line, a column-shaped signal line, and a pixel circuit disposed at each of the intersecting portions. The pixel circuit includes at least an electro-optic element, a drive transistor, a sampling transistor, and a storage capacitor. The drive transistor has a gate connected to the input node, a source connected to the output node, a drain connected to a predetermined power supply potential, and the electro-optic element connected to the output node at one end and the other end Is connected to a predetermined potential, the sampling transistor is connected between the input node and the signal line, and the storage capacitor is connected to the input node.
The sampling transistor operates when selected by a scanning line, samples an input signal from the signal line and holds it in the storage capacitor,
When the drive transistor performs display by supplying a drive current to the electro-optic element in accordance with the signal potential held in the holding capacitor,
In order to detect the decrease in the drive current from the output node side and feed back the result to the input node side to compensate for the decrease in the drive current due to the change over time of the drive transistor,
A voltage drop generated in the resistance component due to the drive current flowing in the resistance component inserted between the output node and a predetermined ground potential is obtained as a detection potential,
A method for driving a display device, comprising: comparing a level of the input signal with a level of the detection potential to obtain a difference; and adding a potential corresponding to the difference to the signal potential held in the holding capacitor.

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