JP4687026B2 - Display device and driving method of display device - Google Patents

Description

  The present invention relates to a display device and a driving method of the display device, and in particular, pixel circuits each having an electro-optic element whose luminance is changed by a flowing current as a display element are arranged in a matrix, and each pixel circuit (pixel) has an active element. The present invention relates to a display device in which display driving is performed in units of pixels by the active element and a driving method of the display device.

  In a display device, for example, a liquid crystal display device using a liquid crystal cell as a display element of a pixel, a number of pixels including the liquid crystal cell are arranged in a matrix, and the light intensity is controlled for each pixel according to image information to be displayed. Thus, image display driving is performed. This display drive is the same for an organic EL display device using an electro-optical element whose luminance is changed by a flowing current, for example, an organic EL (electroluminescence) element, as a pixel display element.

  However, in the case of an organic EL display device, since it is a so-called self-luminous display device using an organic EL element which is a self-luminous element as a pixel display element, the light intensity from the light source (backlight) is controlled. Compared with a liquid crystal display device, it has advantages such as high image visibility, no need for a backlight, and high response speed. Further, the light emission luminance of the organic EL element is controlled by the value of the current flowing therethrough, that is, the organic EL element is of a current control type, which is greatly different from a liquid crystal display device in which the liquid crystal cell is of a voltage control type.

  In the organic EL display device, as in the liquid crystal display device, a simple (passive) matrix method and an active matrix method can be adopted as the driving method. However, although the simple matrix display device has a simple structure, there is a problem that it is difficult to realize a large and high-definition display device. For this reason, in recent years, an active matrix in which a current flowing in a light emitting element in a pixel is controlled by an active element similarly provided in the pixel, for example, an insulated gate field effect transistor (generally, a thin film transistor (TFT)). There is a lot of development of methods.

  FIG. 17 is a block diagram showing an outline of the configuration of an active matrix organic EL display device. This active matrix display device has a pixel array section 52 in which pixels (pixel circuits) 51 including organic EL elements are arranged in m columns and n rows in a matrix. Here, for simplification of the drawing, a case where the pixel array unit 52 is a pixel array of 3 columns and 2 rows is shown as an example.

  In the pixel array unit 52, a scanning line 53 and a driving line 54 are wired for each row of each pixel 51, and a data line 55 is wired for each column. Around the pixel array section 52, there are a write scanning circuit 56 for driving the scanning line 53, a driving scanning circuit 57 for driving the driving line 54, and a data line for supplying a data signal corresponding to the luminance information to the data line 55. A drive circuit 58 is arranged.

  FIG. 18 is a circuit diagram showing a conventional example of a pixel circuit (unit pixel circuit) in an active matrix organic EL display device.

  As is apparent from FIG. 18, the pixel circuit according to this conventional example has, for example, an organic EL element 101 whose cathode (cathode) is connected to the ground potential GND, and a drain connected to the anode (anode) of the organic EL element 101. , A P-channel TFT 102 whose source is connected to the positive power supply potential Vcc, a capacitor 103 connected between the gate of the TFT 102 and the positive power supply potential Vcc, a source to the gate of the TFT 102, a gate to the scanning line 105, The P-channel TFT 104 has a drain connected to the data line 106 (see, for example, Patent Documents 1 and 2).

  Here, since organic EL elements often have a rectifying property, they are sometimes called OLEDs (Organic Light Emitting Diodes). Therefore, in FIG. 18 and other drawings, a diode symbol is used as the OLED. However, in the following description, rectification is not necessarily required for the OLED.

  Next, the operation of the pixel circuit having the above configuration will be described. First, when the potential of the scanning line 105 is set to a selected state (here, a low level state) and the write potential Vdata is applied to the data line 106, the TFT 104 is turned on and the capacitor 103 is charged or discharged. As a result, the gate potential of the TFT 102 becomes the write potential Vdata. Next, when the potential of the scanning line 105 is set to a non-selected state (here, a high level state), the scanning line 105 and the TFT 102 are electrically disconnected, but the gate potential of the TFT 102 is stably held by the capacitor 103. .

  The current flowing in the TFT 102 and the organic EL element 101 has a value corresponding to the gate-source voltage Vgs of the TFT 102. Then, the organic EL element 101 continues to emit light with a luminance corresponding to the current value. Here, the operation of selecting the scanning line 105 and transmitting the luminance information supplied through the data line 106 to the inside of the pixel through the TFT 104 is hereinafter referred to as “writing”.

  As described above, in the pixel circuit of FIG. 18, once the potential Vdata is written, the organic EL element 101 continues to emit light with a constant luminance until the next potential Vdata is written. Further, the value of the current flowing through the organic EL element 101 is controlled by changing the gate voltage of the TFT 102 which is a driving transistor. At this time, the TFT 102 is a constant current source having a current value Ids shown in the following equation (1) because the source is connected to the positive power supply potential Vcc and always operates in the saturation region.

Ids = 1/2 · μ (W / L) Cox (Vgs− | Vth |) ² (1)
Here, Vth is a threshold value of the TFT 102,. Carrier mobility, W is a channel width, L is a channel length, Cox is a gate capacitance per unit area, and Vgs is a gate-source voltage.

  In a simple matrix display device, each light emitting element emits light only at a selected moment. On the other hand, in the active matrix display device, the light emitting element continues to emit light even after writing is completed. Therefore, the active matrix display device is particularly advantageous in a large-sized and high-definition display device in that the peak luminance and peak current of the light-emitting element can be reduced as compared with the simple matrix display device.

  FIG. 19 is a characteristic diagram showing a change with time of current-voltage characteristics (IV characteristics) of an organic EL element. In FIG. 19, the curve indicated by the solid line indicates the characteristic in the initial state, and the curve indicated by the broken line indicates the characteristic after change with time.

  Generally, the IV characteristic of an organic EL element deteriorates with time as shown in FIG. However, in the pixel circuit of FIG. 18, as described above, constant current continues to flow through the organic EL element 101 due to constant current driving by the TFT 102 which is a driving transistor, and the IV characteristics of the organic EL element deteriorate. However, the emission luminance does not decrease.

  By the way, the pixel circuit of FIG. 18 is configured by a P-channel TFT. If a pixel circuit can be constituted by an N-channel TFT instead of the P-channel TFT, a conventional amorphous silicon (a-Si) process can be used for TFT production. Cost reduction can be achieved.

  Consider a pixel circuit in which a P-channel TFT is replaced with an N-channel TFT.

  FIG. 20 is a circuit diagram showing a configuration of a pixel circuit in which the P-channel TFT in FIG. 18 is replaced with an N-channel TFT.

  As is apparent from FIG. 20, this pixel circuit includes, for example, an organic EL element 201 whose cathode is connected to the ground potential GND, a source connected to the anode of the organic EL element 201, and a drain connected to the positive power supply potential Vcc. The N-channel TFT 202, the capacitor 203 connected between the gate of the TFT 202 and the positive power supply potential Vcc, the drain connected to the gate of the TFT 202, the gate connected to the scanning line 205, and the source connected to the data line 206, respectively. The source follower circuit configuration has an N-channel TFT 204.

  FIG. 21 is a diagram illustrating operating points of the TFT 202 as the driving transistor and the organic EL element 201 in the initial state. In FIG. 21, the horizontal axis represents the drain-source voltage Vds of the TFT 202, and the vertical axis represents the drain-source current Ids. As shown in FIG. 21, the source voltage is determined by the operating point of the TFT 202 and the organic EL element 201, and has a different value depending on the gate voltage. Since the TFT 202 is driven in a saturation region, a current Ids having a current value given by the equation (1) is passed with respect to the gate-source voltage Vgs with respect to the source voltage at the operating point.

US Pat. No. 5,684,365 JP-A-8-234683

  However, even in a pixel circuit in which a P-channel TFT is replaced with an N-channel TFT, deterioration due to aging of the IV characteristics of the organic EL element cannot be avoided. As a result, as shown in FIG. Therefore, even if the same gate voltage is applied to the TFT 202 which is a driving transistor, the source voltage fluctuates. As a result, the gate-source voltage Vgs of the TFT 202 changes, and the value of the current flowing through the TFT 202 changes. At the same time, since the current value flowing through the organic EL element 201 also changes, when the IV characteristic of the organic EL element 201 changes, the emission luminance of the organic EL element 201 also changes with time.

As a modification of the pixel circuit of FIG. 20 , as shown in FIG. 23, the anode of the organic EL element 201 is connected to the positive power supply potential Vcc, and the drain of the N-channel TFT 202 as a drive transistor is connected to the cathode of the organic EL element 201. In addition, a circuit configuration in which the source is connected to the ground potential GND can be considered.

  In the pixel circuit according to this modification, the source potential of the N-channel TFT 202 is fixed to the ground potential GND and operates as a constant current source, as in the case of driving by the P-channel TFT 102 of FIG. Therefore, a change in luminance due to deterioration of the IV characteristic of the organic EL element 201 can be prevented.

  However, in the pixel circuit according to this modification, a configuration in which the N-channel TFT 202 that is a driving transistor is connected to the cathode side of the organic EL element 201 must be adopted. In order to adopt this cathode connection configuration, it is necessary to develop a new anode / cathode electrode for the organic EL element. Development of the anode / cathode electrode is considered to be very difficult with the current technology. From such a viewpoint, conventionally, a pixel circuit using an N-channel transistor that suppresses a change in luminance due to a change with time in IV characteristics of an organic EL element has not been developed.

  The present invention has been made in view of the above problems, and an object thereof is to be realized by an N-channel transistor that does not change in luminance even if the current-voltage characteristics of the light-emitting element change over time. An object of the present invention is to provide a display device in which pixel circuits are arranged in a matrix and a method for driving the display device.

In order to achieve the above object, in the present invention,
An electro-optic element having one end connected to the first power supply potential;
A drive transistor having a source connected to the other end of the electro-optic element;
A first capacitor connected between the gate and source of the drive transistor;
A first switching transistor that selectively takes in a signal corresponding to luminance information from the data line;
A second switching transistor connected between the drain of the driving transistor and a second power supply potential;
A third switching transistor connected between the source of the driving transistor and a third power supply potential;
A second capacitor connected between the gate of the drive transistor and the first switching transistor;
A fourth switching transistor connected between the gate and drain of the drive transistor;
In a display device in which pixel circuits having a fifth switching transistor connected between a connection node between the first switching transistor and the second capacitor and a predetermined potential are arranged in a matrix,
From the first row in the matrix array of the pixel array portion, the first switching transistor is driven during the driving period of the second, fourth, and fifth switching transistors from the last row and from the end of driving of the third switching transistor. The pixel circuits up to the Nth row before the number of rows corresponding to the period until the start of driving of the switching transistor are used as effective pixels for image display.

  In the display device having the above structure, with the second switching transistor turned on, the third switching transistor is turned on, the source potential of the driving transistor is set to the third power supply potential, and the first capacitor is charged. Is determined by the difference between the input voltage and the third power supply potential. Then, after the writing to the first capacitor is completed, the third switching transistor is turned off during the light emission period of the electro-optical element, whereby a current starts to flow through the electro-optical element. At this time, since the drive transistor operates as a constant current source, even if the current-voltage characteristic of the electro-optic element changes with time, and the source potential of the drive transistor changes accordingly, the drive transistor is driven by the first capacitor. Since the potential difference between the gate and the source is kept constant, the current flowing through the electro-optic element does not change, and therefore the emission luminance of the electro-optic element is also kept constant.

  Further, prior to the write operation, the fourth and fifth switching transistors are turned on while the third switching transistor is turned on, so that a threshold cancellation period for canceling the variation in the threshold voltage of the driving transistor is entered. By turning off the third switching transistor during this threshold cancellation period, the gate-drain voltage of the driving transistor gradually decreases with the lapse of time due to the action of the first and second capacitors. After the elapse, the sum of the threshold voltage Vth of the driving transistor and the third power supply potential Vss is obtained. At this time, if the predetermined potential is Vofs, the first capacitor holds the voltage (Vofs−Vth−Vss), and the second capacitor holds the voltage Vth. Then, the threshold voltage Vth of the driving transistor is canceled by entering the writing operation.

  Further, in the cancel period of the threshold voltage Vth, the amount of current flowing into or out of the third power supply potential node gradually increases or decreases as scanning progresses toward the last row in the vertical scanning direction. As a result, the third power supply potential fluctuates, and the third power supply potential fluctuates when returning to the original potential when the threshold cancellation operation for the last row is completed. Strip-like white or black streaks or gradation image quality defects occur. These image quality defects occur in the number of rows corresponding to the period from the end of driving of the third switching transistor to the start of driving of the first switching transistor during the driving period of the second, fourth, and fifth switching transistors. Only from the (N + 1) th line before the last line to the last line. Therefore, the pixel circuits from the first row to the Nth row before the last row by the number of rows + 1 are set as effective pixels, and the pixel circuits from the N + 1th row to the last row are not used for image display. As a result, the image quality defect occurs in the invalid pixel region and does not occur in the effective pixel region.

  According to the present invention, even if the current-voltage characteristic of the electro-optic element changes with time, and the source potential of the drive transistor changes accordingly, the emission luminance of the electro-optic element can be kept constant, and the first Therefore, it is possible to prevent band-like white and black streaks or gradation image quality defects caused by fluctuations in the power source potential 3 from occurring in the effective pixel region, and thus uniform image quality without unevenness can be obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of an active matrix display device to which the present invention is applied and a pixel (hereinafter also referred to as a pixel circuit) used in the display device. In the active matrix display device according to this application example, the electro-optic elements whose luminance is changed by a flowing current, for example, the pixels 11 including the organic EL elements 31 as display elements are two-dimensionally arranged in a matrix (matrix). The pixel array unit 12 is included. Here, for simplification of the drawing, only one pixel 11 is shown with a specific circuit configuration.

  In the pixel array unit 12, a scanning line 13, first and second drive lines 14, 15 and an auto-zero line 16 are wired for each row of each pixel 12, and a data line 17 is wired for each column. ing. Around the pixel array section 12, there are a write scanning circuit 18 for driving the scanning line 13, first and second driving scanning circuits 19A and 19B for driving the first and second driving lines 14 and 15, and an auto-zero line. An auto zero circuit 21 for driving 16 and a data line driving circuit 22 for supplying a data signal corresponding to the luminance information to the data line 17 are arranged. In this example, the writing scanning circuit 18 and the first driving scanning circuit 19 are arranged on one side (right side in the figure) across the pixel array unit 12, and the second driving scanning circuit 20 and the auto zero circuit 21 are arranged on the opposite side. It has been configured.

[Pixel circuit]
As is apparent from FIG. 1, the pixel (pixel circuit) 11 includes a drive transistor 32, capacitors (pixel capacitors) 33 and 34, and switching transistors 35 to 39 as circuit elements in addition to the organic EL element 31. ing. The drive transistor 32 and the switching transistors 35 to 39 are N-channel field effect transistors, for example, N-channel TFTs (thin film transistors). Hereinafter, the drive transistor 32 and the switching transistors 35 to 39 are referred to as TFT 32 and TFTs 35 to 39.

  The organic EL element 31 has a cathode electrode connected to the first power supply potential (in this example, the ground potential GND). The TFT 32 is a drive transistor that drives the organic EL element 31 to emit light, and has a drain connected to the second power supply potential (in this example, the positive power supply potential Vcc) and a source connected to the anode electrode of the organic EL element 31. A source follower circuit is formed. The capacitor 33 is a pixel capacitor, and has one end connected to the gate of the TFT 32 and the other end connected to a connection node N11 between the source of the TFT 32 and the anode electrode of the organic EL element 31.

  The TFT 35 has a source connected to the data line 17 and a gate connected to the first scanning line 13. The capacitor 34 has one end connected to the drain of the TFT 35 and the other end connected to a connection node N12 between the gate of the TFT 32 and one end of the capacitor 33. The TFT 36 has a drain connected to the connection node N11 and a source connected to the third power supply potential Vss (for example, the ground potential GND). Note that a negative power supply potential may be used as the third power supply potential Vss.

  The TFT 37 has a drain connected to the power supply potential Vcc, a source connected to the drain of the TFT 32, and a gate connected to the second drive line 15. The drain of the TFT 38 is connected to the connection node N13 between the drain of the TFT 32 and the source of the TFT 37, the source is connected to the connection node N12, and the gate is connected to the auto-zero line 16. The TFT 39 has a drain connected to the predetermined potential Vofs, a source connected to the drain of the TFT 35, and a gate connected to the auto-zero line 16.

  Next, regarding the circuit operation of the active matrix organic EL display device in which the pixels (pixel circuits) 11 having the above-described configuration are two-dimensionally arranged in a matrix, the timing chart of FIG. 2 and the operation explanatory diagrams of FIGS. It explains using.

In FIG. 2, when driving the pixels 11 in a certain row, the write signal WS supplied from the write scanning circuit 18 to the pixels 11 via the scanning lines 13, and the first to second drive scanning circuits 19, 20 to the first. The timing relationship between the first and second drive signals DS1 and DS2 given to the pixel 11 via the second drive lines 14 and 15 and the auto-zero signal AZ given to the pixel 11 via the auto-zero line 16 from the auto-zero circuit 21 is shown. It is . In the operation explanatory diagrams of FIGS . 3 to 7, the TFTs 32 and 35 to 39 are illustrated using switch symbols for simplification of the drawings.

  In a normal light emission state, the write signal WS output from the write scan circuit 18, the drive signal DS1 output from the first drive scan circuit 19, and the auto zero signal AZ output from the auto zero circuit 21 are at the “L” level. Since the drive signal DS2 output from the second drive scanning circuit 20 is at the “H” level, as shown in FIG. 3, the TFTs 35, 36, 38, and 39 are in an off state, and the TFT 37 is in an on state. . At this time, the TFT 32 which is a drive transistor operates as a constant current source because it is designed to operate in a saturation region. As a result, the organic EL element 31 is supplied from the TFT 32 with a constant current Ids given by the above-described formula (1).

  Next, the drive signal DS1 output from the first drive scanning circuit 19 and the auto-zero signal AZ output from the auto-zero circuit 21 in the state where the TFT 37 is turned on become the H ″ level, and the TFTs 36, 38 and 39 are turned on. Thereby, the power supply potential Vss is applied to the anode of the organic EL element 31 and the power supply potential Vcc is applied to the gate of the TFT 32. At this time, the power supply potential Vss is applied to the cathode voltage Vcas of the organic EL element 31 (this example). Then, if it is smaller than the sum (Vcas + Vthel) of the ground potential GNG) and the threshold voltage Vthel of the organic EL element 31, the organic EL element 31 enters a non-emission state and enters a non-emission period, hereinafter Vss ≦ Vcas + Vthel. , Vss is at the GND level, when the TFTs 36 and 38 are turned on. Constant current Ids corresponding to over preparative-source voltage Vgd flows through the path indicated by dotted arrows in FIG.

  Next, when the drive signal DS2 output from the second drive scanning circuit 20 becomes “L” level, as shown in FIG. 5, the TFT 37 is turned off, and the threshold voltage Vth of the TFT 32 is canceled (corrected). The threshold cancellation period starts. At this time, the TFT 32 operates in the saturation region because the gate and the drain are connected via the TFT 38. Further, since the capacitors 33 and 34 are connected in parallel to the gate of the TFT 32, the voltage Vgd between the gate and the drain of the TFT 32 gradually decreases with time as shown in FIG.

  After a certain period of time, the gate-source voltage Vgs of the TFT 32 becomes the threshold voltage Vth of the TFT 32. At this time, the capacitor 34 is charged with a voltage of (Vofs−Vth), and the capacitor 33 is charged with a voltage of Vth. Thereafter, when the TFTs 35 and 37 are turned off and the auto-zero signal AZ output from the auto-zero circuit 21 is changed from the “H” level to the “L” level with the TFT 36 turned on, the TFTs 38 and 39 are turned off, and the threshold cancellation period is reached. Is the end. At this time, the capacitor 34 holds the voltage (Vofs−Vth), and the capacitor 33 holds the voltage Vth.

  Next, when the TFTs 35, 38, and 39 are turned off and the TFTs 36 and 37 are turned on, the write signal WS output from the write scanning circuit 18 becomes “H” level. As described above, the TFT 35 is turned on, and the input signal voltage Vin supplied through the data line 17 is written. When the TFT 35 is turned on, the input signal voltage Vin is taken into the connection node N14 of the drain of the TFT 35, one end of the capacitor 34 and the source of the TFT 39, and the voltage change ΔV of the connection node N14 is transferred to the gate of the TFT 32 via the capacitor 34. To be coupled.

At this time, the gate voltage Vg of the TFT 32 is a value called the threshold voltage Vth, and the coupling amount ΔV is expressed by the following equation (2) according to the capacitance value C1 of the capacitor 33, the capacitance value C2 of the capacitor 34, and the parasitic capacitance value C3 of the TFT 32. To be determined.
ΔV = {C2 / (C1 + C2 + C3)} · (Vin−Vofs) (2)
Therefore, if the capacitance values C1 and C2 of the capacitors 33 and 34 are set sufficiently larger than the parasitic capacitance value C3 of the TFT 32, the coupling amount ΔV to the gate of the TFT 32 is not affected by the threshold voltage Vth of the TFT 32. , Determined only by the capacitance values C1 and C2 of the capacitors 33 and 34.

  The writing signal WS output from the writing scanning circuit 18 changes from the “H” level to the “L” level, and the TFT 35 is turned off, so that the writing period of the input signal voltage Vin ends. After the end of the writing period, the drive signal DS1 output from the first drive scanning circuit 19 becomes “L” level with the TFTs 35, 38, 39 turned off, so that the TFT 36 is turned off. When the drive signal DS2 output from the drive scanning circuit 20 becomes “H” level, the TFT 37 is turned on as shown in FIG.

  When the TFT 37 is turned on, the drain potential of the TFT 32 rises to the power supply potential Vcc. Since the gate-source voltage Vgs of the TFT 32 is constant, the TFT 32 supplies a constant current Ids to the organic EL element 31. At this time, the potential of the connection node N11 rises to a voltage Vx through which the constant current Ids flows through the organic EL element 31, and as a result, the organic EL element 31 emits light.

  Also in the pixel circuit 11 that performs the above-described series of operations, the IV characteristics of the organic EL element 31 change as the light emission time increases. For this reason, the potential of the connection node N11 also changes. However, since the gate-source potential Vgs of the TFT 32 is maintained at a constant value, the current flowing through the organic EL element 31 does not change. Therefore, even if the IV characteristic of the organic EL element 31 deteriorates, the constant current Ids always flows, so that the luminance of the organic EL element 31 does not change. In addition, the threshold voltage Vth of the TFT 32 is canceled by the action of the TFT 38 during the threshold cancellation period, and a constant current Ids that is not affected by the variation of the threshold voltage Vth can be flowed, so that a high-quality image can be obtained. .

  Here, the power supply potential Vss is considered. When the TFT 36 is turned on and the organic EL element 31 enters a non-light emission period, a current flows to a node of the power supply potential Vss (hereinafter referred to as a Vss node) through the path of the power supply potential Vcc → TFT 37 → TFT 32 → TFT 36 (hereinafter referred to as Vss node). Inflow or outflow). After that, the TFTs 38 and 39 are turned on, the TFT 37 is turned off, and the threshold cancellation period for canceling the variation of the threshold voltage Vth is entered, so that the Vss node is reached through the path of the connection node N12 → TFT38 → TFT32 → TFT36. Current flows.

This is a circuit operation in the pixel circuit 11 in a certain row (stage). Even in the entire display panel, current flows in the Vss node for each row, and as shown in FIG. 9, the amount of current flowing in the Vss node as the vertical scanning progresses from the first row to the final row n (Vss node). since the amount of current flowing from the current amount or Vss node flowing into) increases, the power supply potential Vss fluctuates. Then, when the threshold cancellation period of the last row n ends, the current flowing into the Vss node or the current flowing out from the Vss node disappears, so that the power supply potential Vss instantaneously returns to the original potential, and thus the power supply potential Vss fluctuates. Arise. This fluctuation of the power supply potential Vss does not occur if the amount of current flowing into the Vss node or the amount of current flowing out of the Vss node decreases.

In the pixel circuit 11, if the power supply potential Vss fluctuates during the period from the end of driving of the TFT 37 to the end of driving of the TFT 36, the gate potential of the TFT 32 that is a driving transistor is substantially turned off during this period. Therefore, the drain voltage of the TFT 32 (the potential of the connection node N13) cannot follow the fluctuation of the power supply potential Vss, that is, the change of the source potential of the TFT 32. As a result, the capacitor 33 is charged. The voltage, that is, the gate-source voltage Vgs of the TFT 32 changes.

  More specifically, referring to FIG. 10, during the threshold cancel period, particularly when the power supply potential Vss fluctuates in the vicinity of the end of the cancel operation, the threshold cancel period will end soon. The gate potential cannot completely follow the source potential, and the gate-source voltage Vgs of the TFT 32 at the end of the threshold cancellation operation changes by a constant value α with respect to the voltage ΔV when the power supply potential Vss does not fluctuate. Resulting in. Conversely, even if the power supply potential Vss fluctuates in the vicinity of the start of the cancel operation, there is sufficient time until the threshold cancel period ends, and the power supply potential Vss can completely follow the fluctuation within the threshold cancel period. Therefore, the gate-source voltage Vgs of the TFT 32 hardly changes with respect to the voltage ΔV when the power supply potential Vss does not fluctuate.

  Thus, in the cancel period of the threshold voltage Vth, the amount of current flowing into or out of the Vss node gradually increases or decreases as scanning progresses toward the last row n in the vertical scanning direction. When the power supply potential Vss fluctuates and the threshold cancel operation of the last row n is completed, the power supply potential Vss fluctuates when returning to the original potential, and this fluctuation is not limited to the last row n, as shown in FIG. The pixel circuit 11 affects the i-th stage (i is an arbitrary number of stages) in the vertical scanning direction connected to the Vss node. When the power supply potential Vss fluctuates, the change amount α of the gate-source voltage Vgs of the TFT 32 increases, so as shown in FIG. 12, the image is displayed on the last row n side in the vertical scanning direction at the time of raster display. Band-shaped white stripes, black stripes, or gradations are generated, and it becomes impossible to display an image with uniform density.

[First Embodiment]
Therefore, in the present embodiment, in the active matrix organic EL display device based on the pixel circuit (pixel) 11 shown in FIG. 1 and arranged in a matrix, the matrix array of the pixel array unit 12 is arranged. From the first row, the TFT 37 (second switching transistor) and the TFTs 38 and 39 (fourth and fifth) by the second drive scanning circuit 20 and the auto-zero circuit (third drive scanning means) 21 than the last row n. This corresponds to the period from the end of driving of the TFT 36 (third switching transistor) by the first driving scanning circuit 19 to the start of driving of the TFT 35 (first switching transistor) by the writing scanning circuit 18 during the driving period of the switching transistor). Adopting a configuration in which the pixel circuits 11 up to the Nth row before the number of rows are effective pixels. That.

  That is, as shown in FIG. 13, in the pixel array unit 12 having a pixel arrangement of n rows and m columns, the first row to the Nth row before the last row n (nth row) by the number of rows described above. An area of the pixel circuit 11 is an effective pixel area 12A, and an area of the pixel circuit 11 from the (N + 1) th row to the last row n is an invalid pixel area 12B. Here, the effective pixel means a pixel (pixel circuit) actually used for image display, and the invalid pixel means a pixel (pixel circuit) not actually used for image display. Each pixel in the invalid pixel area 12B is not used for image display and therefore does not need to emit light, and thus the organic EL element 31 is not necessary.

  However, in order to make the circuit characteristics of each pixel in the effective pixel area 12A and the circuit characteristics of each pixel in the invalid pixel area 12B exactly the same, the organic EL element 31 is also provided in each pixel in the invalid pixel area 12B. Also good. When the organic EL element 31 is provided in each pixel in the invalid pixel region 12B, the entire invalid pixel region 12B may be shielded from light.

  Here, the basis for determining the last row N (Nth row) of the effective pixel region 12A will be described. As described above, in the cancel period of the threshold voltage Vth, the amount of current flowing into or out of the Vss node (the node of the power supply potential Vss) as the scanning progresses toward the last row n in the vertical scanning direction. The power supply potential Vss fluctuates by gradually increasing or decreasing, and the power supply potential Vss fluctuates when returning to the original potential when the threshold cancel operation of the last row n is completed. A strip-shaped white or black streak or gradation image quality failure occurs on the final line n side.

  These image quality defects occur because the drive of the TFT 35 is started (ON), that is, the writing operation is started after the TFT 36 to 39 is driven (ON) and the TFT 36 is driven (OFF), that is, the threshold voltage Vth is canceled. From the (N + 1) th row before the last row n to the last row n, the number of rows M corresponds to the period up to. From this, the region of each pixel from the first row to the Nth row before the last row n by the number M + 1 is set as the effective pixel region 12A, and from the (N + 1) th row to the last row (M rows). ) Is set as an invalid pixel area 12B. As a result, as apparent from FIG. 14, band-like white stripes, black stripes, or gradation image quality defects occur in the invalid pixel area 12B, so that the image display is actually performed on the effective pixel area 12A. The image quality defect does not appear.

  As described above, in the active matrix organic EL display device in which the pixel circuits (pixels) 11 shown in FIG. 1 are two-dimensionally arranged in a matrix, the period from the start of the threshold cancel operation to the start of the write operation from the first row. By using as the effective pixel region 12A the region of each pixel up to the Nth row before the last row n by the number of rows M + 1 corresponding to the band white stripes generated due to the fluctuation of the power supply potential Vss, Since black stripes or gradation image quality defects do not appear on the effective pixel region 12A, uniform image quality without unevenness can be obtained in the effective pixel region 12A.

  Here, when the pixel array of the pixel array unit 12 is considered based on n rows and m columns, an area corresponding to M rows from the last row n is set as an invalid pixel region 12B, so that image display is actually performed by that amount. The angle of view of the effective pixel area 12A is reduced. Therefore, an area where dummy pixels that do not contribute to image display are arranged below the pixel array unit 12 of n rows and m columns (front side in the vertical scanning direction) may be provided. At this time, the number of rows in the dummy pixel region (the number of pixels in the vertical direction) is set to M rows corresponding to the period from the start of the threshold cancel operation to the start of the write operation, as in the above case. As a result, the same angle of view (effective pixel region) of n rows and m columns as when the invalid pixel region 12B is not provided can be obtained.

  By the way, a power supply line for power supply potential Vss (hereinafter referred to as Vss line) wired in the pixel circuit 11 is generally used in order to reduce the wiring resistance value and to minimize the fluctuation of the power supply potential Vss. In addition, the thickness of the wiring of the Vss line is increased, and the area of the pixel circuit 11 must be increased accordingly. In contrast, in the active matrix organic EL display device according to the present embodiment, as described above, strip-shaped white and black streaks or gradation image quality defects caused by fluctuations in the power supply potential Vss are effective. Since it does not appear on the pixel region 12A, it is not necessary to worry about the fluctuation of the power supply potential Vss, and the thickness of the wiring of the Vss line can be reduced accordingly, so that the area of the pixel circuit 11 can be reduced. be able to. As a result, it is possible to realize high definition accompanying the increase in the number of pixels, and to provide a margin in the layout in the pixels, so that a high yield can be realized.

(Modification)
Here, as shown in the timing chart of FIG. 2, the longer the pulse width of the auto zero signal AZ, that is, the threshold cancellation period, the longer the period from the threshold cancellation operation start to the write operation start. It can be seen that the number of rows (the number of pixels in the vertical direction) increases. Therefore, the number of rows in the invalid pixel region 12B can be arbitrarily set by adjusting the pulse width of the auto-zero signal AZ, and in particular, the number of rows in the invalid pixel region 12B can be suppressed to be small by making the pulse width as narrow as possible.

  In particular, by delaying the rising timing of the auto zero signal AZ and narrowing the pulse width, the light emission period can be set longer by the amount corresponding to the delayed rising timing, and the variation in the threshold voltage Vth of the TFT 32 that is the driving transistor is canceled. At this time, there is also an advantage that the mobility of the TFT 32 can be canceled.

As for the period from the end of driving of the TFT 37 to the end of driving of the TFT 36 as well as the pulse width of the auto-zero signal AZ, if the period is long, the period from the start of the threshold cancel operation to the start of the write operation becomes longer. The number of rows of 12B increases. Accordingly, the number of rows in the invalid pixel region 12B can be arbitrarily set by adjusting the period from the end of the threshold cancel operation to the start of the write operation, and in particular, the number of rows in the invalid pixel region 12B can be suppressed to be small by shortening the period as much as possible. be able to.

[Second Embodiment]
In the present embodiment, the active matrix organic EL display device according to the first embodiment, that is, the pixel circuit (pixel) 11 shown in FIG. 1 is basically used, and the pixel circuits 11 are arranged in a matrix. An active matrix organic structure in which each pixel region from the first to the Nth row before the last row n is used as the effective pixel region 12A by the number of rows M + 1 corresponding to the period from the start of the threshold cancel operation to the start of the write operation. The EL display device employs a configuration in which the drive end (off) timing of the TFT 36 (third switching transistor) is set earlier than the write operation start timing.

  As described above, by setting the timing so that the driving of the TFT 36 is completed earlier than the start of the writing operation, the writing operation starts when the current flows into the Vss node through the TFT 36 or the current flows out from the Vss node. Therefore, the period in which band-like white or black streaks or gradation image quality defects occur due to fluctuations in the power supply potential Vss is not the period from the start of the threshold cancel operation to the start of the write operation. The period from the start of operation to the end of driving of the TFT 36 can be shortened.

  Accordingly, as the number of rows in the invalid pixel region 12B, the number of rows corresponding to the latter period, that is, the period from the start of the threshold cancellation operation to the end of driving of the TFT 36 may be set. It is sufficient to secure a smaller number of rows than in the case of the embodiment, and the ratio of the number of invalid pixel regions 12B to the effective pixel region 12A can be reduced, so that the field angle of the effective pixel region 12A can be set wider accordingly. . Further, when the dummy pixels having the same number of rows are added and the area of the dummy pixels is used as the invalid pixel area 12B, the number of dummy pixels to be added should be smaller than that in the first embodiment. Therefore, the increase in panel size accompanying the addition of dummy pixels can be minimized.

  In setting the timing so that the driving of the TFT 36 is finished earlier than the start of the writing operation, the driving timing of the TFT 36 (third switching transistor) is preferably set to the TFTs 38 and 39 (fourth and fifth switching transistors). ) Is set to the same drive timing. Specifically, as shown in FIG. 15, the rising and falling timings of the driving signal DS1 output from the first driving scanning circuit 19 are respectively determined based on the rising and falling timings of the auto zero signal AZ output from the auto zero circuit 21. The timing is the same as each timing.

  By performing such timing setting, as apparent from the comparison between the timing chart of FIG. 2 and the timing chart of FIG. 15, the period during which the image quality defect occurs can be further shortened, so that there are fewer invalid pixel areas 12B. It is only necessary to secure the number of rows, and the auto zero signal AZ for driving the FTFs 38 and 39 can be used as the drive signal DS1 for driving the TFT 36 (or the drive signal DS1 as the auto zero signal AZ). One transmission line can be reduced, and one of the first drive scanning circuit 19 and the auto zero circuit 21 can be reduced. As a result, it is possible to reduce the area of the pixel circuit 11 and to increase the definition (multiple pixels), and to reduce the frame of the display panel.

(Modification)
As a modification of the second embodiment, as shown in FIG. 16, the driving end of the TFT 36 (the falling timing of the driving signal DS1) is set earlier than the driving end of the TFTs 38 and 39 (the falling timing of the auto zero signal AZ). It is also possible to adopt a configuration to do so. By adopting this configuration, it is impossible to reduce the number of wiring lines for transmitting signals or to reduce one of the first drive scanning circuit 19 and the auto-zero circuit 21, but this is caused by fluctuations in the power supply potential Vss. Thus, the period in which the strip-shaped white stripes, black stripes, or gradation image quality failure occurs can be further shortened, so that the ratio of the number of pixels in the invalid pixel area 12B to the effective pixel area 12A can be further reduced.

  In each of the embodiments described above, the pixel circuit in which the first power supply potential is the ground potential GND, the second power supply potential is the positive power supply potential, and the third power supply potential is the ground potential GND (or the negative power supply potential). However, the present invention is not limited to this potential relationship. For example, a pixel circuit in which the first power supply potential is set to the negative power supply potential and the second power supply potential is set to the ground potential GND; The present invention can be similarly applied to a pixel circuit in which the power supply potential is set to the positive power supply potential.

  In each of the above-described embodiments, the case where the present invention is applied to an organic EL display device using an organic EL element as a pixel display element has been described as an example. The present invention is applicable to all display devices using a changing electro-optic element as a pixel display element.

FIG. 11 is a circuit diagram illustrating a configuration of an active matrix display device according to an application example of the invention and a pixel (pixel circuit) used in the display device. It is a timing chart with which it uses for operation | movement description of the pixel circuit which concerns on this application example. It is operation | movement explanatory drawing (the 1) of the pixel circuit which concerns on this application example. It is operation | movement explanatory drawing (the 2) of the pixel circuit which concerns on this application example. FIG. 11 is an operation explanatory diagram (part 3) of the pixel circuit according to the application example. FIG. 12 is an operation explanatory diagram (part 4) of the pixel circuit according to the application example. FIG. 12 is an operation explanatory diagram (No. 5) of the pixel circuit according to the application example. It is a characteristic view with which it uses for operation | movement description of the pixel circuit which concerns on this application example. It is a wave form diagram (the 1) with which it uses for description of the subject of the pixel circuit which concerns on this application example. It is a wave form diagram (the 2) with which it uses for description of the subject of the pixel circuit which concerns on this application example. It is explanatory drawing of the row which the influence of the fluctuation | variation of the power supply potential Vss reaches. It is a figure which shows a mode that a gradation arises toward the last line of a vertical scanning direction. It is a figure which shows the relationship between the effective pixel area | region and invalid pixel area | region in the active matrix type organic electroluminescence display which concerns on 1st Embodiment of this invention. It is a figure which shows a mode that a gradation does not appear in an effective pixel area | region but it generate | occur | produces in an invalid pixel area | region. It is a timing chart with which it uses for description of operation | movement of the pixel circuit used for the active matrix type organic electroluminescence display which concerns on 2nd Embodiment of this invention. It is a timing chart which concerns on the modification of 2nd Embodiment. It is a block diagram which shows the outline of a structure of an active matrix type organic electroluminescence display. It is a circuit diagram which shows the pixel circuit which concerns on a prior art example. It is a characteristic view which shows a time-dependent change of the IV characteristic of an organic EL element. It is a circuit diagram which shows the pixel circuit which concerns on the prior art example comprised by N channel TFT. It is a figure which shows the operating point of TFT which is a drive transistor in an initial state, and an organic EL element. It is a figure which shows the operating point of TFT which is a drive transistor after a time-dependent change, and an organic EL element. It is a circuit diagram showing a pixel circuit having a configuration in which the source of an N-channel TFT is connected to the ground potential.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pixel (pixel circuit), 12 ... Pixel array unit, 13 ... Scanning line, 14 ... First drive line, 15 ... Second drive line, 16 ... Auto zero line, 17 ... Data line, 18 ... Write scan circuit, 19 DESCRIPTION OF SYMBOLS ... 1st drive scanning circuit, 20 ... 2nd drive scanning circuit, 21 ... Auto zero circuit, 22 ... Data line drive circuit, 31 ... Organic EL element, 32 ... Drive transistor (TFT), 33, 34 ... Capacitor, 35-39 ... Switching transistor (TFT)

Claims (14)

An electro-optic element having one end connected to the first power supply potential;
An N-channel driving transistor having a source connected to the other end of the electro-optic element;
A first capacitor connected between a gate and a source of the driving transistor;
A first switching transistor that selectively takes in a signal corresponding to luminance information from the data line;
A second switching transistor connected between the drain of the driving transistor and a second power supply potential;
A third switching transistor connected between the source of the driving transistor and a third power supply potential;
A second capacitor connected between the gate of the drive transistor and the first switching transistor;
A fourth switching transistor connected between the gate and drain of the drive transistor; and
A pixel array unit in which pixel circuits each having a fifth switching transistor connected between a connection node between the first switching transistor and the second capacitor and a predetermined potential are arranged in a matrix;
Write scanning means for driving the first switching transistor;
First driving scanning means for driving the third switching transistor;
Second drive scanning means for driving the second switching transistor;
Third drive scanning means for driving the fourth and fifth switching transistors;
From the first row in the matrix array of the pixel array section, from the end of driving of the second switching transistor by the second driving scanning unit than the last row , the third switching transistor of the third switching transistor by the first driving scanning unit The pixel circuit up to the Nth row before the number of rows corresponding to the period until the end of driving ,
The first switching transistor is turned on via the write scanning means to capture a signal corresponding to luminance information from the data line,
After that, a display device comprising: control means for turning on the second switching transistor via the second drive scanning means to emit light from the electro-optic element, thereby making effective pixels used for image display. The control means corresponds to the threshold voltage of the drive transistor in the first capacitor in a non-light-emitting state of the electro-optic element prior to capturing a signal corresponding to luminance information by the first switching transistor. In order to maintain the voltage, the first and second switching transistors are turned off, and the fourth and fifth switching transistors are turned off via the third drive scanning means with the third switching transistor turned on. The display device according to claim 1. The display device according to claim 1, wherein the control unit can set the number of rows by adjusting a driving period of the fourth switching transistor. The display device according to claim 1, wherein the control unit is capable of setting the number of rows by adjusting a period from the end of driving of the fourth switching transistor to the start of driving of the first switching transistor. The display device according to claim 1, wherein the control unit causes the driving of the third switching transistor to end before the start of driving of the first switching transistor. The display device according to claim 5, wherein the control unit makes the drive timing of the third switching transistor the same as the drive timing of the fourth switching transistor. The display device according to claim 5, wherein the control unit causes the third switching transistor to finish driving earlier than the fourth switching transistor finishes driving. An electro-optic element having one end connected to the first power supply potential;
An N-channel driving transistor having a source connected to the other end of the electro-optic element;
A first capacitor connected between a gate and a source of the driving transistor;
A first switching transistor that selectively takes in a signal corresponding to luminance information from the data line;
A second switching transistor connected between the drain of the driving transistor and a second power supply potential;
A third switching transistor connected between the source of the driving transistor and a third power supply potential;
A second capacitor connected between the gate of the drive transistor and the first switching transistor;
A fourth switching transistor connected between the gate and drain of the drive transistor; and
A display having a pixel array portion in which pixel circuits each having a fifth switching transistor connected between a connection node between the first switching transistor and the second capacitor and a predetermined potential are arranged in a matrix. In driving the device,
From the first row in the matrix array of the pixel array section, the first row before the last row is the number of rows before the end of driving the second switching transistor to the end of driving the third switching transistor . The pixel circuits up to the Nth row are
The first switching transistor is turned on to take in a signal corresponding to luminance information from the data line,
Thereafter, the second switching transistor is turned on so that the electro-optic element emits light, whereby an effective pixel used for image display is obtained. Prior to capturing a signal corresponding to luminance information by the first switching transistor, the first capacitor should hold a voltage corresponding to the threshold voltage of the driving transistor in a non-light-emitting state of the electro-optic element. 9. The fourth and fifth switching transistors are driven off via the third drive scanning means in a state where the first and second switching transistors are turned off and the third switching transistor is turned on. A driving method of the display device. The display device driving method according to claim 8, wherein the number of rows can be set by adjusting a driving period of the fourth switching transistor. The method for driving a display device according to claim 8, wherein the number of rows can be set by adjusting a period from the end of driving of the fourth switching transistor to the start of driving of the first switching transistor. The method for driving a display device according to claim 8, wherein driving of the third switching transistor is finished earlier than driving of the first switching transistor. The driving method of the display device according to claim 12, wherein the driving timing of the third switching transistor is the same as the driving timing of the fourth switching transistor. The driving method of the display device according to claim 12, wherein the driving end of the third switching transistor is made earlier than the driving end of the fourth switching transistor.

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