JP4665424B2 - Display device and driving method thereof - Google Patents

Description

The present invention relates to a display device that drives an electro-optic element arranged for each pixel by current. Specifically, this is a matrix type display device in which the pixels are arranged in a matrix, and in particular, a so-called active matrix in which the amount of current flowing to the electro-optic element is controlled by an insulated gate field effect transistor provided in each pixel. The present invention relates to a type display device. For example, the present invention relates to an active matrix display device having an electro-optical element whose luminance is controlled by a current value such as an organic EL.

In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and a high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a liquid crystal display or the like in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit.
USP 5,684,365 JP-A-8-234683 JP 2003-323152 A

  FIG. 11 is a block diagram showing a configuration of a general organic EL display device. The display device 100 includes a pixel array unit 102 in which pixel circuits (PXLC) 101 are arranged in an m × n matrix, a horizontal selector (HSEL) 103, a write scanner (WSCN) 104, a drive scanner (DSCN) 105, a horizontal The signal lines DTL101 to DTL10n selected by the selector 103 and supplied with signals according to the luminance information, the scanning lines WSL101 to WSL10m selectively driven by the write scanner 104, and the scanning lines DSL101 to DSL10m selectively driven by the drive scanner 105 are displayed. Have. The write scanner (WSCN) 104 includes a shift register, operates in response to an externally input clock signal wsck, similarly sequentially transfers start pulses wssp input from the outside, and sequentially scans the scan lines WSL101 to WSL10m. And the line sequential scanning is performed. The drive scanner (DSCN) 105 also includes a shift register, operates in response to an externally input clock signal dsck, and similarly sequentially transfers start pulses dssp input from the outside, and sequentially scans the scan pulses DSL101 to DSL10m. And the line sequential scanning is performed.

FIG. 12 is a circuit diagram illustrating a configuration example of the pixel circuit illustrated in FIG. 11. As shown in the figure, the pixel circuit 101 is basically composed of a p-channel thin film field effect transistor (hereinafter referred to as TFT). That is, the pixel circuit 101 includes a drive TFT 111, a switching TFT 112, a sampling TFT 115, an organic EL element 117, and a storage capacitor C111. The pixel circuit 101 having such a configuration is arranged at an intersection between the signal line DTL101 and the scanning lines WSL101 and DSL101. The signal line DTL101 is connected to the drain of the sampling TFT 115, the scanning line WSL101 is connected to the gate of the sampling TFT 115, and the other scanning line DSL101 is connected to the gate of the switching TFT 112.

The drive TFT 111, the switching TFT 112, and the organic EL element 117 are connected in series between the power supply potential Vcc and the ground potential Vss. That is, the source of the drive transistor 111 is connected to the power supply potential Vcc, while the cathode of the organic EL element (light emitting element) 117 is connected to the ground potential Vss. In general, the organic EL element 117 is represented by a diode symbol because of its rectifying property. On the other hand, the sampling TFT 115 and the storage capacitor C111 are connected to the gate of the drive TFT111. The gate-source voltage of the drive TFT 111 is represented by Vgs.

The operation of the pixel circuit 101 is as follows. First, when the scanning line WSL101 is selected (low level here) and a signal is applied to the signal line DTL101, the sampling TFT 115 is turned on and the signal is written into the holding capacitor C111. The signal potential written in the storage capacitor C111 becomes the gate potential of the drive transistor 111. Subsequently, when the scanning line WSL101 is in a non-selected state (here, high level), the signal line DTL101 and the drive TFT 111 are electrically disconnected, but the gate potential Vgs of the drive TFT 111 is stably held by the holding capacitor C111. . Subsequently, when another scanning line DSL101 is selected (here, at a low level), the switching TFT 112 becomes conductive, and a drive current flows through the TFT 111, TFT 112, and the light emitting element 117 from the power supply potential Vcc toward the ground potential Vss. When the DSL 101 is in a non-selected state, the switching transistor 112 is turned off and the driving current does not flow. The switching TFT 112 is inserted to control the light emission time of the light emitting element 117.

The current flowing through the TFT 111 and the light emitting element 117 has a value corresponding to the gate-source voltage Vgs of the TFT 111, and the light emitting element 117 continues to emit light with a luminance corresponding to the current value. The operation of selecting the scanning line WSL101 and transmitting the signal given to the signal line DTL101 to the inside of the pixel circuit 101 as described above is hereinafter referred to as “writing”. As described above, once a signal is written, the light emitting element 117 continues to emit light at a constant luminance until the next rewriting.

As described above, in the pixel circuit 101, the value of the current flowing through the EL light emitting element 117 is controlled by changing the gate application voltage of the TFT 111 serving as the drive transistor in accordance with the input signal. At this time, the source of the p-channel type drive transistor 111 is connected to the power supply potential Vcc, and the TFT 111 always operates in the saturation region. Therefore, the drive transistor 111 is a constant current source having a value represented by the following formula (1).

Ids = (1/2) · μ · (W / L) · Cox · (Vgs−Vth) ² (1) where Ids represents the current flowing between the drain and source of the transistor operating in the saturation region. ing. Further, μ represents mobility, W represents channel width, L represents channel length, Cox represents gate capacitance, and Vth represents a threshold voltage of the transistor. As apparent from the equation (1), in the saturation region, the drain current Ids of the transistor is controlled by the gate-source voltage Vgs. Since the drive transistor 111 shown in FIG. 12 maintains Vgs constant, the drive transistor 111 operates as a constant current source, and the light emitting element 117 can emit light with constant luminance.

FIG. 13 is a graph showing a change with time of current-voltage (IV) characteristics of the organic EL element. In the graph, the curve indicated by the solid line indicates the characteristic in the initial state, and the curve indicated by the broken line indicates the characteristic after change with time. Generally, the IV characteristic of an organic EL element deteriorates over time as shown in the graph. On the other hand, in the pixel circuit shown in FIG. 12, since the drive transistor is driven at a constant current, the constant current Ids continues to flow through the organic EL element, and the IV characteristic of the organic EL element deteriorates. The light emission luminance does not deteriorate with time.

The pixel circuit shown in FIG. 12 is configured by a p-channel TFT. However, if the pixel circuit can be configured by an n-channel TFT, a conventional amorphous silicon (a-Si) process can be used for TFT fabrication. It becomes possible. As a result, the cost of the TFT substrate can be reduced, and development is expected.

FIG. 14 is a circuit diagram showing a configuration in which the p-channel TFT of the pixel circuit shown in FIG. 12 is replaced with an n-channel TFT. As shown in the figure, the pixel circuit 101 includes n-channel TFTs 111, 112, and 115, a storage capacitor C111, and an organic EL element 117 that is a light emitting element. The TFT 111 is a drive transistor, the TFT 112 is a switching transistor, and the TFT 115 is a sampling transistor. In the figure, DTL 101 represents a signal line, and DSL 101 and WSL 101 represent scanning lines, respectively. In the pixel circuit 101, the drain side of the TFT 111 as a drive transistor is connected to the power supply potential Vcc, and the source is connected to the anode of the EL element 117, thereby forming a source follower circuit.

FIG. 15 is a timing chart for explaining the operation of the pixel circuit shown in FIG. When the scanning pulse ws is applied to the scanning line WSL101 from the write scanner WSCN, the sampling transistor 115 is turned on, samples a signal from the signal line DTL101, and writes it to the storage capacitor C111. As a result, the gate potential of the drive transistor 111 is held at the sampled signal potential. This sampling operation is performed line-sequentially. That is, after the scanning pulse ws is applied to the first-stage scanning line WSL101, the scanning pulse ws is subsequently applied to the second-stage scanning line WSL102, and one pixel for each one horizontal period (1H) thereafter. It will be selected. Simultaneously with the selection of the WSL 101, the DSL 101 is also selected by the scanning pulse ds output from the drive scanner DSCN, so that the switching transistor 112 is turned on. As a result, a drive current flows to the light emitting element 117 via the drive transistor 111 and the switching transistor 112, and thus light emission is performed. In the middle of one field period (1F), the DSL 101 is in a non-selected state, and the switching transistor 112 is turned off. As a result, the light emission stops. The scanning line DSL101 controls the light emission time (duty) in one field period.

Here, FIG. 16A is a graph showing operating points of the drive transistor 111 and the EL element 117 in the initial state. In the figure, the horizontal axis represents the drain-source voltage Vds of the drive transistor 111, and the vertical axis represents the drain-source current Ids. As illustrated, the source potential is determined by the operating point of the drive transistor 111 and the EL element 117, and the voltage value varies depending on the gate voltage. Since the drive transistor 111 is driven in the saturation region, the drive current Ids having the current value defined in the above-described equation (1) is supplied with respect to Vgs corresponding to the source voltage at the operating point.

However, the IV characteristic of the EL element deteriorates with time as described above. As shown in (B), the operating point changes due to the deterioration over time, and the source voltage of the transistor changes even when the same gate voltage is applied. As a result, the gate-source voltage Vgs of the drive transistor 111 changes, and the flowing current value fluctuates. At the same time, the value of current flowing through the EL element 117 also changes. When the IV characteristic of the EL element 117 changes in this manner, the light emission luminance of the organic EL element changes with time in the pixel circuit having the source follower configuration shown in FIG.

In the active matrix type organic EL display, in addition to the above-described characteristic variation of the EL element, the threshold voltage of the n-channel TFT constituting the pixel circuit also changes with time. As is clear from the above equation (1), when the threshold voltage Vth of the drive transistor fluctuates, the drain current Ids changes. Thereby, even if the same gate voltage Vgs is given, there is a problem that the light emission luminance changes due to the variation of Vth.

In view of the above-described problems of the conventional technology, it is a general object of the present invention to provide a display device that can stably drive an electro-optic element even when the threshold voltage of a transistor constituting a pixel circuit changes with time. And In particular, it is a specific object of the present invention to provide a circuit configuration and a driving method for stabilizing the operation of a compensation function in a display device to which a compensation function for a threshold voltage variation of a transistor is added.

In order to achieve this purpose, the following measures were taken. That is, the present invention includes a pixel array section and a peripheral driving section that drives the pixel array section, and the pixel array section is composed of pixels arranged at portions where a plurality of scanning lines and signal lines intersect, and each scanning line In response to the start pulse and the clock signal, the peripheral driving unit scans the pixels of the pixel array unit line-by-line in units of stages and outputs each pixel of each horizontal period. A display device that writes video signals to a stage and repeats this line-sequential scanning for each field, and each pixel includes an electro-optic element, a storage capacitor, a sampling transistor, a drive transistor, and a threshold voltage cancel circuit . The sampling transistor operates when selected by a first scanning pulse sent from a first scanning line, samples a video signal from the signal line and holds it in the holding capacitor, and the drive transistor holds the holding capacitor. The threshold voltage cancel circuit is selected by the second scanning pulse sent from the second scanning line prior to the current driving of the electro-optic element. In this period, the threshold voltage of the drive transistor is detected, and a potential necessary for canceling the influence is held in the storage capacitor in advance. The peripheral driving unit includes a first scanner, a selector, and a second scanner. The first scanner performs line sequential scanning of the first scanning line by sequentially transferring the first start pulse according to the clock signal, and sequentially applies the first scanning pulse to each first scanning line every horizontal period. The output is used to select each pixel in units of stages, and the selector supplies a video signal to each signal line in synchronization with the line sequential scanning, thereby writing the video signal to the stage of the selected pixel, and Similarly, the two scanners sequentially transfer the second start pulse in accordance with the clock signal to perform line sequential scanning of the second scanning line, and sequentially output the second scanning pulse to each second scanning line every horizontal period. Then, the threshold voltage cancel circuit of each pixel is driven in units of stages. . The period of the clock signal is set to be twice as long as one horizontal period. On the other hand, the pixel array section is composed of odd-numbered pixels corresponding to an odd number of scanning lines. It is necessary to match the phase of the clock signal between them, and an adjustment interval for phase matching is inserted into the clock signal in the blanking period between both fields. The second scanner sets the width and input timing of the second start pulse appropriately, the second scanning pulse at the head stage rises after the adjustment section, and the second scanning pulse at the last stage reaches the adjustment section. The second scanner is characterized in that the second scanner can always sequentially output the second scanning pulse having the same pulse width regardless of the presence of the adjustment section during the line sequential scanning.

Preferably, the clock signal is set to one horizontal period with a minimum adjustment interval inserted in the blanking period for phase alignment. The threshold voltage cancel circuit includes a detection transistor, and the detection transistor has a source / drain connected to a drain / gate of the drive transistor, a gate connected to a second scanning line, The detection transistor operates according to the width of the second scan pulse sent from the second scan line, and detects the threshold voltage of the drive transistor. The electro-optical element is an organic EL element that emits light by current driving. The sampling transistor and the drive transistor are N-type thin film transistors.

The present invention also includes a pixel array section and a peripheral driving section for driving the pixel array section, and the pixel array section is composed of pixels arranged at portions where a plurality of scanning lines and signal lines intersect, and each scanning line Each pixel includes an electro-optical element, a storage capacitor, a sampling transistor, a drive transistor, and a threshold voltage cancel circuit, and the peripheral driver includes a first stage. A scanner, a selector, and a second scanner, and in response to a start pulse and a clock signal, the pixels of the pixel array section are line-sequentially scanned in units of lines, and video signals are written in the respective stages of pixels every horizontal period A display device driving method in which sequential scanning is repeated for each field, wherein the pixel array unit operates the sampling transistor by a first scanning pulse sent from a first scanning line. And sampling the video signal from the signal line and holding it in the holding capacitor, and subsequently operating the drive transistor to drive the electro-optic element in accordance with the signal potential held in the holding capacitor, Prior to the current drive of the electro-optic element, the threshold voltage cancel circuit is operated during a period selected by the second scan pulse sent from the second scan line, and the threshold voltage of the drive transistor is detected in advance. While the potential necessary for canceling the influence is held in the holding capacitor, the first driver sequentially transfers the first start pulse according to the clock signal on the peripheral driver side. A line-sequential scan of one scan line is performed, and a first scan pulse is sequentially output to each first scan line for each horizontal period to select each pixel in units of stages, and the selector includes: The video signal is supplied to each signal line in synchronization with the line sequential scanning, and the video signal is written to the stage of the selected pixel. The second scanner similarly applies the second start pulse in response to the clock signal. By performing sequential transfer, line sequential scanning of the second scanning line is performed, and a second scanning pulse is sequentially output to each second scanning line every horizontal period to drive the threshold voltage cancel circuit of each pixel in units of stages, The period of the clock signal is set to be twice as long as one horizontal period. On the other hand, the pixel array section is composed of odd-numbered pixels corresponding to an odd number of scanning lines. The phase of the clock signal needs to be synchronized between the two fields, and a phase alignment adjustment section is inserted into the clock signal in the blanking period between the two fields. Input By appropriately setting the imming so that the second scanning pulse of the first stage rises after the adjustment section and the second scanning pulse of the last stage falls before the adjustment section, the second scanner During the line sequential scanning, the second scanning pulse having the same pulse width can always be sequentially output regardless of the presence of the adjustment section.

Preferably, the clock signal is set to one horizontal period with a minimum adjustment interval inserted in the blanking period for phase alignment.

According to the present invention, the pixel circuit adds a threshold voltage cancel circuit around the drive transistor. The threshold voltage cancel circuit detects the threshold voltage of the drive transistor prior to the current drive of the electro-optic element, holds the potential necessary for canceling the influence in advance in the holding capacitor, and applies it to the gate of the drive transistor. Yes. Thereby, even if the threshold voltage of the drive transistor changes with time, the electro-optical element can be stably driven. On the other hand, on the peripheral driver side, the first scanner sequentially transfers the first start pulse according to the clock signal to perform line sequential scanning of the first scanning line, and selects each pixel in units of stages. Similarly, the second scanner sequentially transfers the second start pulse according to the clock signal to perform line sequential scanning of the second scanning line, and drives the threshold voltage cancel circuit of each pixel in units of stages. Here, while the period of the clock signal is set to be twice as long as one horizontal period, the pixel array section is composed of an odd number of pixels corresponding to an odd number of scanning lines. The phase of the clock signal needs to be matched between the two, and a phase adjustment adjustment section is inserted into the clock signal during the blanking period between both fields. On the other hand, the second scanner sets the width and input timing of the second start pulse appropriately, the second scanning pulse in the first stage rises after the adjustment period, and the second scanning pulse in the last stage precedes the adjustment period. Thus, the second scanner can always sequentially output the second scanning pulse having the same pulse width regardless of the presence of the adjustment interval during line sequential scanning. On the other hand, the detection transistor of the threshold voltage cancel circuit operates according to the width of the second scan pulse sent from the second scan line, and detects the threshold voltage of the drive transistor. Since the width of the second scan pulse is always kept constant without being affected by the adjustment interval inserted in the blanking period as described above, the detection of the threshold voltage of the drive transistor is stable over the entire pixel array section. And uniform image quality without unevenness can be obtained.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a configuration of a pixel circuit incorporated in a display device according to the present invention. This pixel circuit has a threshold voltage canceling function. In addition, a bootstrap function that is a compensation function for the characteristic variation of the electro-optic element is also provided. The pixel circuit 101 includes n-channel TFTs 111 to TFT 116, capacitors C 111 and C 112, a light emitting element 117 including an organic EL element (OLED: electro-optical element), and nodes ND 111 to ND 114. In FIG. 1, DTL 101 indicates a signal line, WSL 101 indicates a first scanning line, and DSL 101 indicates a drive line. AZL101 represents a second scanning line, and BSL101 represents a bootstrap drive line. Among these components, the TFT 111 constitutes a driving field effect transistor (drive transistor), the TFT 115 constitutes a sampling transistor, the TFT 113 constitutes a threshold voltage detection transistor, and the capacitor C111 constitutes a storage capacitor element. Yes.

In the pixel circuit 101, a light emitting element (OLED) 117 is connected between the source of the TFT 111 and the cathode potential Vcat. Specifically, the anode of the light emitting element 117 is connected to the source of the TFT 111, and the cathode side is connected to the cathode potential Vcat. A node ND 111 is configured by a connection point between the anode of the light emitting element 117 and the source of the TFT 111. The source of the TFT 111 is connected to the drain of the TFT 114 and the first electrode of the capacitor C111, and the gate of the TFT 111 is connected to the node ND112. The source of the TFT ll4 is connected to a fixed potential (ground potential Vss in this embodiment), and the gate of the TFT 114 is connected to the drive line BSL101. The second electrode of the capacitor C111 is connected to the node ND112. The source and drain of the sampling TFT 115 are connected to the signal line DTL101 and the node ND114, respectively. The gate of the TFT 115 is connected to the scanning line WSL101.

Thus, in the pixel circuit 101 according to the present embodiment, the capacitor C111 is connected between the gate and the source of the TFT 111 as the drive transistor, and the source potential of the TFT 111 is connected to the ground potential Vss through the TFT 114 as the switch transistor. It is configured as follows. In particular, the capacitor C111, the TFT 114, and the node ND111 constitute a bootstrap circuit. The bootstrap circuit has a compensation function for the characteristic variation of the electro-optic element 117.

The pixel circuit includes a threshold voltage cancel circuit in addition to the bootstrap circuit. The threshold voltage cancel circuit basically includes a drive transistor 111, a switching transistor 112, a detection transistor 113, and a storage capacitor C111. In addition to these, the pixel circuit includes a coupling capacitor C112 and a switching transistor. The source / drain of the detection transistor 113 is connected between the gate and drain of the drive transistor 111. The drain of the switching transistor 116 is connected to the drain of the sampling transistor 115, and the source is supplied with the offset voltage Vofs. The coupling capacitor C112 is interposed between the node ND114 on the sampling transistor 115 side and the node ND112 on the drive transistor side. A scanning line AZL 101 for canceling a threshold voltage (Vth) is connected to the gates of the detection transistor 113 and the switching transistor 116.

FIG. 2 is a timing chart for explaining the operation of the pixel circuit shown in FIG. This pixel circuit sequentially performs Vth correction, signal writing, and bootstrap operation during one field. Vth correction and signal writing are performed during the non-light emission period of one field, and the bootstrap operation is performed at the beginning of the light emission period. This timing chart shows a first scanning pulse ws applied to the first scanning line WSL101, a second scanning pulse az applied to the second scanning line AZL101, a driving pulse ds applied to the driving line DSL101, and other driving lines. The time relationship of the other drive pulse bs applied to BSL101 is represented. In the light emission period T1, only the drive pulse ds is on (high level), and the remaining pulses ws, bs, and az are off (low level). In the non-light emitting period, the pulses bs and az rise in the first period T2, and a threshold cancel preparation operation is performed. Subsequently, in the threshold cancellation period T3, the pulse ds falls and the threshold cancellation operation is executed. That is, Vth of the drive transistor is detected and the detected Vth is held in the storage capacitor. Thereafter, when the period proceeds to the writing period T4, the scanning pulse ws is turned on, and the video signal Vin is sampled (written) in the storage capacitor. Then, after the pulse bs falls, the next light emission period T5 starts.

In the light emission period T5, the drive pulse ds rises to a high level and starts light emission, and a bootstrap operation is performed. As a result, the signal potential Vin applied to the gate of the drive transistor 111 rises by Vx according to the ID characteristic of the light emitting element 117. In this way, the pixel circuit 101 adds Vth and Vx in addition to the net signal component Vin applied to the gate of the drive transistor 111. Even if Vth and Vx change, the influence can always be canceled, so that the light emitting element 117 can be driven stably.

Hereinafter, the configuration and operation of the display device including the pixel circuit 101 shown in FIG. 1 will be described specifically and in detail with reference to FIGS. First, in the light emitting period T1 of the EL element, as shown in FIG. 3A, only the transistor 112 is on. At this time, the drive transistor 111 is designed to operate in a saturation region, and the current Ids flowing through the EL element takes a value represented by the above-described equation (1).

Subsequently, in the non-light emitting period, in the preparation period T2, as shown in FIG. 3B, by turning on the transistor 114, the transistor 116, and the detection transistor 113, the voltage applied to the EL element becomes Vss, and the drive transistor The gate of 111 is set to the power supply voltage Vcc. At this time, since the Vss is smaller than the sum of the cathode voltage Vcat of the EL element and the threshold voltage Vthel of the EL element, the EL element does not emit light. That is, Vss ≦ Vcat + Vthel. Even when the transistor 114 is turned on, the voltage held in the holding capacitor C111, that is, the gate-source voltage Vgs of the drive transistor 111 does not change, so that the drain current Ids flows as shown in the figure.

Next, in the threshold cancellation period T3, the transistor 112 is turned off as shown in FIG. Since the gate and drain of the drive transistor 111 are connected via the detection transistor 113, the drive transistor 111 operates in the saturation region. Further, since the capacitors C111 and C112 are connected in parallel to the gate of the drive transistor 111, the gate-drain voltage Vgd decreases with time as shown in FIG. 4B. After a predetermined time has elapsed, the gate-source voltage Vgs of the drive transistor 111 becomes the threshold voltage (Vth) of the drive transistor 111. At this time, Vofs−Vth is charged in the capacitor C112, and Vth is charged in the capacitor C111. At this time, by turning off the transistor 116 and the detection transistor 113, the above-described potential difference is held in the respective capacitors C111 and C112.

When the writing period T4 further proceeds, as shown in FIG. 5A, the sampling transistor 115 is turned on, the input voltage Vin is input to the node ND114, and the voltage change amount at the node ND114 is coupled to the gate of the drive transistor 111. Ring. At this time, the gate voltage of the drive transistor 111 is a value Vth, and the coupling amount ΔV is determined by the capacitance C1 of the capacitor C111, the capacitance C2 of the capacitor C112, and the parasitic capacitance C3 of the drive transistor 111 as shown in the following equation (2). Is done. If C1 and C2 are sufficiently larger than C3, the coupling amount ΔV to the gate is determined only by C1 and C2.
ΔV = (C2 / C1 + C2 + C3) · (Vin−Vofs) (2)

Subsequently, as shown in FIG. 5B, after the writing is completed, the transistor 114 is turned off, the transistor 112 is turned on, and the drain voltage of the drive transistor 111 is raised to the power supply voltage Vcc. Since the gate-source voltage Vgs of the drive transistor 111 is constant, the drive transistor 111 passes a constant current Ids to the EL element 117, and the potential of the node ND111 in the figure rises to a voltage Vx at which a current Ids flows through the EL element 117. The EL element 117 emits light. Also in this circuit, the EL characteristic of the EL element changes as the light emission time becomes longer. Therefore, the potential Vx of the node ND111 also changes in the drawing. However, since the gate-source voltage Vgs of the drive transistor 111 is maintained at a constant value by the bootstrap function, the current flowing through the EL element does not change. That is, if one end (node ND111) of the storage capacitor C111 increases by Vx, the other end (node ND112) of the storage capacitor C111 automatically increases by Vx accordingly, so that Vgs of the drive transistor 111 is always kept constant. Be drunk. Therefore, even if the IV characteristic of the EL element deteriorates, the constant current Ids always flows and the luminance of the EL element does not change.

FIG. 6 is a schematic block diagram showing a display device in which the pixel circuits 101 shown in FIG. 1 are arranged in a matrix. As shown in FIG. 6, the display device 100 includes a pixel array unit 102 in which pixel circuits (PXLC) 101 are arranged in an m × n matrix and a peripheral drive unit. The peripheral driving unit includes a horizontal selector (HSEL) 103, a write scanner (WSCN) 104, a drive scanner (DSCN) 105, another drive scanner (BSCN) 106, and an auto zero scanner (AZRD) 107. In addition to these, signal lines DTL101 to DT110n selected by the horizontal selector 103 and supplied with video signals according to luminance information, first scanning lines WSL101 to WSL10m selectively driven by the write scanner (first scanner) 104, drive Drive lines DSL101 to DSL10m selectively driven by the scanner 105, drive lines BSL101 to BSL10m selectively driven by the other drive scanner 106, and second scan lines AZL101 to AZL10m selectively driven by the auto zero scanner (second scanner) 107. Have The write scanner (WSCN) 104 includes a shift register, operates in response to an externally input clock signal wsck, and similarly sequentially transfers start pulses wssp input from the outside, and sequentially transmits the scan pulses to the first scan line WSL101. Applying to ~ WSL10m, the line sequential scanning is performed. The drive scanner (DSCN) 105 also includes a shift register, operates in response to an externally input clock signal dsck, and similarly sequentially transfers start pulses dssp input from the outside, and sequentially performs the first scan pulse to the first scan. The line sequential scanning is performed by applying to the lines DSL101 to DSL10m. The other drive scanner (BSCN) 106 also includes a shift register, operates in response to an externally input clock signal bsck, and sequentially transfers start pulses bssp input from the outside, and sequentially transmits the scan pulses to the scan line BSL101. Apply to DSL10m to perform line sequential scanning. The auto-zero scanner (AZRD) 107 also includes a shift register, operates in accordance with an externally input clock signal azck, sequentially transfers start pulses azsp input from the outside, and sequentially scans the second scan pulse to the second scan. The line sequential scanning is performed by applying to the lines AZL101 to AZL10m. In the pixel array unit 102, the pixel circuits 101 are arranged in a matrix of m × n. However, in FIG. 6, in order to simplify the drawing, a matrix of 2 (= m) × 3 (= n) is used. An example of arrangement is shown.

FIG. 7 is a schematic diagram illustrating a connection relationship between the pixel circuit 101 included in the pixel array unit 102 and each scanner included in the peripheral driving unit in the display device 100 illustrated in FIG. 6. As shown in the figure, this circuit includes n-channel TFTs 111 to 116, capacitors C111 and C112, a light emitting element 117 composed of an organic EL element, a first node ND111, a second node ND112, a third node NDll3, and a fourth. Node ND114. In FIG. 7, DTL 101 indicates a signal line, WSL 101 indicates a first scanning line, DSL 101 and BSL 101 indicate drive lines, and AZL 101 indicates a second scanning line. Among these components, the TFT 111 constitutes a drive transistor, the TFT 113 constitutes a detection transistor, the TFT 115 constitutes a sampling transistor, the capacitor C111 constitutes a holding capacitor element, and the capacitor C112 constitutes a coupling capacitor element. ing.

  In the pixel circuit 101, a TFT 112, a third node ND113, a TFT 111 as a drive transistor, a first node ND111, and a light emitting element (OLED) 117 are connected in series between a power supply potential Vcc and a cathode potential Vcat. Yes. Specifically, the cathode of the light emitting element 117 is connected to the cathode potential Vcat, the anode is connected to the first node ND111, the source of the TFT 111 is connected to the first node ND111, and the drain of the TFT 111 is the third node. The source / drain of the TFT 112 is connected between the third node ND113 and the power supply potential Vcc. The gate of the TFT 111 is connected to the second node ND112, and the gate of the TFT 112 is connected to the drive line DSL111. The source / drain of the TFT 113 is connected between the second node ND112 and the third node ND113, and the gate of the TFT 113 is connected to the second scanning line AZL101. The drain of the TFT 114 is connected to the first node ND111 and the first electrode of the capacitor C111, the source is connected to a fixed potential (ground potential Vss in this embodiment), and the gate of the TFT 114 is connected to the drive line BSL101. The second electrode of the capacitor C111 is connected to the second node ND112. The first electrode of the capacitor C112 is connected to the second node ND112, and the second electrode is connected to the fourth node ND114. The source and drain of the TFT 115 are connected to the signal line DTL101 and the fourth node ND114, respectively. The gate of the TFT 115 is connected to the scanning line WSL101. Further, the source and drain of the TFT 116 are connected between the fourth node ND114 and the predetermined potential Vofs. The gate of the TFT 116 is connected to the second scanning line AZL101.

As shown in FIGS. 6 and 7, the actual display device includes a peripheral drive unit in addition to the panel constituting the pixel array unit. The peripheral driving unit includes various scanners. Each scanner basically includes a shift register, operates in response to a clock signal ck, sequentially transfers start pulses sp, and generates scan pulses necessary for line-sequential scanning of drive lines and scan lines. For example, paying attention to the write scanner WSCN, the clock signal wsck, the start pulse wssp, and the scan pulse ws are as shown in the timing chart of FIG. As shown in FIG. 8, the scanning pulse ws corresponding to each stage of the pixel is generated using the start pulse wssp and the clock signal wsck inputted to the write scanner, and outputted to the gate line of each stage. As for the input clock signal wsck, generally, the width of one pulse (1ck) is 1H as shown in FIG. That is, the cycle of the clock signal wsck is 2H. The same applies to the other clock signals azck, dsck, and bsck.

FIG. 9 is a timing chart showing a clock signal azck and a start pulse azsp input to a general auto zero scanner AZRD, and a scan pulse az output from the auto zero scanner. By the way, when 1F is an odd multiple of 1H, that is, 1F = odd number H (that is, when the scanning lines are composed of an odd number), the clock signal azck input from the outside is the first field and the second field. In order to maintain continuity between the periods, the period becomes discontinuous as shown in FIG. 9 during the blanking period. Here, when the Vth detection period is relatively long, the start pulse azsp is set to be long, but the rise of the first stage of az occurs before the part (adjustment interval) where the period of azck existing in the blanking period becomes long. End up. As a result, the period of the scan pulse az output to the gate line with respect to the input start pulse azsp varies depending on each stage, and the gate potential depends on the width of the scan pulse az as shown in FIG. Changes. That is, the threshold voltage detection level varies between the stages, and the threshold voltage canceling operation varies. In the illustrated example, the scanning pulse az applied to the first to third stages is longer than the scanning pulse az applied to the fourth and subsequent stages. This phenomenon causes variations in the detection of Vth, resulting in a problem that a uniform image cannot be obtained during raster display of the panel.

In order to deal with the above problems, the present invention, as shown in FIG. 10, when 1ck = 1H (that is, the period of the clock signal azck = 2H) and 1F = odd number H, the clock signal azck in the blanking period is The lengthening adjustment period is set to 2H by adding the minimum unit, that is, 1H, so that the first stage of the scanning pulse az rises after the portion where the clock signal azck becomes long. Also, at the falling edge, the falling edge of the scanning pulse az at the pixel final stage comes before the adjustment portion where the clock signal azck becomes longer. By setting the width and input timing of the start pulse azsp as described above, the length of the scan pulse az input to the pixels at each stage can be made constant, and as a result, uniform image quality can be obtained. Similarly to other clock signals wsck, dsck and bsck, azck can also be set to 1ck = 1H, and all clock signals can be shared. As a result, the area of the scanner can be reduced. The present invention is applicable to all pixel circuits in which 1F = odd number H and Vth cancellation function.

As described above, the display device according to the present invention shown in FIG. 7 basically includes the pixel array unit 102 and the peripheral driving unit that drives the pixel array unit 102. The pixel array unit 102 includes pixels 101 arranged at portions where a plurality of scanning lines and signal lines intersect, and each stage of the pixels 101 is configured corresponding to each scanning line (see FIG. 6). . In response to the start pulse sp and the clock signal ck, the peripheral driver scans the pixels 101 of the pixel array unit 102 line by line in units of stages, and writes a video signal to each stage of the pixels 101 every horizontal period (1H). Line sequential scanning is repeated for each field. Each pixel 101 includes an electro-optic element 117, a storage capacitor C111, a sampling transistor 115, a drive transistor 111, and a threshold voltage cancel circuit. The sampling transistor 115 operates when selected by the first scanning pulse sent from the first scanning line WSL101, samples the video signal from the signal line DTL101, and holds it in the holding capacitor C111. The drive transistor 111 current-drives the electro-optic element 117 according to the signal potential held in the holding capacitor C111. The threshold voltage cancel circuit (see FIG. 1) operates during a period selected by the second scanning pulse sent from the second scanning line AZL 101 prior to the current driving of the electro-optic element 117, and sets the threshold voltage of the drive transistor 111. A potential necessary for detecting and canceling the influence in advance is held in the holding capacitor C111. The peripheral drive unit includes a first scanner 104, a selector 103, and a second scanner 107. The first scanner 104 performs line sequential scanning of the first scanning line WSL101 by sequentially transferring the first start pulse wssp according to the clock signal wsck, and sequentially performs the first scanning pulse for each horizontal period. Each pixel 101 is selected in units of stages by outputting to the line WSL. The selector 103 supplies a video signal to each signal line DTL in synchronization with the line sequential scanning, and writes the video signal to the stage of the selected pixel 101. The second scanner 107 performs line sequential scanning of the second scanning line AZL by sequentially transferring the second start pulse azsp according to the clock signal azck, and sequentially performs the second scanning pulse at each second scanning every horizontal period. The threshold voltage cancel circuit of each pixel 101 is driven in units of stages by outputting to the line AZL.

Here, the cycle of the clock signal azck is set to be twice as long as one horizontal period, while the pixel array unit 102 includes odd-numbered pixels PXLC corresponding to odd-numbered scanning lines AZL101 to AZL10m (m = odd number). Therefore (see FIG. 6), it is necessary to match the phase of the clock signal azck between the previous field and the next field, and in the blanking period between both fields, the phase adjustment adjustment section (see FIG. 10). In the example, the adjustment section has a minimum 1H, half cycle) inserted. The second scanner AZRD appropriately sets the width and input timing of the second start pulse azsp, the second scanning pulse az at the leading stage rises after the adjustment period, and the second scanning pulse az at the final stage sets the adjustment period. I'm trying to fall forward. Therefore, the second scanner AZRD can always sequentially output the second scanning pulse az having the same pulse width regardless of the presence of the adjustment interval during line sequential scanning. On the other hand, the threshold voltage cancel circuit includes a detection transistor 113. The detection transistor 113 has its source / drain connected to the drain / gate of the drive transistor 111, and its gate connected to the second scanning line AZL. The detection transistor 113 operates according to the width of the second scan pulse az sent from the second scan line AZL and detects the threshold voltage of the drive transistor 111. Since the width of the second scanning pulse is always maintained constant without being affected by the adjustment interval inserted in the blanking period, the detection of the threshold voltage is stabilized over the entire pixel array unit 102, and there is no unevenness. Image quality can be obtained. According to the present invention, when 1F = odd H, the length of the start pulse azsp input to the auto zero scanner AZRD is optimally defined in all pixel circuits having the Vth cancel operation, even when 1F is odd H. The length of the Vth detection scanning pulse az input to each pixel stage can be made constant, and the Vth detection period can be made constant, so that uniform image quality without unevenness can be obtained. Further, according to the present invention, since all the scanners including the auto zero scanner can be configured with 1 ck = 1H, the area of the scanner can be reduced.

It is a circuit diagram which shows the pixel circuit used as the principal part of the display apparatus concerning this invention. 2 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 1. FIG. 2 is a schematic diagram for explaining an operation of the pixel circuit shown in FIG. 1. FIG. 2 is a schematic diagram for explaining an operation of the pixel circuit shown in FIG. 1. FIG. 2 is a schematic diagram for explaining an operation of the pixel circuit shown in FIG. 1. It is a block diagram which shows the whole structure of the display apparatus containing the pixel circuit shown in FIG. FIG. 7 is a wiring diagram illustrating a connection relationship between individual pixel circuits and peripheral driving units in the display device illustrated in FIG. 6. It is a timing chart with which it uses for description of operation | movement of the display apparatus shown in FIG. It is a timing chart with which it uses for description of operation | movement of the display apparatus shown in FIG. It is a timing chart with which it uses for description of operation | movement of the display apparatus shown in FIG. It is a block diagram which shows an example of the conventional display apparatus. It is a circuit diagram which shows an example of the pixel circuit contained in the conventional display apparatus. It is a graph which shows the time-dependent change of the characteristic of an EL element. It is a circuit diagram which shows the other example of the conventional pixel circuit. FIG. 15 is a timing chart for explaining the operation of the pixel circuit shown in FIG. 14. FIG. It is a graph which shows the operating point of a drive transistor and an EL element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Display apparatus, 101 ... Pixel circuit, 102 ... Pixel array part, 103 ... Horizontal selector, 104 ... Write scanner, 105 ... Drive scanner, 106 ... Drive scanner, 107 ... Auto-zero scanner 111 ... Drive transistor 112 ... Transistor 113 ... Detection transistor 114 ... Transistor 115 ... Sampling transistor 116 ... Transistor 117 ... Light emitting element, C111: Retention capacity, C112: Coupling capacity

Claims (7)

Including a pixel array section and a peripheral driving section for driving the pixel array section,
Picture element array portion consists respective distribution pixel in the portion where the plurality of scanning lines and the signal lines intersect is configured that each stage of the pixels corresponding to each scanning line,
Peripheral driving section in response to a start pulse and a clock signal, image pixels of the element array portion with line-sequential scanning by the stage unit writing a video signal to each stage of one horizontal period each pixel, the field of this line-sequential scanning A display device that repeats every time,
The pixel array section is composed of odd-numbered pixels corresponding to the odd number of scanning lines,
Each pixel includes an electro-optic element, a storage capacitor, a sampling transistor, a drive transistor, and a threshold voltage cancel circuit,
Sa pump ring transistor operates when selected by the first scan pulse sent from the first scanning line, samples the video signal held in the hold capacitor from the signal Line,
Drive transistor, and a current driving the electric optical element in accordance with the signal potential held in the hold capacitor,
Threshold voltage cancellation circuit operates during the period selected by the second scan pulse sent from the second scan line prior to the current driving the electric optical element in advance the effect to detect the threshold voltage of the drive transistor the potential necessary to cancel are those allowed to hold the hold capacitance,
Peripheral driving section includes a first scanner, a selector, and a second scanner,
The first scanner, by sequentially transferring the first start pulse in response to a first clock signal performs line sequential scanning of the first scan line, the first scan pulse sequentially each first scan line in each horizontal period To select each pixel in steps,
Selector supplies a video signal in synchronization with the line sequential scanning to the signal lines, than Te, writes the video signal to the stage of the selected pixel,
The second scanner performs line sequential scanning of the second scanning line by sequentially transferring the second start pulse in accordance with the second clock signal having the same cycle as the first clock signal, and performs second scanning every horizontal period. A scan pulse is sequentially output to each second scan line to drive a threshold voltage cancel circuit of each pixel in units of stages,
The second clock signal has an adjustment period for phase alignment inserted in a part of the blanking period between the previous field and the next field, and the period in the normal period excluding the adjustment period is one horizontal period. fold is set to the,
The second scanner, when the width of the second start pulse exceeds one horizontal period, rising after the second scan pulse of the previous Atamadan is adjusted interval, before the second scan pulse in the final stage of the adjustment section as falls, set the width and the input timing of the second start pulse, than Te, in line-sequential scanning, despite the presence of the adjustment period, always sequential output enable der a second scan pulse having the same pulse width Viewing apparatus that. The second clock signal, the display device according to 請 Motomeko 1 adjustment interval that is set to one horizontal period. The threshold voltage cancellation circuit includes a detection transistor,
Detection known transistor has its source / drain connected to the drain / gate of the drive transistor, its gate connected to the second scan line, according to the width of the second scan pulse sent from the second scan line the display device according to 請 Motomeko 1 or claim 2 detect the threshold voltage of the operation to drive the transistor Te. Electrical optical element, a display device according to any one of claims 3 to 請 Motomeko 1 Ru Oh organic EL element which emits light by current driving. Sa pump ring transistors and the drive transistor display device according to any one of claims 4 to 請 Motomeko 1 Ru thin film transistor der of N-type. Including a pixel array section and a peripheral driving section for driving the pixel array section,
Picture element array portion consists respective distribution pixel in the portion where the plurality of scanning lines and the signal lines intersect, with each stage of the pixels corresponding to each scanning line is constituted, the odd scan lines Corresponding to the odd number of pixels,
Each pixel includes an electro-optic element, a storage capacitor, a sampling transistor, a drive transistor, and a threshold voltage cancel circuit,
The peripheral driver includes a first scanner and the selector and the second scanner, a start pulse and responsive to a clock signal, each stage of one horizontal period each pixel line-sequentially scan the pixels of the image element array portion in stage units A video signal is written to the display device, and this line sequential scanning is repeated for each field.
Picture element array portion side,
Operating the service pump ring transistor by a first scan pulse sent from the first scanning line, samples the video signal held in the hold capacitor from the signal Line,
By operating the drive transistor Subsequently, while the current driving the corresponding electrical optical element to the signal potential held in the hold capacitor,
Prior to the current driving the electric optical element, to the period of time that is selected by the second scanning pulse sent from the second scanning line is operated the threshold voltage cancellation circuit, in advance the effect to detect the threshold voltage of the drive transistor while are kept on the hold capacitance the potential required to cancel,
The peripheral driving part side,
First scanner, a first a first start pulse sequentially performs line sequential scanning of the first scanning line by transferring in response to the clock signal, the first scan pulse sequentially each first scan line in each horizontal period To select each pixel in steps,
Selector is in synchronization with the line sequential scanning to supply a video signal to each signal line, than Te, writes the video signal to the stage of the selected pixel,
The second scanner performs line sequential scanning of the second scanning line by sequentially transferring the second start pulse in accordance with the second clock signal having the same cycle as the first clock signal, and performs second scanning every horizontal period. A scan pulse is sequentially output to each second scan line to drive a threshold voltage cancel circuit of each pixel in units of stages,
The second clock signal has an adjustment period for phase alignment inserted in a part of the blanking period between the previous field and the next field, and the period in the normal period excluding the adjustment period is one horizontal period. fold is set to the,
The second scanner, when the width of the second start pulse exceeds one horizontal period, rising after the second scan pulse of the previous Atamadan is adjusted interval, before the second scan pulse in the final stage of the adjustment section as falls, set the width and the input timing of the second start pulse, than Te, despite the presence of a line-sequential scanning during the adjustment period, Ru always sequentially output enable der a second scan pulse having the same pulse width the driving method of Viewing device. The second clock signal, a driving method of a display device according to 請 Motomeko 6 adjustment interval that is set to the minimum of one horizontal period.

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