JP2005338591A - Pixel circuit and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pixel circuit and a display device, wherein a current of a desired value can be stably and accurately supplied to light emitting elements of respective pixels regardless of variation in the threshold of active elements in the pixels and a reference potential can be stably held regardless of provision of a offset cancel function realized by precharge potential lines and luminance of a display image is prevented from having a gradient to display images of high quality as a result. <P>SOLUTION: Power supply potential lines VCCL101 to VCCL10n in n columns for supplying a supply voltage Vcc and precharge potential lines VPCL101 to VPCL10n in n columns for supplying a reference voltage Vpc for performing offset cancel are wired in the same direction so as to be parallel to signal lines SGL101 to SGL10n. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a pixel circuit having an electro-optical element whose luminance is controlled by a signal line including an active matrix display device such as an organic EL (Electroluminescence) display device and an LCD (Liquid Crystal Display device), and the pixel circuit in a matrix form. The present invention relates to a wiring structure, an arrangement, and a circuit in an arranged image display device.

In an active matrix display device, an electro-optical element such as a liquid crystal cell or an organic EL element is used as a display element of a pixel.
Among them, the organic EL element has a structure in which a layer made of an organic material, that is, an organic layer is sandwiched between electrodes.
In this organic EL element, by applying a voltage to the element, electrons from the cathode and holes from the anode are injected into the organic layer. As a result, the electrons and holes are recombined to generate light. This organic EL element has the following features.

(1) Since a luminance of several hundreds to several 10000 cd / m ² can be obtained by driving at a low voltage of 10 V or less, power consumption can be reduced.
(2) Since it is a self-luminous element, it has a high image contrast and a high response speed, so that it has good visibility and is suitable for displaying moving images.
(3) It is an all solid state element having a simple structure, and the element can be made highly reliable and thin.

  An organic EL display device using an organic EL element having these features as a pixel display element (hereinafter referred to as an organic EL display) is considered promising as a next-generation flat panel display.

  By the way, as a driving method of the organic EL display, there are a simple matrix method and an active matrix method. Among these methods, the active matrix method has the following features.

(1) An active matrix system that can hold light emission of an organic EL element in each pixel for one frame period is suitable for high definition and high luminance of an organic EL display.
(2) Since a peripheral circuit using a thin film transistor can be formed over a substrate (panel), the interface with the outside of the panel can be simplified and the function of the panel can be enhanced.

In this active matrix type organic EL display, a polysilicon thin film transistor (TFT) having polysilicon as an active layer is generally used as a transistor as an active element.
This is because the polysilicon TFT has a high driving capability and can be designed to have a small pixel size, which is advantageous for high definition.

By the way, while the polysilicon TFT has the above-described features, it is widely known that the characteristic variation is large.
Therefore, in the case of using a polysilicon TFT, it is a big problem in an active matrix type organic EL display using a polysilicon TFT to suppress the characteristic variation and to compensate for the TFT characteristic variation in a circuit. This is for the following reason.

  That is, in a liquid crystal display using a liquid crystal cell as a pixel display element, the luminance data of each pixel is controlled by a voltage value, whereas in an organic EL display, the luminance data of each pixel is controlled by a current value. It is because the structure to control is taken.

Here, an outline of the active matrix organic EL display will be described.
FIG. 1 is a diagram illustrating an outline of a configuration of a general active matrix organic EL display, and FIG. 2 is a circuit diagram illustrating a configuration example of a pixel circuit of the active matrix organic EL display (for example, Patent Documents). 1 and 2).

  The active matrix organic EL display 1 includes m × n pixel circuits 10 arranged in a matrix, and signal lines for n columns driven by a data driver (DDRV) 2 with respect to the matrix arrangement of the pixel circuits 10. SGL1 to SGLn are wired for each pixel column, and m rows of scanning lines SCNL1 to SCNLm driven by the scan driver (SDRV) 3 are wired for each pixel row.

Further, as shown in FIG. 2, the pixel circuit 10 includes a p-channel TFT 11, an n-channel TFT 12, a capacitor C11, and a light emitting element 13 including an organic EL element (OLED).
The TFT 11 of each pixel circuit 10 has a source connected to the power supply potential line VCCL and a gate connected to the drain of the TFT 12. The organic EL light emitting element 13 has an anode connected to the drain of the TFT 11 and a cathode connected to a reference potential (for example, ground potential) GND.
The TFT 12 of each pixel circuit 10 is connected to the signal lines SGL1 to SGLn of the column corresponding to the source, and to the scanning lines SCNL1 to SCNLm of the row corresponding to the gate.
The capacitor C11 has one end connected to the power supply potential line VCCL and the other end connected to the drain of the TFT 12.

  Since organic EL elements often have rectifying properties, they are sometimes referred to as OLEDs (Organic Light Emitting Diodes). In FIG. 2 and other figures, diode symbols are used as light-emitting elements. However, it does not necessarily require rectification.

In the pixel circuit 10 having such a configuration, in a pixel to which luminance data is written, a pixel row including the pixel is selected by the scan driver 3 via the scanning line SCNL. Turn on.
At this time, the luminance data is supplied as a voltage from the data driver 2 through the signal line SGL, and is written into the capacitor C11 that holds the data voltage through the TFT 12.
The luminance data written in the capacitor C11 is held for one field period. The held data voltage is applied to the gate of the TFT 11.
Thereby, TFT11 drives the organic EL element 13 with an electric current according to holding | maintenance data. At this time, gradation expression of the organic EL light emitting element 13 is performed by modulating the gate-source voltage Vdata (<0) of the TFT 11 held by the capacitor C11.

  In general, the luminance Loled of the organic EL element is proportional to the current Ioled flowing through the element. Therefore, the following equation (1) is established between the luminance Loled of the organic EL light emitting element 13 and the current Ioled.

(Equation 1)
Loled∝Ioled = k (Vdata−Vth) ² (1)

In the formula (1), k = 1/2 · μ · Cox · W / L. Here, μ is the carrier mobility of the TFT 11, Cox is the gate capacitance per unit area of the TFT 11, W is the gate width of the TFT 11, and L is the gate length of the TFT 11.
Therefore, it can be seen that the variation in mobility μ and threshold voltage Vth (<0) of the TFT 11 directly affects the luminance variation of the organic EL light emitting element 13.

  In this case, for example, even when the same potential Vdata is written to different pixels, the threshold voltage Vth of the TFT 11 varies from pixel to pixel. As a result, the current Ioled flowing through the light emitting element (OLED) 13 varies greatly from pixel to pixel and is completely different from the desired value. As a result, the display cannot be expected to have high image quality.

  A number of pixel circuits have been proposed in order to improve this problem. A typical example is shown in FIG. 3 (see, for example, Patent Document 3 or Patent Document 4).

The pixel circuit 20 in FIG. 3 includes a p-channel TFT 21, n-channel TFTs 22 to 24, capacitors C21 and C22, and an organic EL light emitting element 25 that is a light emitting element. In FIG. 3, SGL indicates a signal line, SCNL indicates a scanning line, AZL indicates an auto-zero line, and DRVL indicates a drive line.
The operation of the pixel circuit 20 will be described below with reference to the timing chart shown in FIG.

  As shown in FIGS. 4A and 4B, the drive line DRVL and the auto-zero line AZL are set to high level, and the TFTs 22 and 23 are turned on. At this time, since the TFT 21 is connected to the light emitting element (OLED) 25 in a diode-connected state, a current flows through the TFT 21.

  Next, as shown in FIG. 4A, the drive line DRVL is set to low level, and the TFT 22 is turned off. At this time, the scanning line SCNL is at a high level, as shown in FIG. 4C, and the TFT 24 is in a conductive state, and the reference potential Vref is applied to the signal line SGL as shown in FIG. 4D. Since the current flowing through the TFT 21 is cut off, the gate potential Vg of the TFT 21 rises as shown in FIG. 4E. However, when the potential rises to VDD− | Vth | Potential stabilizes. Hereinafter, this operation may be referred to as “auto-zero operation”.

  As shown in FIGS. 4B and 4D, the auto zero line AZL is set to a low level to turn off the TFT 23, and the potential of the signal line SGL is set to a potential that is lower than Vref by ΔVdata. This change in the signal line potential lowers the gate potential of the TFT 21 by ΔVg through the capacitor C21, as shown in FIG.

  As shown in FIGS. 4A and 4C, when the TFT 24 is turned off by setting the scanning line SCNL to the low level and the TFT 22 is turned on by setting the drive line DRVL to the high level, the TFT 21 and the light emitting element (OLED) 25 are turned on. Current flows, and the light emitting element 25 starts to emit light.

  If the parasitic capacitance can be ignored, ΔVg and the gate potential Vg of the TFT 21 are as follows.

(Equation 2)
ΔVg = ΔVdata × C1 / (C1 + C2) (2)

(Equation 3)
Vg = V _CC − | Vth | −ΔVdata × C1 / (C1 + C2) (3)

  Here, C1 indicates the capacitance value of the capacitor C21, and C2 indicates the capacitance value of the capacitor C22.

  On the other hand, if the current flowing through the light emitting element (OLED) 25 during light emission is Ioled, the current value is controlled by the TFT 21 connected in series with the light emitting element 25. Assuming that the TFT 21 operates in the saturation region, the following relationship is obtained using the well-known MOS transistor equation and the above equation (3).

(Equation 4)
Ioled = μCoxW / L / 2 (V _CC −Vg− | Vth |) ²
= ΜCoxW / L / 2 (ΔVdata × C1 / (C1 + C2)) ²
(4)

  Here, μ represents carrier mobility, Cox represents gate capacitance per unit area, W represents gate width, and L represents gate length.

  According to the equation (4), Ioled is controlled by ΔVdata given from the outside regardless of the threshold value Vth of the TFT 21. In other words, if the pixel circuit 20 of FIG. 3 is used, it is possible to realize a display device that is relatively unaffected by the threshold value Vth that varies from pixel to pixel and that has a relatively high current uniformity and, consequently, luminance uniformity.

USP 5,684,365 JP-A-8-234683 USP 6,229,506 Fig. 1 of JP-T-2002-514320. 3

  As described above, when the pixel circuit 10 as shown in FIG. 2 is used, the uniformity of luminance between pixels is impaired due to variations in the threshold voltage Vth of the transistor, and a high-quality display device can be configured. Have difficulty.

  On the other hand, if the pixel circuit of FIG. 3 is used, a display device with relatively high luminance uniformity can be realized, but this has the following problems.

  The first problem is that the gate amplitude ΔVg of the driving transistor decreases according to the equation (2) with respect to the data amplitude ΔVdata driven from the outside. Conversely, in order to obtain the same ΔVg, it is necessary to give a large ΔVdata, which is undesirable from the viewpoint of power consumption and noise.

The second problem is that the above description of the operation relating to the pixel circuit 20 of FIG. 3 is ideal, and in practice, the influence of the variation in Vth of the TFT 21 that drives the light emitting element (OLED) 25 is not eliminated. .
This is because the auto zero line AZL and the gate node of the TFT 21 are coupled by the gate capacitance of the TFT 23, and the channel charge of the TFT 23 becomes the gate of the TFT 21 in the process in which the auto zero line AZL transitions to a high level and the TFT 23 becomes non-conductive. This is because it flows into the node. The reason for this will be described next.

That is, the gate potential of the TFT 21 should ideally be VDD− | Vth | after the completion of the auto-zero operation, but actually becomes a slightly higher potential due to the inflow of the charge, and the inflow amount of the charge is It varies depending on the value of Vth. This is because the gate potential of the TFT 21 immediately before the end of the auto zero operation is approximately VDD− | Vth |. Therefore, this potential is higher as | Vth | is smaller, for example.
On the other hand, when the auto zero line ends, the potential of the auto zero line AZL rises and the TFT 23 switches to non-conduction, so that the higher the source potential, that is, the gate potential of the TFT 21, the more delayed the timing at which the TFT 23 becomes non-conduction, Will flow into the gate of the TFT 21. As a result, the gate potential of the TFT 21 after completion of the auto-zero operation is influenced by | Vth |, and thus the above-described equations (3) and (4) are not strictly established and are affected by Vth which varies from pixel to pixel. become.

In view of this, it is conceivable to use a threshold voltage correction type (offset cancellation type) pixel circuit as a pixel circuit capable of compensating for the threshold voltage Vth, in which luminance variation is likely to be a problem.
In this pixel circuit, for example, in the circuit of FIG. 3, the connection point between the drain of the TFT 24 and the coupling capacitor C21 is precharged to a predetermined precharge potential, for example, in an auto-zero period.
In this case, the precharge potential line is wired in the same direction (left-right direction in FIG. 1) so as to be parallel to the scanning line.

  As described above, these threshold correction type pixel circuits generally include the coupling capacitor C21 connected to the gate of the TFT 21 as a driving transistor that determines the current flowing through the organic EL element. The following operations are performed during the cancel operation.

In relation to FIG. 3, (1) a constant current Iref flows in the TFT 21 as a driving transistor. This may be a reference current input from the outside or a zero current.
(2) One end of the coupling capacitor C21 is connected to the reference potential (precharge potential) Vpc.
(3) At both ends of the coupling capacitor C21, the same voltage as the gate-source potential when the current Iref flows through the drive transistor TFT21 is generated. This potential Vref is expressed by the following equation, with the gate side of the driving transistor TFT21 being in the plus direction.

(Equation 5)
Iref = β (Vref−Vth) ² (5)

  Here, β is a proportional coefficient of the driving transistor (the mobility of the driving transistor), and Vth is a threshold voltage of the driving transistor. That is, the gate-source potential Vref of the TFT 21 as the driving transistor is as follows. Note that Iref = 0 may be used.

(Equation 6)
Vref = Vth + (Iref / β) ^1/2 (6)

  (4) Thereafter, at the time of data writing, the data voltage Vdata is written from the signal line SGL to the other end side of the TFT 21 that is the driving transistor of the coupling capacitor C21. Therefore, the gate-source potential of the driving transistor at this time is expressed as Vgs as follows.

(Equation 7)
Vgs = Vdata + Vref−Vsource
= Vdata + Vth + (Iref / β) ^1/2 −Vsource (7)

  Therefore, the current Ids flowing through the driving transistor is as follows.

(Equation 8)
Ids = β (Vdata + (Iref / β) ^1/2 −Vsource) ² (8)

  That is, the current Ids flowing through the driving transistor does not depend on the threshold voltage Vth, that is, threshold voltage correction is performed.

Next, an example of offset cancellation timing will be shown. At this time, the offset cancel operation is generally performed in synchronization with the scanning line.
FIG. 3 shows timing when the K horizontal period (H = 3 in the figure) is set as the offset cancel period immediately before data writing. Further, it is assumed that the number of pixels of this display is M × N.

At this time, as described above, when a layout in which pre-jersey potential lines parallel to the scanning line direction are wired is used, the number of pixels in which one pre-jersey potential line in the scanning direction is simultaneously offset canceled is N pixels. In general, N is several hundreds to 1000 or more.
Therefore, as the resolution increases, it becomes difficult to keep the reference voltage Vpc at a stable potential. In addition, when the potential has a gradient on the left and right sides of the screen, there is a problem that the luminance of the display image can be gradient.

  The present invention has been made in view of such circumstances, and an object of the present invention is to stably and accurately supply a current of a desired value to a light emitting element of each pixel regardless of variations in threshold values of active elements inside the pixel. Even if it can be supplied and has an offset cancel function using a precharge potential line, the reference potential can be stably maintained, and it is possible to prevent a gradient in the brightness of the display image, and as a result, a high-quality image can be displayed. It is an object of the present invention to provide a possible pixel circuit and display device.

  In order to achieve the above object, a first aspect of the present invention is a pixel circuit that drives an electro-optical element whose luminance changes according to a flowing current, and includes a signal line to which at least a data signal corresponding to luminance information is supplied. Forming a current supply line between at least the first control line and the second control line, a predetermined precharge potential, the first node, the second node, and the first terminal and the second terminal; A drive transistor for controlling a current flowing through the current supply line according to a potential of a control terminal connected to the second node; and connected between the signal line and the first node; A first switch whose conduction is controlled by a control line; a coupling capacitor connected between the first node and a second node connected to the control terminal of the driving transistor; and one end connected to a precharge potential. A second switch having the other end connected to the first node or the second node and controlled to conduct by the second control line, and the precharge potential line is parallel to the signal line. Are wired in the same direction.

  According to a second aspect of the present invention, there is provided a pixel circuit for driving an electro-optical element whose luminance is changed by a flowing current, wherein at least a signal line to which a signal corresponding to luminance information is supplied, at least a first control line, , First and second reference potentials, a predetermined precharge potential, a field effect transistor, a node, and a first switch connected between the source of the field effect transistor and the first reference potential A second switch connected between the source of the field effect transistor and the node; a third switch connected between the gate of the field effect transistor and the precharge potential; and the signal line. And a node connected between the node and the node, and connected between the node and the gate of the field effect transistor. The electro-optic element is connected between the drain of the field-effect transistor and a second reference potential, and is wired in the same direction so that the precharge potential line is parallel to the signal line. ing.

  According to a third aspect of the present invention, there is provided a pixel circuit for driving an electro-optical element whose luminance is changed by a flowing current, wherein at least a signal line to which a signal corresponding to luminance information is supplied, at least a first control line, First and second reference potentials, a predetermined precharge potential, a field effect transistor, a node, a first switch connected between the source of the field effect transistor and the electro-optic element, A second switch connected between the source of the field effect transistor and the node; a third switch connected between the gate of the field effect transistor and the precharge potential; and the signal line; A fourth switch connected between the node and controlled to be conductive by the first control line; and connected between the node and the gate of the field effect transistor. The electro-optic element is connected between the first switch and the second reference potential, and is wired in the same direction so that the precharge potential line is parallel to the signal line. Has been.

  According to a fourth aspect of the present invention, there is provided a pixel circuit for driving an electro-optical element whose luminance is changed by a flowing current, at least a signal line to which a signal corresponding to luminance information is supplied, at least a first control line, First and second reference potentials, a predetermined precharge potential, a field effect transistor, a node, a first switch connected between a drain of the field effect transistor and an electro-optic element, and A second switch connected between the drain and gate of the field effect transistor; a third switch connected between the node and the precharge potential; and between the signal line and the node. A fourth switch connected and controlled in conduction by the first control line, and a coupling capacitor connected between the node and the gate of the field effect transistor; The source of the field effect transistor is connected to the first reference potential, the electro-optic element is connected between the first switch and the second reference potential, and the precharge potential line is parallel to the signal line. Are wired in the same direction.

  According to a fifth aspect of the present invention, there are provided a plurality of pixel circuits arranged in a matrix, a signal line wired for each column to the matrix arrangement of the pixel circuits, and supplied with at least a data signal corresponding to luminance information , At least a first control line and a second control line wired for each row with respect to the matrix arrangement of the pixel circuits, and a predetermined line wired in the same direction as the signal lines with respect to the matrix arrangement of the pixel circuits. Each of the pixel circuits includes a first node, a second node, and a current supply line between the first terminal and the second terminal, and the second node Connected between the drive transistor for controlling the current flowing through the current supply line in accordance with the potential of the control terminal connected to the signal line, the signal line and the first node, and the conduction control by the first control line. First to be done A switch, a coupling capacitor connected between the first node and a second node connected to the control terminal of the driving transistor, one end connected to the corresponding precharge potential line, and the other end connected to the first node. And a second switch connected to the second node and connected to the second node, the conduction of which is controlled by the second control line.

  According to a sixth aspect of the present invention, there are provided a plurality of pixel circuits arranged in a matrix, a signal line wired for each column to the matrix arrangement of the pixel circuits, and supplied with at least a data signal corresponding to luminance information At least a first control line wired for each row with respect to the matrix arrangement of the pixel circuits, and a predetermined precharge potential line wired in the same direction as the signal lines with respect to the matrix arrangement of the pixel circuits. , And each pixel circuit includes a field effect transistor, a node, a source of the field effect transistor, and a first reference potential connected between the first reference potential and the first reference potential. And a second switch connected between the source of the field effect transistor and the node, and a gate of the field effect transistor and the precharge potential. A third switch connected between the signal line and the node and controlled to be conductive by the first control line, and between the node and the gate of the field effect transistor. A coupling capacitor connected thereto, wherein the electro-optic element is connected between the drain of the field-effect transistor and a second reference potential.

  According to a seventh aspect of the present invention, there are provided a plurality of pixel circuits arranged in a matrix, a signal line wired for each column to the matrix arrangement of the pixel circuits, and supplied with at least a data signal corresponding to luminance information At least a first control line wired for each row with respect to the matrix arrangement of the pixel circuits, and a predetermined precharge potential line wired in the same direction as the signal lines with respect to the matrix arrangement of the pixel circuits. , Each pixel circuit includes: a field effect transistor; a node; a source of the field effect transistor; and a first optical potential element connected between the electro-optic element. A switch; a second switch connected between the source of the field effect transistor and the node; and a connection between the gate of the field effect transistor and the precharge potential. A third switch connected between the signal line and the node and controlled to be conducted by the first control line, and between the node and the gate of the field effect transistor. And the electro-optic element is connected between the first switch and a second reference potential.

  According to an eighth aspect of the present invention, there are provided a plurality of pixel circuits arranged in a matrix, a signal line wired for each column to the matrix arrangement of the pixel circuits, and supplied with at least a data signal corresponding to luminance information At least a first control line wired for each row with respect to the matrix arrangement of the pixel circuits, and a predetermined precharge potential line wired in the same direction as the signal lines with respect to the matrix arrangement of the pixel circuits. A first switch connected between a field effect transistor, a node, a drain of the field effect transistor, and an electro-optical element. A second switch connected between the drain and gate of the field effect transistor, a third switch connected between the node and the precharge potential, A fourth switch connected between the signal line and the node and controlled in conduction by the first control line; and a coupling capacitor connected between the node and the gate of the field effect transistor. And the source of the field effect transistor is connected to the first reference potential, and the electro-optic element is connected between the first switch and the second reference potential.

According to the present invention, the pre-jersey potential line is wired in the same direction so as to be parallel to the signal line.
In this case, the number of pixels that are connected to one of the pre-jersey potential lines wired in the same direction as the signal line and simultaneously cancel the offset is, for example, K pixels. Usually, K is an offset cancel period, which is a time required for sufficient offset, but usually 1 to several tens or less, which is smaller than the number of pixels to be offset canceled at the same time. Also, K does not change even if the panel resolution increases. Therefore, it becomes easy to keep the precharge potential at a stable potential.
It is also possible to share the precharge line of the L pixel adjacent in the direction parallel to the scanning line. In this case, the number of pixels that are connected to one of the pre-jersey lines parallel to the signal line and simultaneously cancel the offset is K × L pixels. At this time, L may be selected as an appropriate numerical value within a range where the precharge line can be maintained at a stable potential.

Further, for example, the first switch, the second switch, and the third switch are turned on by a predetermined control line.
At this time, the control terminal of the driving transistor, for example, the gate is set to the precharge potential Vpc by the third switch, and the input side potential (node potential) of the coupling capacitor is the first and second switches in the conductive state. It rises to 1 reference potential (power supply potential V _CC ) or its vicinity.
Then, the first switch is turned off by a predetermined control line. As a result, the current flowing through the drive transistor is cut off, so that the potential of the second terminal (for example, drain) of the drive transistor falls, but when the potential falls to Vpc + | Vth |, the drive transistor becomes non-conductive. The potential becomes stable.
At this time, the input side potential (node potential) of the capacitor is also Vpc + | Vth | because the second switch is in a conductive state. Here, | Vth | is the absolute value of the threshold value of the driving transistor.
Next, the second and third switches are turned off by a predetermined control line. Alternatively, after the second switch is turned off, the third switch is turned off by a predetermined control line. The potential of the input node of the capacitor is Vpc + | Vth |, and the gate potential of the driving transistor is Vpc. That is, the potential difference between the capacitor terminals is | Vth |.
Next, the fourth switch is turned on, and the potential Vdata corresponding to the luminance data is supplied from the signal line to the input side node of the capacitor.
Since the potential difference between the capacitor terminals is maintained as | Vth |, the gate potential of the driving transistor is Vdata− | Vth |.
Next, when the fourth switch is turned off and the first switch is turned on by a predetermined control line, a current flows through the driving transistor and the electro-optical element, and light emission is started.
As described above, the pixel circuit according to the present invention can supply a current to the electro-optical element regardless of the threshold value of the driving transistor that varies from pixel to pixel, thereby realizing a display device that displays a high-quality image. can do. In particular, when compared with the prior art, the influence of noise from the control line to the drive transistor is small, and therefore, more accurate threshold variation correction can be performed.

According to the present invention, a current of a desired value can be supplied to a light emitting element of each pixel stably and accurately regardless of variations in threshold values of active elements inside the pixel, and an offset cancel function using a precharge potential line Even if it has, it can hold | maintain a reference potential stably, can prevent that the brightness | luminance of a display image makes a gradient, As a result, a high quality image can be displayed.
That is, crosstalk between pixels can be prevented with a relatively simple wiring configuration in which one fixed potential line is added on a plane without providing a three-dimensional electromagnetic shield.
Various variations can be applied to the fixed potential line.
Moreover, there is an advantage that luminance unevenness does not occur at the top and bottom of the screen.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 6 is a circuit diagram showing a first embodiment of an active matrix organic EL display (display device) according to the present invention.
FIG. 7 is a diagram showing a wiring arrangement related to the power supply line of the active matrix organic EL display according to the first embodiment.

As shown in FIG. 6, the organic EL display 100 includes a pixel array unit 102 in which pixel circuits 101 are arranged in an m × n matrix, a data driver (DDRV) 103, and a scan driver (SDRV) 104. Yes.
The signal lines SGL1 to SGLn for n columns driven by the data driver (DDRV) 103 with respect to the matrix arrangement of the pixel circuit 101 are selectively driven by the scan driver (SDRV) 12 for each pixel column. Scan lines SCNL101 to SCNL10m, drive lines DRL101 to DRV10m, and auto-zero lines AZL101 to AZL10m are wired for each pixel row.

  Further, in the present embodiment, n columns of power supply potential lines VCCL101 to VCCL10n for supplying the power supply voltage Vcc and n columns of precharge potential lines VPCL101 for supplying the reference voltage Vpc for performing offset cancellation. The VPCL 10n is wired for each pixel column in the same direction so as to be parallel to the signal lines SGL101 to SGL10n.

  Further, in the present embodiment, the power supply potential line VCCL is a pixel that is a display region in order to prevent luminance unevenness due to a potential difference in the length direction generated above and below the power supply potential line VCCL as shown in FIG. The upper and lower portions of the array unit 102 in the drawing are made common, that is, both ends of the plurality of power supply potential lines VCCL101 to VCCL10n are connected in common to achieve the same potential.

In the pixel array unit 102, the pixel circuits 101 are arranged in a matrix of m × n. However, in FIG. 6, a matrix of 2 (= m) × 2 (= n) is shown for simplification of the drawing. The example arranged in the shape is shown.
In FIG. 6, each of the 2 × 2 pixel circuits is also expressed as Pixel (M, N), Pixel (M, N + 1), Pixel (M + 1, N), and Pixel (M + 1, N + 1).

  Next, a specific configuration of each pixel circuit 101 will be described.

  As shown in FIG. 6, the pixel circuit 101 includes one p-channel TFT 111, four n-channel TFTs 112 to 115, an organic EL light emitting element 116, capacitors C111 and C112, and nodes ND111 to ND113.

In the pixel circuit Pixel (M, N) arranged in the first row and the first column in FIG. 6, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL101 wired in the first row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M + 1, N) arranged in the second row and first column in FIG. 6, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL102 wired in the second row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M, N + 1) arranged in the first row and the second column in FIG. 6, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL102 wired in the second column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL101 wired in the first row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N + 1) arranged in the second row and the second column in FIG. 6, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL102 wired in the second column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL102 wired in the second row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

  Next, the operation of the pixel circuit 101 will be described using Pixel (M, N) in FIG. 6 as an example.

The drive line DRL101 and the auto-zero line AZL101 are set to high level, and the TFT 112, TFT 113, and TFT 115 are turned on. At this time, since the TFT 111 is connected to the light emitting element (OLED) 116 in a diode-connected state, a constant current Iref flows through the TFT 111.
Further, the fixed reference voltage Vpc supplied to the precharge potential line VPCL101 is supplied to the node ND112 on one end (second electrode side) of the coupling capacitor C111 through the TFT 115.
Then, at both ends of the coupling capacitor C111, the same voltage as the gate-source potential when the current Iref flows in the TFT 111 as the driving transistor is generated. This potential Vref is expressed by the following equation, with the gate side of the TFT 111 as the driving transistor being a plus direction.

(Equation 9)
Iref = β (Vref−Vth) ² (9)

  Here, β is a proportional coefficient of the driving transistor (the mobility of the driving transistor), and Vth is a threshold voltage of the driving transistor. That is, the gate-source potential Vref of the TFT 111 as the driving transistor is as follows. In the present embodiment, Iref = 0.

(Equation 10)
Vref = Vth + (Iref / β) ^1/2 (10)

  Next, the drive line DRL101 is set to a low level, and the TFT 112 is turned off. At this time, the scanning line SCNL101 is at a high level and the TFT 114 is turned on, and the reference potential Vref is applied to the signal line SGL101. Since the current flowing through the TFT 111 is cut off, the gate potential Vg of the TFT 111 rises, but when the potential rises to Vcc− | Vth |, the TFT 111 becomes non-conductive and the potential is stabilized. That is, an auto zero operation is performed.

  The auto zero line AZL101 is set to a low level to turn off the TFT 113, and the data voltage Vdata is written to the other end side (node ND111 side) of the coupling capacitor C111 through the signal line SGL101. Therefore, the gate-source potential of the driving transistor at this time is expressed as Vgs as follows.

(Equation 11)
Vgs = Vdata + Vref−Vsource
= Vdata + Vth + (Iref / β) ^1/2 −Vsource (11)

  Therefore, the current Ids flowing through the driving transistor is as follows.

(Equation 12)
Ids = β (Vdata + (Iref / β) ^1/2 −Vsource) ² (12)

  That is, the current Ids flowing through the driving transistor does not depend on the threshold voltage Vth, that is, threshold voltage correction is performed.

  Note that after the data voltage is taken in order for the light emitting element 116 to start light emission, the scanning line SCNL101 is set to the low level, the TFT 114 is turned off, and the drive line DRL101 is set to the high level, and the TFT 112 is turned on. Is called.

Here, the timing of offset cancellation will be considered.
In the present embodiment, a pre-jersey potential line VPCL is wired in parallel with the signal line SGL. At this time, the number of pixels that are connected to one of the pre-jersey potential lines VPCL parallel to the signal line SGL and are simultaneously offset canceled is K pixels.
Usually, K is an offset cancel period, which is a time required for sufficient offset, but usually 1 to several tens or less, which is smaller than the number of pixels subjected to offset cancel simultaneously in the conventional example. Also, K does not change even if the panel resolution increases. Therefore, it becomes easy to keep the precharge potential at a stable potential.

As described above, according to the first embodiment, n columns of power supply potential lines VCCL101 to VCCL10n for supplying the power supply voltage Vcc and n columns for supplying the reference voltage Vpc for performing offset cancellation. The precharge potential lines VPCL101 to VPCL10n are wired for each pixel column in the same direction so that the signal lines SGL101 to SGL10n are parallel to each other. A current of a desired value can be stably and accurately supplied to the light-emitting element of each pixel, and even if it has an offset cancel function by a precharge potential line, it can stably hold a reference potential and can have a gradient in the brightness of a display image. Can be prevented.
As a result, a high-quality image can be displayed.

  In the present embodiment, the power supply potential line VCCL is common to the upper and lower sides of the pixel array unit 102 in the drawing, that is, the power supply potential lines VCCL101 to VCCL10n are connected in common. We are trying to increase the potential. Accordingly, luminance unevenness due to a potential difference in the length direction occurring at the top and bottom of the power supply potential line VCCL in the drawing can be prevented.

  Note that the pixel circuit 101 in FIG. 6 is an example, and the present invention is not limited to this. For example, as described above, since the TFTs 112 to 115 are merely switches, it is obvious that all or a part of them can be constituted by p-channel TFTs or other switching elements.

Second Embodiment
FIG. 8 is a circuit diagram showing a second embodiment of an active matrix organic EL display (display device) according to the present invention.
FIG. 9 is a diagram showing a wiring arrangement related to the power supply line of the active matrix organic EL display according to the second embodiment.

  The second embodiment is different from the first embodiment described above in that two adjacent pixel circuits of a pixel circuit arranged in an odd column of the same row and a pixel circuit arranged in an even column are A so-called mirror-type circuit arrangement that is symmetrical with respect to the axis in the column direction, and the power supply potential line VCCL is shared by the adjacent pixel circuits to form the power supply potential line VCCL thicker according to the first embodiment. The even-numbered pixel circuit signal lines and the odd-numbered pixel circuit signal lines that do not take the mirror-type circuit arrangement are wired adjacently, and the even-numbered pixel circuits and the odd-numbered row that do not take this mirror-type circuit arrangement The precharge potential line VPCL is shared between the pixel circuits, and is arranged between the even-numbered pixel circuit signal lines and the odd-numbered pixel circuit signal lines that do not have a mirror-type circuit arrangement. Interference (crosstalk) phenomenon Lies in the fact that so as to suppress.

  Therefore, the power supply potential lines VCCL are wired one by one in the odd columns, the precharge potential lines VPCL are arranged for each column, and the precharge potential lines VPCLO wired in the odd columns are the drains of the TFTs 115 of the pixel circuits in the odd columns. Are connected to each other, and the precharge potential line VPCLE wired in the even-numbered columns is connected to the drains of the TFTs 115 of the even-numbered pixel circuits and the TFTs 115 of the odd-numbered pixel circuits that do not take a mirror type circuit arrangement with the even-numbered pixel circuits. The drains are connected in common.

In this pixel array portion 102A, the pixel circuits 101A are arranged in an m × n matrix. However, in FIG. 8, a 2 (= m) × 3 (= n) matrix is shown in order to simplify the drawing. The example arranged in the shape is shown.
In FIG. 6, each of the 2 × 3 pixel circuits is represented by Pixel (M, N), Pixel (M, N + 1), Pixel (M, N + 2), Pixel (M + 1, N), and Pixel (M + 1, N + 1). , Pixel (M + 1, N + 2).

  The configuration and operation of each pixel circuit 101A in FIG. 8 are the same as those in the circuit in FIG. 6, but there are differences in the connection relationship, so only a specific connection relationship will be described here.

In the pixel circuit Pixel (M, N) arranged in the first row and the first column in FIG. 8, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL101 wired in the first row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M, N + 1) arranged in the first row and the second column in FIG. 8, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL101 wired in the first row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M, N + 2) arranged in the first row and the third column in FIG. 8, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL103 wired in the third column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL101 wired in the first row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL103 wired in the third column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL103 wired in the third column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N) arranged in the second row and the first column of FIG. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL102 wired in the second row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M + 1, N + 1) arranged in the second row and second column in FIG. 8, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL102 wired in the second row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND112 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N + 2) arranged in the second row and the third column in FIG. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL102 wired in the second row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND112 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL103 wired in the third column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL103 wired in the third column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In such a configuration, for example, as shown in FIG. 10, the select switch 1032 of the data driver is turned on and data is transferred to the signal line SGL102, then the select switch 1032 is turned off and the select switch 1033 is turned on. When data is transferred to the signal line SGL103, since the precharge potential line VPCL102 having a fixed potential exists between the signal line SGL102 and the signal line SGL103, mutual electromagnetic coupling is shielded and crosstalk occurs. Absent.
Therefore, accurate luminance data can be written.

  According to the second embodiment, in addition to the effects of the first embodiment described above, crosstalk between pixels can be prevented with a relatively simple wiring configuration without applying a three-dimensional electromagnetic shield, and luminance can be reduced. There is an advantage that data can be written accurately.

<Third Embodiment>
FIG. 11 is a circuit diagram showing a third embodiment of an active matrix organic EL display (display device) according to the present invention.

The difference between the third embodiment and the first embodiment described above is the configuration of the pixel circuit 101B.
Hereinafter, the configuration and operation of the pixel circuit 101B according to the third embodiment will be described in order.

As shown in FIG. 11, each pixel circuit 101B according to the third embodiment includes a light emitting element 126 including a p-channel TFT 121, n-channel TFTs 122 to 125, capacitors C121 and C122, and an organic EL element OLED (electro-optical element). And nodes ND121 to ND123.
Of these components, the TFT 121 constitutes a field effect transistor according to the present invention, the TFT 122 constitutes a first switch, the TFT 123 constitutes a second switch, the TFT 125 constitutes a third switch, and the TFT 124 Constitutes a fourth switch, and the capacitor C121 constitutes a capacitor according to the present invention.
The scanning line SCNL corresponds to the first control line according to the present invention. Note that the auto-zero line AZL is commonly used as a control line for turning on / off the TFT 135, but it is also possible to perform on / off control using another control line.
Further, the supply line (power supply potential) of the power supply voltage V _CC corresponds to the first reference potential, and the potential of the cathode line CSL (for example, the ground potential GND) corresponds to the second reference potential.

In the present pixel array portion 102B, the pixel circuits 101B are arranged in an m × n matrix. However, in FIG. 11 as well, a 2 (= m) × 2 (= n) matrix is used to simplify the drawing. The example arranged in the shape is shown.
In FIG. 11, each of the 2 × 2 pixel circuits is also expressed as Pixel (M, N), Pixel (M, N + 1), Pixel (M + 1, N), and Pixel (M + 1, N + 1).

  Next, a specific configuration of each pixel circuit 101B will be described.

In the pixel circuit Pixel (M, N) arranged in the first row and the first column in FIG. 11, the source of the TFT 121 as a drive transistor is connected to a node ND123 (a connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL101 wired in the first column, and the gate is connected to the drive line DRL101 wired in the first row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M + 1, N) arranged in the second row and the first column in FIG. 11, the source of the TFT 121 as a drive transistor is connected to a node ND123 (a connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL101 wired in the first column, and the gate is connected to the drive line DRL102 wired in the second row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M, N + 1) arranged in the first row and the second column in FIG. 11, the source of the TFT 121 as a drive transistor is connected to a node ND123 (a connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL102 wired in the second column, and the gate is connected to the drive line DRL101 wired in the first row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N + 1) arranged in the second row and the second column in FIG. 11, the source of the TFT 121 as a drive transistor is connected to the node ND123 (the connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL102 wired in the second column, and the gate is connected to the drive line DRL102 wired in the second row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL102 wired in the second column.

  Next, the operation of the pixel circuit 101B will be described with reference to the timing chart shown in FIG. 12, taking Pixel (M, N) in FIG. 11 as an example.

Step ST11 :
First, as shown in FIGS. 12A and 12B, the drive line DRL101 and the auto-zero line AZL101 are set to high level, and the TFT 122, TFT 123, and TFT 125 are turned on.
At this time, the gate of the TFT 121 becomes a precharge potential Vpc by the TFT 125 as shown in FIG. 12F, and the input side potential VC121 of the capacitor C121 is shown in FIG. It rises to the power supply potential V _CC or near to.

Step ST12:
As shown in FIG. 12A, the drive line DRL101 is set to a low level and the TFT 122 is turned off. Since the current flowing through the TFT 121 is cut off, the drain potential of the TFT 121 decreases. However, when the potential decreases to Vpc + | Vth |, the TFT 121 becomes non-conductive and the potential is stabilized.
At this time, the input side potential VC121 of the capacitor C121 is also Vpc + | Vth | as shown in FIG. 12E because the TFT 123 is in a conductive state. Here, | Vth | is the absolute value of the threshold value of the TFT 121.

Step ST13 :
As shown in FIG. 12B, the auto-zero line AZL101 is set to a low level to turn off the TFT 123 and the TFT 125. The potential VC121 of the input side node of the capacitor C121 is Vpc + | Vth | as shown in FIG. 12E, and the gate potential Vg121 of the TFT 121 is Vpc as shown in FIG. That is, the potential difference between the terminals of the capacitor C121 is | Vth |.

Step ST14 :
As shown in FIGS. 12C and 12D, the scanning line SCNL101 is set to the high level to make the TFT 124 conductive, and the potential Vdata corresponding to the luminance data is supplied from the signal line SGL101 to the input side node ND121 of the capacitor C121.
Since the potential difference between the terminals of the capacitor C121 is held as | Vth |, the gate potential Vg121 of the TFT 121 becomes Vdata− | Vth | as shown in FIG.

Step ST15 :
As shown in FIGS. 12A and 12C, when the scanning line SCNL101 is set to a low level to make the TFT 124 non-conductive, and the drive line DRL101 is set to a high level to make the TFT 122 conductive, the TFT 121 and the light emitting element (OLED) 126 are connected. A current flows and the OLED starts to emit light.

  In the operations of steps ST11 and ST12, it is necessary to set the value of Vpc so that Vpc + | Vth | <VDD. However, as long as this value is satisfied, the value of Vpc is arbitrary.

  When the current Ioled flowing through the light emitting element (OLED) 126 is calculated after the above operation is performed, if the TFT 121 is operating in the saturation region, the following is obtained.

(Equation 13)
Ioled = μCoxW / L / 2 (Vgs−Vth) ²
= ΜCoxW / L / 2 (V _CC −Vg− | Vth |) ²
= ΜCoxW / L / 2 (V _CC −Vdata + | Vth | − | Vth |) ²
= ΜCoxW / L / 2 (V _CC −Vdata) ²
... (13)

Here, μ represents carrier mobility, Cox represents gate capacitance per unit area, W represents gate width, and L represents gate length.
According to the equation (13), the current Ioled does not depend on the threshold value Vth of the TFT 121 (regardless of Vth) and is controlled by Vdata supplied from the outside.
In other words, when the pixel circuit 101B in FIG. 11 is used, it is possible to realize a display device that is relatively free from the influence of Vth, which varies from pixel to pixel, and that has relatively high current uniformity and thus luminance uniformity.

  Even when the TFT 121 is operating in the linear region, the current Ioled flowing through the light emitting element (OLED) 126 is as follows and is not dependent on Vth.

(Equation 14)
Ioled = μCoxW / L {(Vgs -Vth) Vds-Vds 2/2}
= ΜCoxW / L {(V _CC −Vg− | Vth |) (V _CC −Vd) − (V _CC
-Vd) ^2/2}
= ΜCoxW / L {(V _CC −Vdata + | Vth | − | Vth |) (V _CC −
_{Vd) - (V CC -Vd)} 2/2}
_{= ΜCoxW / L {(V CC} -Vdata) (V CC -Vd) - (V CC -Vd) 2/2}
... (14)

  Here, Vd represents the drain potential of the TFT 121.

As described above, the pixel circuit 101B of the third embodiment is superior to the conventional example of FIG. 1 in that the influence of variations in the threshold value Vth can be canceled.
3 is superior to the conventional example of FIG. 3 in the following points.
First, the conventional example of FIG. 3 has a problem that the gate amplitude ΔVg of the driving transistor decreases according to the equation (2) with respect to the data amplitude ΔVdata driven from the outside. Accordingly, the pixel circuit can be driven with a smaller signal line amplitude.
As a result, it is possible to drive with lower power consumption and lower noise.
Second, regarding the capacitive coupling between the auto-zero line and the TFT gate, which is a problem in the conventional example of FIG. 3, the TFT 123 is not directly connected to the gate of the TFT 121 in the pixel circuit 101B of FIG. Less is.
On the other hand, the TFT 125 is connected to the gate of the TFT 121, but the source of the TFT 125 is connected to the constant potential Vpc. Therefore, even if the gate potential changes at the end of the auto-zero operation, the gate potential of the TFT 121 is approximately Vpc. Kept at potential.
Thus, in the pixel circuit 101B of FIG. 11, the influence of the coupling between the auto zero line AZL31 and the gate of the TFT 121 is small, and as a result, the Vth variation is corrected more accurately than the pixel circuit of FIG.
That is, according to the present embodiment, a current having a desired value is accurately supplied to the light emitting element of the pixel circuit regardless of variations in the threshold value of the transistor, and as a result, high luminance uniformity and high quality are achieved. An organic EL pixel circuit capable of displaying an image can be realized. As a result, the threshold value can be corrected with higher accuracy than the conventional similar circuit.

Also consider the timing of offset cancellation.
Also in the third embodiment, the pre-jersey potential line VPCL is wired in parallel with the signal line SGL. At this time, the number of pixels that are connected to one of the pre-jersey potential lines VPCL parallel to the signal line SGL and are simultaneously offset canceled is K pixels.
Usually, K is an offset cancel period, which is a time required for sufficient offset, but usually 1 to several tens or less, which is smaller than the number of pixels subjected to offset cancel simultaneously in the conventional example. Also, K does not change even if the panel resolution increases. Therefore, it becomes easy to keep the precharge potential at a stable potential.

  According to the third embodiment, an effect similar to that of the first embodiment described above, that is, a desired light emitting element of each pixel can be stably and accurately regardless of variations in threshold values of active elements inside the pixel. Can be supplied, and even if the offset cancel function using the precharge potential line is provided, the reference potential can be stably maintained, and a gradient in the brightness of the display image can be prevented. As a result, there is an advantage that a high-quality image can be displayed.

  Also in the third embodiment, the power supply potential line VCCL is common to the upper and lower sides of the pixel array unit 102 as a display region, that is, both ends of the plurality of power supply potential lines VCCL101 to VCCL10n are connected in common. Therefore, the same potential is achieved. Accordingly, luminance unevenness due to a potential difference in the length direction occurring at the top and bottom of the power supply potential line VCCL in the drawing can be prevented.

  Note that the pixel circuit 101B in FIG. 11 is an example, and the present invention is not limited to this. For example, as described above, since the TFTs 122 to 125 are merely switches, it is obvious that all or a part of them can be constituted by p-channel TFTs or other switching elements.

<Fourth embodiment>
FIG. 13 is a circuit diagram showing a fourth embodiment of an active matrix organic EL display (display device) according to the present invention.

  The fourth embodiment is different from the above-described third embodiment in that two adjacent pixel circuits of a pixel circuit arranged in an odd column of the same row and a pixel circuit arranged in an even column are A so-called mirror-type circuit arrangement that is symmetrical with respect to the axis in the column direction, and the power supply potential line VCCL is shared by the adjacent pixel circuits to form the power supply potential line VCCL thicker according to the first embodiment. The even-numbered pixel circuit signal lines and the odd-numbered pixel circuit signal lines that do not take the mirror-type circuit arrangement are wired adjacently, and the even-numbered pixel circuits and the odd-numbered row that do not take this mirror-type circuit arrangement The precharge potential line VPCL is shared between the pixel circuits, and is arranged between the even-numbered pixel circuit signal lines and the odd-numbered pixel circuit signal lines that do not have a mirror-type circuit arrangement. Interference (crosstalk) phenomenon Lies in the fact that so as to suppress.

  Accordingly, the power supply potential lines VCCL are wired one by one in the odd columns, the precharge potential lines VPCL are arranged for each column, and the precharge potential lines VPCLO wired in the odd columns are the drains of the TFTs 125 of the pixel circuits in the odd columns. Are connected, and the precharge potential line VPCLE wired in the even-numbered column is connected to the drain of the TFT 125 of the even-numbered pixel circuit and the TFT 125 of the odd-numbered pixel circuit that does not take a mirror type circuit arrangement with the even-numbered pixel circuit. The drains are connected in common.

In the pixel array unit 102C, the pixel circuits 101C are arranged in an m × n matrix. However, in FIG. 13, a 2 (= m) × 3 (= n) matrix is shown for simplification of the drawing. The example arranged in the shape is shown.
In FIG. 13, each of the 2 × 3 pixel circuits is represented by Pixel (M, N), Pixel (M, N + 1), Pixel (M, N + 2), Pixel (M + 1, N), and Pixel (M + 1, N + 1). , Pixel (M + 1, N + 2).

  The configuration and operation of each pixel circuit 101C in FIG. 13 are the same as those in the circuit in FIG. 11, but there are differences in the connection relationship, so only a specific connection relationship will be described here.

In the pixel circuit Pixel (M, N) arranged in the first row and the first column in FIG. 13, the source of the TFT 121 as a drive transistor is connected to the node ND123 (the connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL101 wired in the first column, and the gate is connected to the drive line DRL101 wired in the first row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M, N + 1) arranged in the first row and the second column in FIG. 13, the source of the TFT 121 as a drive transistor is connected to the node ND123 (the connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL101 wired in the first column, and the gate is connected to the drive line DRL101 wired in the first row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M, N + 2) arranged in the first row and the third column in FIG. 13, the source of the TFT 121 as a drive transistor is connected to the node ND123 (the connection point between the source of the TFT 122 and the drain of the TFT TFT 123), and the drain is The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL103 wired in the third column, and the gate is connected to the drive line DRL101 wired in the first row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL103 wired in the third column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL103 wired in the third column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N) arranged in the second row and the first column in FIG. 13, the source of the TFT 121 as a drive transistor is connected to a node ND123 (a connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL101 wired in the first column, and the gate is connected to the drive line DRL102 wired in the second row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M + 1, N + 1) arranged in the second row and the second column in FIG. 13, the source of the TFT 121 as a driving transistor is connected to the node ND123 (the connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL101 wired in the first column, and the gate is connected to the drive line DRL102 wired in the second row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N + 2) arranged in the second row and the third column in FIG. 13, the source of the TFT 121 as a driving transistor is connected to the node ND123 (the connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL103 wired in the third column, and the gate is connected to the drive line DRL102 wired in the second row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL103 wired in the third column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL103 wired in the third column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In such a configuration, for example, as shown in FIG. 14, the select switch 1032 of the data driver is turned on and data is transferred to the signal line SGL102, then the select switch 1032 is turned off and the select switch 1033 is turned on. When data is transferred to the signal line SGL103, since the fixed potential precharge potential line VPCL102 exists between the signal line SGL102 and the signal line SGL103, mutual electromagnetic coupling is shielded and crosstalk occurs. Absent.
Therefore, accurate luminance data can be written.

  According to the fourth embodiment, in addition to the effects of the first and third embodiments described above, crosstalk between pixels can be prevented with a relatively simple wiring configuration without providing a three-dimensional electromagnetic shield. There is an advantage that luminance data can be written accurately.

<Fifth Embodiment>
FIG. 15 is a circuit diagram showing a fifth embodiment of an active matrix organic EL display (display device) according to the present invention.

The fifth embodiment is different from the first embodiment described above in the configuration of the pixel circuit 101D.
Hereinafter, the configuration and operation of the pixel circuit 101D according to the fifth embodiment will be described in order.

As shown in FIG. 15, each pixel circuit 101D according to the fifth embodiment includes n-channel TFTs 131 to 135, capacitors C131 and C132, a light emitting element 136 composed of an organic EL element OLED (electro-optical element), and a node ND131. ~ ND133.
Among these components, the TFT 131 constitutes a field effect transistor according to the present invention, the TFT 132 constitutes a first switch, the TFT 133 constitutes a second switch, the TFT 135 constitutes a third switch, and the TFT 134 Constitutes a fourth switch, and the capacitor C131 constitutes a capacitor according to the present invention.
The scanning line SCNL corresponds to the first control line according to the present invention. Note that the auto-zero line AZL is commonly used as a control line for turning on / off the TFT 135, but it is also possible to perform on / off control using another control line.
Further, the supply line (power supply potential) of the power supply voltage V _CC corresponds to the first reference potential, and the potential of the cathode line CSL (for example, the ground potential GND) corresponds to the second reference potential.

In this pixel array unit 102D, the pixel circuits 101D are arranged in an m × n matrix. However, in FIG. 15 as well, a 2 (= m) × 2 (= n) matrix is used to simplify the drawing. The example arranged in the shape is shown.
In FIG. 15, each of the 2 × 2 pixel circuits is also expressed as Pixel (M, N), Pixel (M, N + 1), Pixel (M + 1, N), and Pixel (M + 1, N + 1).

  Next, a specific configuration of each pixel circuit 101D will be described.

In the pixel circuit Pixel (M, N) arranged in the first row and first column in FIG. 15, the drain of the TFT 131 as the drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the source is connected to the node ND133. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (source of the TFT 131), the source is connected to the anode side of the organic EL light emitting element 136, the gate is connected to the drive line DRL101 wired in the first row, and the light emitting element 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M + 1, N) arranged in the second row and the first column in FIG. 15, the drain of the TFT 131 as a drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the source is connected to the node ND133. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (the source of the TFT 131), the source is connected to the anode side of the organic EL light emitting device 136, the gate is connected to the drive line DRL102 wired in the second row, and the light emitting device 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M, N + 1) arranged in the first row and the second column in FIG. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (source of the TFT 131), the source is connected to the anode side of the organic EL light emitting element 136, the gate is connected to the drive line DRL101 wired in the first row, and the light emitting element 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N + 1) arranged in the second row and the second column in FIG. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (the source of the TFT 131), the source is connected to the anode side of the organic EL light emitting device 136, the gate is connected to the drive line DRL102 wired in the second row, and the light emitting device 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

  The biggest difference between the pixel circuit 101D in FIG. 15 and the pixel circuit 101B in FIG. 11 is that the TFT 131 is an n-channel as a driving transistor for controlling the current flowing in the light emitting element (OLED) 46, and the source and the organic EL light emitting element ( OLED) and a TFT 132 as a switch.

  Next, the operation of the pixel circuit 101D will be described with reference to the timing chart shown in FIG. 16, taking Pixel (M, N) in FIG. 15 as an example.

Step ST21 :
As shown in FIGS. 16A and 16B, the drive line DRL101 and the auto-zero line AZL101 are set to the high level, and the TFTs 132, 133, and 135 are turned on. At this time, the gate potential Vg131 of the TFT 131 becomes the precharge potential Vpc as shown in FIG. When Vpc is set to a sufficiently high potential, the TFT 131 becomes conductive, and a current flows through the TFT 131 and the light emitting element (OLED) 136.

Step ST22 :
As shown in FIG. 16A, the drive line DRL101 is set to a low level and the TFT 132 is turned off. Since the current flowing through the TFT 131 is cut off, the source potential of the TFT 131 rises, but when the potential rises to (Vpc−Vth), the TFT 131 becomes non-conductive and the potential is stabilized.
At this time, the input side potential VC131 of the capacitor C131 is also (Vpc−Vth) as shown in FIG. 16E because the TFT 133 is in a conductive state. Here, Vth is a threshold value of the TFT 131.

Step ST23 :
As shown in FIG. 16B, the auto zero line AZL101 is set to a low level to turn off the TFT 133 and the TFT 135. The potential VC131 of the input side node ND131 of the capacitor C131 is (Vpc−Vth) as shown in FIG. 16E, and the gate potential Vg131 of the TFT 131 is Vpc as shown in FIG. That is, the potential difference between the terminals of the capacitor C131 is Vth.

Step ST24 :
As shown in FIGS. 16C and 16D, the scanning line SCNL101 is set to the high level to make the TFT 134 conductive, and the potential Vdata corresponding to the luminance data is supplied from the signal line SGL101 to the input side node ND131 of the capacitor C131. Since the potential difference between the terminals of the capacitor C131 is maintained at Vth, the gate potential Vg131 of the TFT 131 is (Vdata + Vth) as shown in FIG.

Step ST25 :
As shown in FIGS. 16A and 16C, when the scanning line SCNL101 is at a low level and the TFT 134 is turned off, and the driving line DRL101 is at a high level and the TFT 132 is turned on, the TFT 131 and the light emitting element (OLED) 136 are turned on. A current flows through the light emitting element (OLED) 136, and light emission starts.

  In the operations of steps ST21 and ST22, it is necessary to set the value of Vpc so that Vpc_Vth> Vth_el when Vth_el is the threshold value of OLED. The value of is arbitrary.

  When the current Ioled flowing through the light emitting element (OLED) 136 is calculated after the above operation is performed, if the TFT 131 operates in the saturation region, the following is obtained.

(Equation 15)
Ioled = μCoxW / L / 2 (Vgs−Vth) ²
= ΜCoxW / L / 2 (V _CC −Vs−Vth) ²
= ΜCoxW / L / 2 (Vdata + Vth−Vs−Vth) ²
= ΜCoxW / L / 2 (Vdata−Vs) ²
... (15)

Here, μ represents carrier mobility, Cox represents gate capacitance per unit area, W represents gate width, and L represents gate length.
According to the equation (15), the current Ioled flowing through the light emitting element (OLED) 136 is controlled by Vdata applied from the outside regardless of the threshold value Vth of the TFT 131.
In other words, when the pixel circuit 101D in FIG. 15 is used, it is possible to realize a display device that is relatively unaffected by Vth that varies from pixel to pixel and that has relatively high current uniformity and thus luminance uniformity. The same applies to the case where the TFT 131 operates in the linear region.

  According to the fifth embodiment, the same effects as those of the first and third embodiments described above, that is, the light emission of each pixel stably and accurately regardless of variations in threshold values of active elements inside the pixel. Even if a current having a desired value can be supplied to the element and an offset cancel function using a precharge potential line is provided, the reference potential can be stably maintained, and a gradient in display image luminance can be prevented. As a result, there is an advantage that a high-quality image can be displayed.

  Also in the fifth embodiment, the power supply potential line VCCL is common to the upper and lower sides of the pixel array unit 102 as a display region, that is, both ends of the plurality of power supply potential lines VCCL101 to VCCL10n are connected in common. Therefore, the same potential is achieved. Accordingly, luminance unevenness due to a potential difference in the length direction occurring at the top and bottom of the power supply potential line VCCL in the drawing can be prevented.

  Note that the pixel circuit 101D in FIG. 15 is an example, and the present invention is not limited to this. For example, as described above, since the TFTs 132 to 135 are merely switches, it is obvious that all or a part of them can be constituted by p-channel TFTs or other switching elements.

<Sixth Embodiment>
FIG. 17 is a circuit diagram showing a sixth embodiment of an active matrix organic EL display (display device) according to the present invention.

  The sixth embodiment is different from the fifth embodiment described above in that two adjacent pixel circuits of a pixel circuit arranged in an odd column of the same row and a pixel circuit arranged in an even column are A so-called mirror-type circuit arrangement that is symmetrical with respect to the axis in the column direction, and the power supply potential line VCCL is shared by the adjacent pixel circuits to form the power supply potential line VCCL thicker according to the first embodiment. The even-numbered pixel circuit signal lines and the odd-numbered pixel circuit signal lines that do not take the mirror-type circuit arrangement are wired adjacently, and the even-numbered pixel circuits and the odd-numbered row that do not take this mirror-type circuit arrangement The precharge potential line VPCL is shared between the pixel circuits, and is arranged between the even-numbered pixel circuit signal lines and the odd-numbered pixel circuit signal lines that do not have a mirror-type circuit arrangement. Interference (crosstalk) phenomenon Lies in the fact that so as to suppress.

  Accordingly, the power supply potential line VCCL is wired one by one in the odd columns, the precharge potential line VPCL is arranged for each column, and the precharge potential line VPCLO wired in the odd columns is the drain of the TFT 135 of the pixel circuit in the odd column. Are connected to each other, and the precharge potential line VPCLE wired to the even-numbered columns is connected to the drains of the TFTs 135 of the even-numbered pixel circuits and the TFTs 135 of the odd-numbered pixel circuits that do not take a mirror type circuit arrangement with the even-numbered pixel circuits. The drains are connected in common.

In the pixel array unit 102E, the pixel circuits 101E are arranged in an m × n matrix. However, in FIG. 17, a 2 (= m) × 3 (= n) matrix is shown for simplification of the drawing. The example arranged in the shape is shown.
In FIG. 17, each of the 2 × 3 pixel circuits is represented by Pixel (M, N), Pixel (M, N + 1), Pixel (M, N + 2), Pixel (M + 1, N), and Pixel (M + 1, N + 1). , Pixel (M + 1, N + 2).

  The configuration and operation of each pixel circuit 101E in FIG. 17 are the same as those in the circuit in FIG.

In the pixel circuit Pixel (M, N) arranged in the first row and first column in FIG. 17, the drain of the TFT 131 as a drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the source is connected to the node ND133. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (source of the TFT 131), the source is connected to the anode side of the organic EL light emitting element 136, the gate is connected to the drive line DRL101 wired in the first row, and the light emitting element 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M, N + 1) arranged in the first row and the second column in FIG. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (source of the TFT 131), the source is connected to the anode side of the organic EL light emitting element 136, the gate is connected to the drive line DRL101 wired in the first row, and the light emitting element 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M, N + 2) arranged in the first row and the third column in FIG. 17, the drain of the TFT 131 as the drive transistor is connected to the power supply potential line VCCL103 wired in the third column, and the source is connected to the node ND133. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (source of the TFT 131), the source is connected to the anode side of the organic EL light emitting element 136, the gate is connected to the drive line DRL101 wired in the first row, and the light emitting element 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL103 wired in the third column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL103 wired in the third column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N) arranged in the second row and the first column in FIG. 17, the drain of the TFT 131 as the drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the source is connected to the node ND133. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (the source of the TFT 131), the source is connected to the anode side of the organic EL light emitting device 136, the gate is connected to the drive line DRL102 wired in the second row, and the light emitting device 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M + 1, N + 1) arranged in the second row and the second column in FIG. 17, the drain of the TFT 131 as a drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the source is connected to the node ND133. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (the source of the TFT 131), the source is connected to the anode side of the organic EL light emitting device 136, the gate is connected to the drive line DRL102 wired in the second row, and the light emitting device 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N + 2) arranged in the second row and the third column in FIG. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (the source of the TFT 131), the source is connected to the anode side of the organic EL light emitting device 136, the gate is connected to the drive line DRL102 wired in the second row, and the light emitting device 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL103 wired in the third column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL103 wired in the third column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In such a configuration, for example, as shown in FIG. 18, the select switch 1032 of the data driver is turned on to transfer data to the signal line SGL102, then the select switch 1032 is turned off and the select switch 1033 is turned on. When data is transferred to the signal line SGL103, since the fixed potential precharge potential line VPCL102 exists between the signal line SGL102 and the signal line SGL103, mutual electromagnetic coupling is shielded and crosstalk occurs. Absent.
Therefore, accurate luminance data can be written.

  According to the sixth embodiment, in addition to the effects of the first, third, and fifth embodiments described above, the pixels can be arranged between pixels with a relatively simple wiring configuration without applying a three-dimensional electromagnetic shield. There is an advantage that crosstalk can be prevented and luminance data can be written accurately.

<Seventh embodiment>
FIG. 19 is a circuit diagram showing a seventh embodiment of an active matrix organic EL display (display device) according to the present invention.
FIG. 20 is a diagram showing a wiring arrangement related to the power supply lines of the active matrix organic EL display according to the seventh embodiment.

  The difference between the seventh embodiment and the third embodiment described above is an example in which the precharge potential line VPCL is shared between two pixels adjacent in the scanning line direction. Thus, the number of precharge potential lines VPCL wired in the signal line direction can be halved.

  It is also possible to share the precharge line of the L pixel adjacent in the direction parallel to the scanning line. In this case, the number of pixels that are connected to one of the pre-jersey lines parallel to the signal line and simultaneously cancel the offset is K × L pixels. At this time, L may be selected as an appropriate numerical value as long as the precharge line can be kept at a stable potential.

It is a block diagram showing a general active matrix type organic EL display (display device). It is a circuit diagram which shows the 1st structural example of the conventional pixel circuit. It is a circuit diagram which shows the 2nd structural example of the conventional pixel circuit. 4 is a timing chart for explaining a method of driving the circuit of FIG. 3. It is a figure which shows the example of timing of offset cancellation. 1 is a circuit diagram showing a first embodiment of an active matrix organic EL display (display device) according to the present invention. It is a figure which shows the wiring arrangement | positioning regarding the power source line of the active matrix type organic EL display which concerns on 1st Embodiment. It is a circuit diagram which shows 2nd Embodiment of the active matrix type organic electroluminescent display (display apparatus) based on this invention. It is a figure which shows the wiring arrangement | positioning regarding a power source line of the active matrix type organic EL display which concerns on 2nd Embodiment. It is a figure for demonstrating the crosstalk prevention effect by the precharge electric potential line in 2nd Embodiment. It is a circuit diagram which shows 3rd Embodiment of the active matrix type organic electroluminescent display (display apparatus) which concerns on this invention. 12 is a timing chart for explaining the operation of the pixel circuit of FIG. 11. It is a circuit diagram which shows 4th Embodiment of the active matrix type organic electroluminescent display (display apparatus) based on this invention. It is a figure for demonstrating the crosstalk prevention effect by the precharge electric potential line in 4th Embodiment. FIG. 6 is a circuit diagram showing a fifth embodiment of an active matrix organic EL display (display device) according to the present invention. 16 is a timing chart for explaining the operation of the pixel circuit of FIG. 15. It is a circuit diagram which shows 6th Embodiment of the active matrix type organic electroluminescent display (display apparatus) based on this invention. It is a figure for demonstrating the crosstalk prevention effect | action by the precharge electric potential line in 6th Embodiment. It is a circuit diagram which shows 7th Embodiment of the active matrix type organic electroluminescent display (display apparatus) based on this invention. It is a figure which shows the wiring arrangement | positioning regarding a power source line of the active matrix type organic electroluminescent display which concerns on 7th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100,100A-100F ... Active matrix type organic EL display (display device), 101, 101A-101F ... Pixel circuit, 102, 102A-102F ... Pixel array part, 103 ... Data driver (DDRV), 104 ... Scan driver, 111 , 121, 131, 141... TFT as a drive transistor, 112 to 115, 122 to 125, 132 to 135... TFT as a switch, C111, C112, C121, C122, C131, C132 ... capacitor, ND111 to ND113, ND121 to ND123, ND131 to ND133... Node, VCCL... Power supply potential line, VPCL... Precharge potential line

Claims (8)

A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A signal line to which a data signal corresponding to at least luminance information is supplied;
At least a first control line and a second control line;
A predetermined precharge potential;
A first node;
A second node;
A drive transistor that forms a current supply line between the first terminal and the second terminal and controls a current flowing through the current supply line in accordance with a potential of a control terminal connected to the second node;
A first switch connected between the signal line and the first node, the conduction of which is controlled by the first control line;
A coupling capacitor connected between the first node and a second node connected to the control terminal of the drive transistor;
A second switch having one end connected to the precharge potential, the other end connected to the first node or the second node, and conduction controlled by the second control line;
A pixel circuit in which the precharge potential line is wired in the same direction so as to be parallel to the signal line. A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A signal line to which a signal corresponding to at least luminance information is supplied;
At least a first control line;
First and second reference potentials;
A predetermined precharge potential;
A field effect transistor;
Nodes,
A first switch connected between the source of the field effect transistor and a first reference potential;
A second switch connected between the source of the field effect transistor and the node;
A third switch connected between the gate of the field effect transistor and the precharge potential;
A fourth switch connected between the signal line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The electro-optic element is connected between the drain of the field-effect transistor and a second reference potential;
A pixel circuit in which the precharge potential line is wired in the same direction so as to be parallel to the signal line. A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A signal line to which a signal corresponding to at least luminance information is supplied;
At least a first control line;
First and second reference potentials;
A predetermined precharge potential;
A field effect transistor;
Nodes,
A first switch connected between a source of the field effect transistor and the electro-optic element;
A second switch connected between the source of the field effect transistor and the node;
A third switch connected between the gate of the field effect transistor and the precharge potential;
A fourth switch connected between the signal line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The drain of the field effect transistor is connected to a first reference potential; the electro-optic element is connected between the first switch and a second reference potential;
A pixel circuit in which the precharge potential line is wired in the same direction so as to be parallel to the signal line. A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A signal line to which a signal corresponding to at least luminance information is supplied;
At least a first control line;
First and second reference potentials;
A predetermined precharge potential;
A field effect transistor;
Nodes,
A first switch connected between the drain of the field effect transistor and the electro-optic element;
A second switch connected between the drain and gate of the field effect transistor;
A third switch connected between the node and the precharge potential;
A fourth switch connected between the signal line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the gate of the field effect transistor;
A source of the field effect transistor is connected to a first reference potential; the electro-optic element is connected between a first switch and a second reference potential;
A pixel circuit in which the precharge potential line is wired in the same direction so as to be parallel to the signal line. A plurality of pixel circuits arranged in a matrix;
A signal line that is wired for each column with respect to the matrix arrangement of the pixel circuit and that is supplied with a data signal according to at least luminance information;
At least a first control line wired for each row with respect to the matrix arrangement of the pixel circuit;
A predetermined precharge potential line wired in the same direction as the signal line with respect to the matrix arrangement of the pixel circuit,
Each pixel circuit is
A first node;
A second node;
A drive transistor that forms a current supply line between the first terminal and the second terminal and controls a current flowing through the current supply line in accordance with a potential of a control terminal connected to the second node;
A first switch connected between the signal line and the first node, the conduction of which is controlled by the first control line;
A coupling capacitor connected between the first node and a second node connected to the control terminal of the drive transistor;
A second switch having one end connected to a corresponding precharge potential line, the other end connected to the first node or the second node, and conduction controlled by the second control line. . A plurality of pixel circuits arranged in a matrix;
A signal line that is wired for each column with respect to the matrix arrangement of the pixel circuit and that is supplied with a data signal according to at least luminance information;
At least a first control line wired for each row with respect to the matrix arrangement of the pixel circuit;
A predetermined precharge potential line wired in the same direction as the signal line with respect to the matrix arrangement of the pixel circuit;
First and second reference potentials,
Each pixel circuit is
A field effect transistor;
Nodes,
A first switch connected between the source of the field effect transistor and a first reference potential;
A second switch connected between the source of the field effect transistor and the node;
A third switch connected between the gate of the field effect transistor and the precharge potential;
A fourth switch connected between the signal line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The display device, wherein the electro-optic element is connected between a drain of the field effect transistor and a second reference potential. A plurality of pixel circuits arranged in a matrix;
A signal line that is wired for each column with respect to the matrix arrangement of the pixel circuit and that is supplied with a data signal according to at least luminance information;
At least a first control line wired for each row with respect to the matrix arrangement of the pixel circuit;
A predetermined precharge potential line wired in the same direction as the signal line with respect to the matrix arrangement of the pixel circuit;
First and second reference potentials,
Each pixel circuit is
A field effect transistor;
Nodes,
A first switch connected between a source of the field effect transistor and the electro-optic element;
A second switch connected between the source of the field effect transistor and the node;
A third switch connected between the gate of the field effect transistor and the precharge potential;
A fourth switch connected between the signal line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The display device, wherein the drain of the field effect transistor is connected to a first reference potential, and the electro-optic element is connected between the first switch and a second reference potential. A plurality of pixel circuits arranged in a matrix;
A signal line that is wired for each column with respect to the matrix arrangement of the pixel circuit and that is supplied with a data signal according to at least luminance information;
At least a first control line wired for each row with respect to the matrix arrangement of the pixel circuit;
A predetermined precharge potential line wired in the same direction as the signal line with respect to the matrix arrangement of the pixel circuit;
First and second reference potentials,
Each pixel circuit is
A field effect transistor;
Nodes,
A first switch connected between the drain of the field effect transistor and the electro-optic element;
A second switch connected between the drain and gate of the field effect transistor;
A third switch connected between the node and the precharge potential;
A fourth switch connected between the signal line and the node and controlled in conduction by the first control line;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The source of the field effect transistor is connected to a first reference potential, and the electro-optic element is connected between a first switch and a second reference potential.

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