JP2007256881A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the variance in luminance level of each pixel in a current driven self-luminescent display device, for example, an organic EL display device. <P>SOLUTION: A wiring layer 36, having a voltage lower than that of a driving-side end of a light-emitting element, is provided directly above a double-gatet transistor, connected to one end of a signal level holding capacitor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device, and can be applied to a self-luminous display device driven by current, such as an organic EL (Electro Luminescence) display device. In the present invention, a wiring layer having a lower voltage than the driving side end of the light emitting element is provided immediately above the double gate transistor connected to one end of the signal level holding capacitor, thereby preventing variations in luminance level in each pixel.

  Conventionally, various devices have been proposed for display devices using organic EL elements, for example, in US Pat. No. 5,684,365 and Japanese Patent Laid-Open No. 8-234683.

  FIG. 11 is a block diagram showing a so-called active matrix display device using a conventional organic EL element. In the display device 1, the pixel unit 2 is formed by arranging pixels (PX) 3 in a matrix. In the pixel unit 2, a pair of scanning lines SCN1 and SCN2 are provided in the horizontal direction in units of lines with respect to the pixels 3 arranged in a matrix, and are orthogonal to the pair of scanning lines SCN1 and SCN2. The signal line SIG is provided for each column.

  Here, FIG. 12 is a connection diagram showing the configuration of each pixel 3. The display device 1 using an organic EL element includes an organic EL element 8 in which each pixel 3 is a self-luminous light emitting element driven by current, and a driving circuit (hereinafter referred to as a pixel) for each pixel that drives the organic EL element 8. Called a circuit).

  Here, in the pixel circuit, one end of the signal level holding capacitor C1 is held at a constant potential, and the other end of the signal level holding capacitor C1 is connected to the signal line SIG via the transistor TR1 that is turned on and off by the write signal WS. Is done. Thus, in the pixel circuit, the transistor TR1 is turned on by the rising of the write signal WS, and the other end of the signal level holding capacitor C1 is set to the signal level of the signal line SIG.

In the pixel circuit, the drain of the transistor TR2 is connected to the gate of the transistor TR2 whose source is connected to the power supply VCC via the transistor TR3 which is connected to the other end of the signal level holding capacitor C1 and is turned on / off by the drive pulse signal DS. Is connected to the anode of the organic EL element 8. Here, the pixel circuit is set so that the transistor TR2 always operates in the saturation region. As a result, the transistor TR2 has (1/2) × μ × (W / L) × Cox × (Vgs−Vth) ^2. A constant current circuit with a drain current Ids represented by Here, Vgs is the gate-source voltage of the transistor TR2, and μ is the mobility. W is the channel width, L is the channel length, Cox is the gate capacitance, and Vth is the threshold voltage of the transistor TR2. Thus, in the pixel circuit, the transistor TR3 is turned on by the rise of the drive pulse signal DS, and the organic EL element 8 is turned on by the drive current Ids according to the potential of the signal line SIG set at the other end of the signal level holding capacitor C1. To drive.

  As shown in FIG. 13, the display device 1 drives the scanning lines SCN1 and SCN2 by the vertical drive circuit 4 to sequentially select the pixels 3 of the pixel unit 2 in units of lines. The gray level of each pixel 3 is set by driving the signal line SIG by the horizontal drive circuit 5 so as to correspond to the selection of the pixel 3.

  That is, the vertical drive circuit 4 generates a write signal WS for sequentially instructing writing to each pixel 3 in line units by the write scan circuit (WSCN) 4A, and outputs this write signal WS to the scanning line SCN1 to output each pixel 3 Set the gradation. The vertical drive circuit 4 generates a drive pulse signal DS for controlling the light emission period of each pixel 3 by a drive scan circuit (DSCN) 4B, and outputs the drive pulse signal DS to the scan line SCN2. Further, the horizontal drive circuit 5 generates a drive signal according to the gradation data D1 indicating the gradation of each pixel 3, and distributes this drive signal to each signal line SIG by the horizontal selector (HSEL) 5A and outputs it. In FIG. 13, lines that are continuous in the vertical direction are shown in parentheses. Accordingly, FIG. 13A1 and FIG. 13A2 show the write signal WS output to the uppermost line and subsequent lines on the display screen.

  Here, as shown in FIG. 14, the current-voltage characteristics of the organic EL element 8 change with time in a direction in which current hardly flows when used. In FIG. 14, symbol L1 indicates an initial characteristic, and symbol L2 indicates a characteristic due to a change with time. Accordingly, as shown in FIG. 15 in comparison with FIG. 12, when the N-channel type is applied to all the transistors TR1 to TR3, the current flowing through the organic EL element 8 is gradually increased by the change in the current-voltage characteristics shown in FIG. The luminance of each pixel gradually decreases. FIG. 16 is a timing chart of the display device shown in FIG. 15 in comparison with FIG. However, when the organic EL element 8 is driven with the circuit configuration shown in FIG. 12, it is possible to prevent a change in luminance of each pixel due to a change in current-voltage characteristics over time.

  For an active matrix display device using such an organic EL element, for example, as shown in FIG. 17, the variation in component parts is prevented while preventing a change in luminance of each pixel due to a change in current-voltage characteristics of the light emitting element over time. Some ideas have been proposed to prevent this.

  Here, in the display device 11 shown in FIG. 17, the pixel portion 12 is formed by arranging the pixels 13 in a matrix. Here, in the pixel 13, one end of the signal level holding capacitor C <b> 1 is connected to the anode of the organic EL element 8, and the other end of the signal level holding capacitor C <b> 1 is connected via the transistor TR <b> 1 that operates on and off according to the write signal WS. Is connected to the signal line SIG. Thereby, in the pixel 13, the voltage at the other end of the signal level holding capacitor C1 is set to the signal level Vsig of the signal line SIG in accordance with the write signal WS.

  In the pixel 13, both ends of the signal level holding capacitor C1 are connected to the source and gate of the transistor TR2, and the drain of the transistor TR2 is connected to the power supply Vcc via the transistor TR3 that is turned on and off by the drive pulse signal DS. . Accordingly, the pixel 13 drives the organic EL element 8 to emit light by the transistor TR2 having the source follower circuit configuration in which the gate potential is set to the signal level VSIG of the signal line SIG.

  Further, in the pixel 13, both ends of the signal level holding capacitor C1 are connected to predetermined fixed potentials Vofs and Vini through transistors TR4 and TR5 that are turned on and off by control signals AZ2 and AZ1, respectively. Here, the control signals AZ2 and AZ1 are generated by control signal generation circuits (AZ2, AZ1) 14C and 14D provided in the vertical drive circuit 14, respectively. Here, C2 is the capacity of the organic EL element 8.

  As shown at time t1 in FIG. 18, the control signals AZ2 and AZ1 rise before the terminal voltage of the signal level holding capacitor C1 is set to the signal level Vsig of the signal line SIG by the write signal WS. Thereby, in the pixel 13, the transistors TR4 and TR5 are turned on by the control signals AZ2 and AZ1, and the potentials at both ends of the signal level holding capacitor C1 are set to potentials determined by the fixed potentials Vofs and Vini. Here, the potentials at both ends of the signal level holding capacitor C1 are the gate and source potentials of the transistor TR2 in FIG.

  In the pixel 13, the transistor TR5 is subsequently turned off by the control signal AZ1. The drive pulse signal DS once falls (time t2) and then rises (time t3). As a result, the pixel 13 causes the transistor TR5 to be turned on by discharging the accumulated charge of the signal level holding capacitor C1 via the organic EL element 8 or by the inflow of charge to the signal level holding capacitor C1 via the transistor TR4. The potential at the other end of the signal level holding capacitor C1 set by the above changes, and the potential difference between both ends of the signal level holding capacitor C1 is set to the threshold voltage Vth of the transistor TR2.

  Thereafter, after the transistor TR4 is turned off by the fall of the control signal AZ1, the write signal WS rises at time t4, the potential of the other end of the signal level holding capacitor C1 rises to the signal level Vsig of the signal line SIG, and the signal level The potential difference between both ends of the holding capacitor C1 is set to a voltage Vsig + Vth obtained by adding the signal level Vsig of the signal line SIG to the threshold voltage Vth of the transistor TR2. At this time, since the capacitance of the signal level holding capacitor C1 is sufficiently large, the source potential of the driving transistor TR2 does not change.

  After that, in the pixel 13, after the write signal WS falls and the transistor TR1 is turned off, the drive pulse signal DS falls and the transistor TR2 is turned on at time t5, and the pixel 13 responds to the potential difference between both ends of the signal level holding capacitor C1. The organic EL element 8 emits light by the drive current I. According to the configuration of FIG. 18, after the terminal voltage of the signal level holding capacitor C1 is set in advance to the threshold voltage Vth of the driving transistor TR2 for driving the organic EL element 8, this signal level holding capacitor is used. By setting the terminal voltage of the capacitor C1 to the signal level of the signal line, variations in the threshold voltage Vth of the transistor TR2 can be corrected, and image quality deterioration due to the variations in the threshold voltage Vth can be prevented.

  Thus, in the pixel portion 12 shown in FIG. 17, the transistors TR4 and TR5 constitute a correction circuit that corrects the terminal voltage of the signal level holding capacitor and corrects the variation in the threshold voltage Vth of the transistor TR2. Note that the variation in mobility of the transistor TR2 can also be corrected by setting a period after the transistor TR1 is turned off until the transistor TR3 is turned on at time t5.

By the way, in this type of display device, it is conceivable that the transistor constituting the pixel circuit is constituted by a double gate transistor for the purpose of improving the flexibility of layout. However, it has been found that when the transistor constituting the pixel circuit is constituted by a double gate transistor, a leakage current is generated, the terminal voltage of the signal level holding capacitor C1 varies, and the luminance level varies among the pixels.
USP 5,684,365 JP-A-8-234683

  The present invention has been made in consideration of the above points, and an object of the present invention is to propose a display device capable of preventing variations in luminance level when a transistor constituting a pixel circuit is constituted by a double gate transistor. .

  In order to solve the above-described problems, the invention of claim 1 is applied to a display device having a pixel portion in which pixels are arranged in a matrix and the pixel portion has a drive circuit, and the pixel includes a light emitting element, a signal, and a signal. A level holding capacitor, a signal level setting transistor that is turned on and off by a control signal output from the drive circuit, and sets a terminal voltage at one end of the signal level holding capacitor to a signal level of a signal line; and the signal At least a driving transistor for driving the light emitting element according to a terminal voltage of the level holding capacitor, a transistor connected to one end of the signal level holding capacitor is a double gate transistor, and the signal level holding The driving transistor of the light emitting element is directly above the transistor connected to one end of the capacitor for driving. Wiring layer having a low voltage is provided from the other end.

  When the transistor connected to one end of the signal level holding capacitor is a double gate transistor, the light emitting element driving circuit is directly above the transistor connected to one end of the signal level holding capacitor. If a wiring layer having a lower voltage than the transistor side end is provided, the potential of the intermediate point of the double gate transistor should be set so that the leakage current can be sufficiently reduced when the transistor is turned off. Thus, variation in luminance level due to leakage current can be prevented.

  According to the present invention, it is possible to prevent variations in luminance level when the transistors constituting the pixel circuit are constituted by double gate transistors.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 2 is a connection diagram showing a configuration of a display device according to Embodiment 1 of the present invention in comparison with FIG. In the display device 21, the pixel unit 22 is formed by arranging the pixels 23 in a matrix. In the pixel 23, the transistor TR1 that sets the terminal voltage of the signal level holding capacitor C1 to the signal level Vsig of the signal line SIG is formed of a double gate transistor. The display device 21 is configured in the same manner as the display device 1 described above with reference to FIG. 11 except that the configuration regarding the transistor TR1 in the pixel portion 22 is different.

  Here, as shown in FIGS. 1A and 1B, the pixel portion 22 is formed by laminating a TFT (Thin Film Transistor) or the like on an insulating substrate B made of, for example, a glass substrate. That is, in the pixel portion 22, after the gate electrodes of the transistors TR1 to TR3 constituting the pixel circuit are formed on the insulating substrate B with molybdenum or the like, the gate oxide film M1 is formed with a silicon oxide film or the like. Further, an amorphous silicon film doped with impurities is sequentially deposited on the gate oxide film M1, and then the source electrode S and the drain electrode D of the transistors TR1 to TR3 are formed. In the transistor TR1, which is a double gate transistor, a gate electrode (not shown) is formed after further depositing a predetermined silicon oxide film. In the pixel portion 22, the transistors TR1 to TR3 created in this way are protected by an insulating layer M2 made of a silicon oxide film, and are wired with a circuit configuration shown in FIG. Lines SCN1 and SCN2 are created. Further, in the pixel portion 22, the anode electrode 34 of the organic EL element 8 is further formed on the front side surface of the insulating layer M2, and then the cathode electrode 36 is formed so as to sandwich the organic EL element material 35 therebetween. Reference numeral 37 denotes an insulating layer made of a silicon oxide film or the like. In the pixel portion 22, the anode electrode 34 is insulated between adjacent pixels 23, the organic EL element material 35 is disposed for each pixel 23, and the organic EL element 8 is provided for each pixel 23. On the other hand, the cathode electrode 36 is formed in common by the adjacent pixels 23. Note that FIG. 1B is a cross-sectional view taken along line AA in FIG.

  In the display device 21, a transistor TR2 for driving the organic EL element 8 and a transistor TR3 for controlling the transistor TR2 are disposed below the portion where the organic EL element material 35 is disposed. On the other hand, the double gate transistor TR1 for setting the signal level of the signal line SIG to the signal level holding capacitor C1 is arranged avoiding the lower layer of the organic EL element material 35.

  The display device 21 is set so that a wiring layer having a voltage lower than at least the driving side end voltage of the organic EL element 8 is directly above the double-gate transistor TR1 disposed so as to avoid the lower layer of the organic EL element material 35. The More specifically, in this embodiment, since the anode side of the organic EL element 8 is driven by the transistor TR3, the wiring layer whose voltage is lower than the anode side end of the organic EL element 8 is the double-gate transistor TR1. It is set to be directly above. In the display device 21, the cathode electrode 36 is assigned to the wiring layer. Here, the term “directly above” means, as a matter of course, directly above, with the insulating layer interposed therebetween.

  Therefore, in each pixel 23, the cathode electrode 36 covers the entire surface of the pixel portion 22, and an anode electrode 34 opposite to the cathode electrode 36 is provided so as to avoid at least directly above the double-gate transistor TR3. By setting the wiring layer, the display device 21 prevents the leakage current IR (FIG. 2) of the double-gate transistor TR1, and the luminance level variation in the case where the transistor constituting the pixel circuit is constituted by the double-gate transistor. To prevent.

  That is, as shown in FIG. 3, in the transistor TR1 for setting the terminal voltage of the signal level holding capacitor C1 to the potential of the signal line SIG, the potential of the wiring layer disposed immediately above the potential of the anode electrode 34 of the organic EL element 8 In the case of a potential, coupling capacitors CA to CC are formed at intermediate points by the substrate bias effect due to the potential of the anode electrode 34. For this reason, in this embodiment, as shown in FIG. 4, the potential at the intermediate point is held at -2 [V] with respect to the potential -2.4 [V] of the anode electrode 34. As shown, the double gate transistor exhibits the characteristics of a depletion type transistor. As a result, in this case, even if the transistor TR1 is turned off by the write signal WS, the leakage current IR flows to the signal line SIG via the transistor TR1, and the terminal voltage of the signal level holding capacitor C1 Changes from the normal voltage, and a variation in luminance level occurs in each pixel 23. The characteristic shown in FIG. 5 is that the drain-source voltage Vds is set to 10 [V], and the potential of the anode 34 is set to 0 [V], 5 [V], 10 [V], and 15 [V]. Vgs is a gate-source voltage, and Ids is a source current.

  However, as in this embodiment, more specifically, the cathode electrode is directly above the double gate transistor TR1 so that the wiring layer having a lower voltage than the anode side end of the organic EL element 8 is directly above the double gate transistor TR1. By arranging 36, the leakage current IR of the transistor TR1 can be prevented, and as a result, variations in the luminance level of each pixel can be prevented.

(2) Operation of Embodiment In the above configuration, in this display device 21 (FIG. 2), the horizontal drive circuit 5 is applied to the pixels 23 of the pixel unit 22 in units of lines sequentially by driving the scanning lines SCN1 and SCN2 by the vertical drive circuit 4. The signal level of the signal line SIG driven by is set, and each pixel 23 emits light according to the set signal level, and a desired image is displayed on the pixel unit 22.

  In each pixel 23, the transistor TR1 is turned on by the write signal WS output to the scanning line SCN1, and the terminal voltage of the signal level holding capacitor C1 is set to the signal level of the signal line SIG. Also, the transistor TR3 is turned on by driving the scanning line SCN1, and the organic EL element 8 is driven by the transistor TR2 by the driving current corresponding to the terminal voltage of the signal level holding capacitor C1, and the gray level set by the signal line SIG is set. Emits light (see FIG. 13).

  However, when the transistor TR1 connected to the terminal of the signal level holding capacitor C1 is simply constituted by a double gate transistor, the leakage current IR of the transistor TR1 causes the signal level holding capacitor C1 set to the potential of the signal line SIG. The terminal voltage will change. This leakage current IR changes due to variations in the transistor TR1 provided in each pixel 23. As a result, variations in luminance level occur in the pixel portion 22.

  For this reason, in this display device 21, the wiring layer having a lower voltage than the anode side end of the organic EL element 8 is set to be directly above the double-gate transistor TR1, and more specifically, directly above the double-gate transistor TR1. The cathode electrode 36 is disposed, and the potential at the intermediate point when the transistor TR1 is turned off is set to a sufficiently low voltage. As a result, in the display device 21, the leakage current IR of the transistor TR1 is prevented, and variations in the luminance level in each pixel 23 are prevented.

  If the transistor TR1 is arranged below the cathode electrode while avoiding the area below the anode electrode in this way, the area occupied by the pixel circuit can be reduced and the definition can be increased.

(3) Effects of the embodiment According to the above configuration, the driving side of the organic EL element is connected to one end of the signal level holding capacitor and directly above the double gate transistor for setting the signal level holding capacitor terminal voltage. By providing a wiring layer having a lower voltage than the end, variations in luminance level in each pixel can be prevented.

  More specifically, by disposing the cathode electrode of the organic EL element immediately above the double gate transistor, it is possible to prevent variations in luminance level in each pixel.

  FIG. 6 is a connection diagram showing a display apparatus according to a second embodiment of the present invention in comparison with FIG. The display device 31 is configured the same as the display device 21 of the first embodiment except that the configuration of the pixel unit 32 is different. The pixel unit 32 is configured in the same manner as the pixel unit 22 of the display device 21 described above with respect to the first embodiment except that the configuration of the pixel 33 is different.

  Here, in each pixel 33, the organic EL element 8 is directly connected to the transistor TR2 having a source follower circuit configuration, and a signal level holding capacitor C1 is disposed between the gate and source of the transistor TR2. Further, the transistor TR2 is turned on and off by the transistor TR3 to control light emission and non-light emission of the organic EL element 8. Each pixel 33 sets the terminal voltage of the signal level holding capacitor C1 connected to the gate of the transistor TR2 to the signal level of the signal line SIG by ON / OFF control of the transistor TR1, and sets the gradation of the organic EL element 8. To do. FIG. 7 is a timing chart showing the operation of each pixel 33 shown in FIG.

  In this embodiment, in the pixel 33, the transistors TR1 and TR3 respectively connected to both ends of the signal level holding capacitor C1 are constituted by double gate transistors. Of these transistors TR1 and TR3, the transistor TR1 is a transistor for setting the terminal voltage of the signal level holding capacitor C1. Therefore, like the transistor TR1 of the first embodiment, the anode of the organic EL element 8 is directly above. A wiring layer having a lower voltage than the side end is disposed, and more specifically, the cathode electrode 36 of the organic EL element is disposed immediately above.

  As a result, in this embodiment, leakage current due to the transistor TR1 is prevented, fluctuation of the terminal voltage of the signal level holding capacitor C1 is prevented, and variation in luminance level is prevented.

  Even in the configuration in which the organic EL element is driven by the transistor of the source follower circuit configuration as in this embodiment, a voltage lower than the anode side end of the organic EL element is directly above the transistor that sets the terminal voltage of the signal level holding capacitor. By arranging the wiring layer, more specifically, by arranging the cathode electrode of the organic EL element immediately above, it is possible to prevent variations in luminance level.

  FIG. 8 is a connection diagram showing the display apparatus according to the third embodiment of the present invention in comparison with FIG. The display device 41 has the same configuration as that of the display device of FIG. 17 except that the transistors TR1, TR4, and TR5 are double gate transistors in the pixel unit 42, and the configuration of the transistors TR1, TR4, and TR5 is different. Is done.

  Here, in each pixel 43 of the display device 41, the transistors TR1 and TR4 out of the double gate transistors TR1, TR4, and TR5 are transistors that set the terminal voltage of the signal level holding capacitor C1. As with the first transistor TR1, a wiring layer having a lower voltage than the anode side end of the organic EL element 8 is disposed immediately above these transistors TR1 and TR4, and more specifically, the cathode electrode 36 of the organic EL element is disposed. Is done.

  As a result, in this embodiment, leakage current due to the transistors TR1 and TR4 is prevented, fluctuation of the terminal voltage of the signal level holding capacitor C1 is prevented, and variation in luminance level is prevented.

  Even when a transistor is separately connected to one end of the signal level holding capacitor C1 for setting the signal level of the signal line SIG as in this embodiment, the terminal voltage of the signal level holding capacitor C1 is corrected. By disposing a wiring layer having a lower voltage than the anode side end of the organic EL element directly above the transistor, more specifically, by disposing the cathode electrode of the organic EL element directly above, the luminance level variation can be prevented. be able to.

  FIG. 9 is a connection diagram showing the display device of Example 4 of the present invention in comparison with FIG. As shown in FIG. 10 in comparison with FIG. 1, the display device 51 has a lower voltage than the anode side end of the organic EL element disposed immediately above the double gate transistors TR 1 and TR 4 in each pixel 53 of the pixel unit 52. A wiring pattern 56 of the constant voltage Vini supplied to the source side of the transistor TR5 is applied to the wiring layer. Here, the constant voltage Vini is −3.3 [V] in this embodiment. The display device 51 of this embodiment is configured in the same manner as that of Embodiment 3 except that the configuration of the wiring layer is different. In FIG. 10, although the cathode electrode and the like are arranged on the upper layer of the constant voltage Vini wiring pattern 56 in the same manner as in the first embodiment, the layout on the upper layer side is shown. Various settings can be made.

  Similar to the third embodiment, another constant voltage wiring pattern may be applied to the wiring layer having a lower voltage than the anode side end of the organic EL element disposed immediately above the double gate transistor as in this embodiment. The effect of can be obtained.

  In the above-described fourth embodiment, the voltage between the terminals of the signal level holding capacitor is corrected with the threshold voltage of the driving transistor for driving the organic EL element by using the correction circuit by the transistors TR4 and TR5, and the driving circuit is used. Although the case where the variation in the threshold voltage of the transistor is corrected has been described, the present invention is not limited to this, and is widely applied to display devices using various correction circuits for correcting the voltage across the terminals of the signal level holding capacitor. be able to.

  Further, in the above-described embodiment, when the pixel circuit of each pixel is configured with a specific circuit configuration, the leakage current of the Dackle gate transistor connected to the signal level holding capacitor is prevented to prevent luminance level variations. Although the case has been described, the present invention is not limited to this, and can be widely applied when the pixel circuit is configured by various circuit configurations.

  In the above-described embodiments, the case where the light emitting element by the organic EL element is current-driven has been described. However, the present invention is not limited to this, and can be widely applied to display devices using various light-emitting elements related to current driving. .

  The present invention relates to a display device, and can be applied to a self-luminous display device driven by current, such as an organic EL display device.

It is the top view and sectional drawing which show the layout of the pixel in the display apparatus of Example 1 of this invention. It is a connection diagram which shows the display apparatus of Example 1 of this invention. It is a connection diagram for explanation of the operation of the double gate transistor. FIG. 4 is a connection diagram for explaining the operation of the double gate transistor according to the first embodiment in comparison with FIG. 3. It is a characteristic curve figure of a double gate transistor. It is a connection diagram which shows the display apparatus of Example 2 of this invention. It is a timing chart with which it uses for description of operation | movement of the display apparatus of FIG. It is a connection diagram which shows the display apparatus of Example 3 of this invention. It is a connection diagram which shows the display apparatus of Example 4 of this invention. FIG. 10 is a cross-sectional view illustrating a pixel layout in the display device of FIG. 9. It is a block diagram which shows the active matrix type display apparatus using the conventional organic EL element. FIG. 12 is a connection diagram illustrating a configuration of a pixel in the display device of FIG. 11. 12 is a timing chart for explaining the operation of the display device of FIG. 11. It is a characteristic curve figure which shows a time-dependent change of an organic EL element. It is a connection diagram which shows the other example of the conventional display apparatus. It is a timing chart with which it uses for description of operation | movement of the display apparatus of FIG. FIG. 16 is a connection diagram illustrating another example of a conventional display device different from the example of FIG. 15. It is a timing chart with which it uses for description of operation | movement of the display apparatus of FIG.

Explanation of symbols

1, 11, 21, 31, 41, 51... Display device, 2, 12, 22, 32, 42, 52... Pixel unit, 3, 13, 23, 33, 43, 53. ...... Vertical drive circuit, 5 ... Horizontal drive circuit, 8 ... Organic EL element, C1 ... Signal level holding capacitor, TR1 to TR5 ... Transistor, 34 ... Anode electrode, 35 ... Organic EL material, 36 …… Cathode electrode

Claims (5)

In a display device having a pixel portion in which pixels are arranged in a matrix and a driving circuit for driving the pixel portion,
The pixel is
A light emitting element;
A signal level holding capacitor;
A signal level setting transistor that is turned on and off by a control signal output from the drive circuit and sets a terminal voltage at one end of the signal level holding capacitor to a signal level of a signal line;
And at least a driving transistor for driving the light emitting element according to a terminal voltage of the signal level holding capacitor,
The transistor connected to one end of the signal level holding capacitor is a double gate transistor,
A display device, wherein a wiring layer having a voltage lower than that of the driving transistor side end of the light emitting element is provided immediately above a transistor connected to one end of the signal level holding capacitor. The low-voltage wiring layer is
It is a wiring layer of the cathode electrode of the said light emitting element. The display apparatus of Claim 1 characterized by the above-mentioned. The low-voltage wiring layer is
The display device according to claim 1, wherein the display device is a constant voltage wiring layer for correcting a voltage between terminals of the signal level holding capacitor. The display device according to claim 1, wherein the double gate transistor is the signal level setting transistor. The display device according to claim 1, wherein the double gate transistor is a transistor of a correction circuit that corrects a voltage between terminals of the signal level holding capacitor.

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