JP4477380B2 - マルチレイヤシステム及びクロック制御方法 - Google Patents

マルチレイヤシステム及びクロック制御方法 Download PDF

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Publication number
JP4477380B2
JP4477380B2 JP2004057608A JP2004057608A JP4477380B2 JP 4477380 B2 JP4477380 B2 JP 4477380B2 JP 2004057608 A JP2004057608 A JP 2004057608A JP 2004057608 A JP2004057608 A JP 2004057608A JP 4477380 B2 JP4477380 B2 JP 4477380B2
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JP
Japan
Prior art keywords
slave
master
clock
switch
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004057608A
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English (en)
Japanese (ja)
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JP2005250653A5 (enExample
JP2005250653A (ja
Inventor
幸子 星
恭一 成相
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
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NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Priority to JP2004057608A priority Critical patent/JP4477380B2/ja
Priority to US11/054,952 priority patent/US20050198429A1/en
Priority to KR1020050015576A priority patent/KR100700158B1/ko
Priority to CNB2005100530333A priority patent/CN100461066C/zh
Publication of JP2005250653A publication Critical patent/JP2005250653A/ja
Publication of JP2005250653A5 publication Critical patent/JP2005250653A5/ja
Application granted granted Critical
Publication of JP4477380B2 publication Critical patent/JP4477380B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Bus Control (AREA)
  • Power Sources (AREA)
  • Information Transfer Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Electronic Switches (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2004057608A 2004-03-02 2004-03-02 マルチレイヤシステム及びクロック制御方法 Expired - Fee Related JP4477380B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2004057608A JP4477380B2 (ja) 2004-03-02 2004-03-02 マルチレイヤシステム及びクロック制御方法
US11/054,952 US20050198429A1 (en) 2004-03-02 2005-02-11 Multilayer system and clock control method
KR1020050015576A KR100700158B1 (ko) 2004-03-02 2005-02-24 다층시스템 및 클록제어방법
CNB2005100530333A CN100461066C (zh) 2004-03-02 2005-03-02 多层系统和时钟控制方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004057608A JP4477380B2 (ja) 2004-03-02 2004-03-02 マルチレイヤシステム及びクロック制御方法

Publications (3)

Publication Number Publication Date
JP2005250653A JP2005250653A (ja) 2005-09-15
JP2005250653A5 JP2005250653A5 (enExample) 2006-11-16
JP4477380B2 true JP4477380B2 (ja) 2010-06-09

Family

ID=34909042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004057608A Expired - Fee Related JP4477380B2 (ja) 2004-03-02 2004-03-02 マルチレイヤシステム及びクロック制御方法

Country Status (4)

Country Link
US (1) US20050198429A1 (enExample)
JP (1) JP4477380B2 (enExample)
KR (1) KR100700158B1 (enExample)
CN (1) CN100461066C (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006195746A (ja) * 2005-01-13 2006-07-27 Oki Electric Ind Co Ltd マルチレイヤバスシステム
JP2007183860A (ja) * 2006-01-10 2007-07-19 Nec Electronics Corp クロック制御回路
JP2007287029A (ja) * 2006-04-19 2007-11-01 Freescale Semiconductor Inc バス制御システム
JP4967483B2 (ja) * 2006-07-06 2012-07-04 富士通セミコンダクター株式会社 クロック切り替え回路
JP6056363B2 (ja) * 2012-10-12 2017-01-11 株式会社ソシオネクスト 処理装置及び処理装置の制御方法
JP6395647B2 (ja) * 2015-03-18 2018-09-26 ルネサスエレクトロニクス株式会社 半導体装置
EP4354250A1 (en) * 2022-10-14 2024-04-17 EM Microelectronic-Marin SA Clock distribution network

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1008594B (zh) * 1985-05-21 1990-06-27 D·A·V·I·D·系统公司 数字小交换机中使用的数字时隙和信号总线
JPH02201516A (ja) * 1989-01-31 1990-08-09 Toshiba Corp パワーセーブ方式
US5600839A (en) * 1993-10-01 1997-02-04 Advanced Micro Devices, Inc. System and method for controlling assertion of a peripheral bus clock signal through a slave device
US5615376A (en) * 1994-08-03 1997-03-25 Neomagic Corp. Clock management for power reduction in a video display sub-system
US5951689A (en) * 1996-12-31 1999-09-14 Vlsi Technology, Inc. Microprocessor power control system
US5881297A (en) * 1996-12-31 1999-03-09 Intel Corporation Apparatus and method for controlling clocking frequency in an integrated circuit
US6021500A (en) * 1997-05-07 2000-02-01 Intel Corporation Processor with sleep and deep sleep modes
US6079024A (en) * 1997-10-20 2000-06-20 Sun Microsystems, Inc. Bus interface unit having selectively enabled buffers
US6085330A (en) * 1998-04-07 2000-07-04 Advanced Micro Devices, Inc. Control circuit for switching a processor between multiple low power states to allow cache snoops
US6424659B2 (en) * 1998-07-17 2002-07-23 Network Equipment Technologies, Inc. Multi-layer switching apparatus and method
US6609209B1 (en) * 1999-12-29 2003-08-19 Intel Corporation Method and apparatus for reducing the power consumed by a processor by gating the clock signal to pipeline stages
US6611920B1 (en) * 2000-01-21 2003-08-26 Intel Corporation Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit
EP1182552A3 (en) * 2000-08-21 2003-10-01 Texas Instruments France Dynamic hardware configuration for energy management systems using task attributes
US20030226050A1 (en) * 2000-12-18 2003-12-04 Yik James Ching-Shau Power saving for mac ethernet control logic
JP2002351825A (ja) * 2001-05-29 2002-12-06 Rohm Co Ltd 通信システム
JP2003141061A (ja) * 2001-11-01 2003-05-16 Nec Corp Ｉ２ｃバス制御方法及びｉ２ｃバスシステム
US6583659B1 (en) * 2002-02-08 2003-06-24 Pericom Semiconductor Corp. Reduced clock-skew in a multi-output clock driver by selective shorting together of clock pre-outputs
US7477662B2 (en) * 2003-02-14 2009-01-13 Infineon Technologies Ag Reducing power consumption in data switches
JP3857661B2 (ja) * 2003-03-13 2006-12-13 インターナショナル・ビジネス・マシーンズ・コーポレーション 情報処理装置、プログラム、及び記録媒体
US6981088B2 (en) * 2003-03-26 2005-12-27 Lsi Logic Corporation System and method of transferring data words between master and slave devices
US7099689B2 (en) * 2003-06-30 2006-08-29 Microsoft Corporation Energy-aware communications for a multi-radio system
JP2005250650A (ja) * 2004-03-02 2005-09-15 Nec Electronics Corp マルチレイヤシステム及びクロック制御方法
JP2005250833A (ja) * 2004-03-04 2005-09-15 Nec Electronics Corp バスシステム及びアクセス制御方法

Also Published As

Publication number Publication date
CN1664743A (zh) 2005-09-07
US20050198429A1 (en) 2005-09-08
KR100700158B1 (ko) 2007-03-27
JP2005250653A (ja) 2005-09-15
KR20060042176A (ko) 2006-05-12
CN100461066C (zh) 2009-02-11

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