JP4476977B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4476977B2 JP4476977B2 JP2006200425A JP2006200425A JP4476977B2 JP 4476977 B2 JP4476977 B2 JP 4476977B2 JP 2006200425 A JP2006200425 A JP 2006200425A JP 2006200425 A JP2006200425 A JP 2006200425A JP 4476977 B2 JP4476977 B2 JP 4476977B2
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- JP
- Japan
- Prior art keywords
- conductor
- resin package
- conductors
- semiconductor device
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
また、好ましい実施の形態の構成について、上記樹脂パッケージは、x方向に間隔を隔てた一対の第1の側面と、x方向に直交するy方向に間隔を隔てた一対の第2の側面とを有しているとともに、上記複数の導体は、それらの端子部がx方向に間隔を隔てて対をなすように設けられており、かつ上記非矩形状に形成された厚肉部は、上記樹脂パッケージの中央寄りになるほどy方向の幅が小さくなる先細形状部を有している。この先細形状部は、略台形状、略三角形状、または略半円状である、と表現することもできる。このような構成によれば、上記樹脂パッケージを金型を利用して成形するときに、上記先細形状部は、成形用の樹脂を上記樹脂パッケージの隅部(第1および第2の側面が互いに交差して繋がっている部分)に相当する箇所へスムーズに流れ込むようにガイドする役割を果たすこととなる。したがって、上記樹脂パッケージの隅部に樹脂の未充填部分が発生しないようにして、上記樹脂パッケージにクラックがより生じ難くすることが可能となる。
また、上記各導体は、上記第1の側面から露出した端部を有しており、かつこの端部には凹部が形成されていてもよい。このような構成によれば、半導体装置の面実装時に、ハンダを上記凹部に進入させることができ、これによって上記各導体とハンダとの接合面積を大きくして、半導体装置の実装強度を高めることが可能となる。
1 半導体チップ
2A,2B,2B’ 導体
3 樹脂パッケージ
10a 電極
21a,21b 厚肉部
22a,22b 薄肉部
23a,23b 端子部
25a,25b 凹部
30b 底面(樹脂パッケージの)
30c,30d 第1の側面(樹脂パッケージの)
30e,30f 第2の側面(樹脂パッケージの)
Claims (4)
- 半導体チップと、この半導体チップに接続された複数の導体と、これら複数の導体および半導体チップを封止する樹脂パッケージと、を有しており、
上記各導体は、厚みが相違する厚肉部と薄肉部とを有し、かつ上記厚肉部の下面部が上記樹脂パッケージの底面から露出した面実装用の端子部とされている、半導体装置であって、
上記複数の導体のうちの一つの第1の導体には半導体チップが搭載され、上記複数の導体における他の導体のうちの少なくとも一つの第2の導体には半導体チップの電極にボンディングされたワイヤの他端がボンディングされており、
第2の導体は樹脂パッケージの底面に隣接する側面の一つからこの側面に垂直に樹脂パッケージ中央寄りの方向に伸びており、第2の導体の厚肉部は樹脂パッケージの中央寄りになるほど幅が小さくなる先細形状部を有しており、第2の導体の薄肉部は樹脂パッケージの中央寄りになるほど幅が大きくなる肩部を有している半導体装置。 - 上記樹脂パッケージは、上記底面に隣接する側面の一つを含む、x方向に間隔を隔てた一対の第1の側面と、x方向に直交するy方向に間隔を隔てた一対の第2の側面とを有しているとともに、
上記複数の導体は、それらの端子部がx方向に間隔を隔てて対をなすように設けられており、かつ、
非矩形状に形成された上記厚肉部は、上記樹脂パッケージの中央寄りになるほどy方向の幅が小さくなる先細形状部を有している、請求項1に記載の半導体装置。 - さらに、半導体チップに接続されないダミー端子となる導体が、上記複数の導体および半導体チップとともに樹脂パッケージにより封止されている請求項1または2に記載の半導体装置。
- 第2の導体は、上記側面から露出した端部を有しており、かつこの端部には凹部が形成されている、請求項1ないし3のいずれか1項に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006200425A JP4476977B2 (ja) | 2006-07-24 | 2006-07-24 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006200425A JP4476977B2 (ja) | 2006-07-24 | 2006-07-24 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002176821A Division JP4002476B2 (ja) | 2002-06-18 | 2002-06-18 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009298268A Division JP5171803B2 (ja) | 2009-12-28 | 2009-12-28 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006287263A JP2006287263A (ja) | 2006-10-19 |
JP4476977B2 true JP4476977B2 (ja) | 2010-06-09 |
Family
ID=37408745
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006200425A Expired - Lifetime JP4476977B2 (ja) | 2006-07-24 | 2006-07-24 | 半導体装置 |
Country Status (1)
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JP (1) | JP4476977B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010040894A (ja) | 2008-08-07 | 2010-02-18 | Rohm Co Ltd | 半導体装置および半導体装置の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0758271A (ja) * | 1993-08-20 | 1995-03-03 | Mitsubishi Electric Corp | 半導体装置用リードフレームおよびそれを用いた半導体装置の製造方法 |
JP3686287B2 (ja) * | 1999-07-14 | 2005-08-24 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP3915337B2 (ja) * | 1999-09-01 | 2007-05-16 | 松下電器産業株式会社 | リードフレームとそれを用いた樹脂封止型半導体装置の製造方法 |
JP3732987B2 (ja) * | 1999-12-28 | 2006-01-11 | 株式会社ルネサステクノロジ | 半導体装置 |
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2006
- 2006-07-24 JP JP2006200425A patent/JP4476977B2/ja not_active Expired - Lifetime
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JP2006287263A (ja) | 2006-10-19 |
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