JP4467489B2 - 回路基板およびそれを用いた回路装置 - Google Patents
回路基板およびそれを用いた回路装置 Download PDFInfo
- Publication number
- JP4467489B2 JP4467489B2 JP2005250369A JP2005250369A JP4467489B2 JP 4467489 B2 JP4467489 B2 JP 4467489B2 JP 2005250369 A JP2005250369 A JP 2005250369A JP 2005250369 A JP2005250369 A JP 2005250369A JP 4467489 B2 JP4467489 B2 JP 4467489B2
- Authority
- JP
- Japan
- Prior art keywords
- opening
- metal substrate
- circuit board
- insulating layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 94
- 239000000945 filler Substances 0.000 claims description 37
- 230000017525 heat dissipation Effects 0.000 claims description 23
- 239000004020 conductor Substances 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 110
- 229910052751 metal Inorganic materials 0.000 description 85
- 239000002184 metal Substances 0.000 description 85
- 229920005989 resin Polymers 0.000 description 27
- 239000011347 resin Substances 0.000 description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 23
- 239000010949 copper Substances 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000011889 copper foil Substances 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 8
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 241000135309 Processus Species 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 3
- 229910001374 Invar Inorganic materials 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000003112 inhibitor Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000113 differential scanning calorimetry Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 229920001690 polydopamine Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
- H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0382—Continuously deformed conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09054—Raised area or protrusion of metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0323—Working metal substrate or core, e.g. by etching, deforming
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Description
図1は、本発明の第1実施形態に係る金属基板を備えた回路基板を有する回路装置を示した断面図である。図2は、図1中の金属基板の開口部近傍の拡大図である。
図6は、本発明の第1実施形態の変形例に係る金属基板を備えた回路基板を有する回路装置を示した断面図である。第1実施形態の変形例では、金属基板1の開口部2の端に設けられた突起1aを、LSIチップ20を搭載する側(開口部2の上面側)ではなく、開口部2の下面側に突起1aを形成している。それ以外については、第1実施例と同様である。
図7は、本発明の第2実施形態に係る金属基板を備えた回路基板を有する回路装置を示した断面図である。第1実施形態と異なる箇所は、金属基板1の開口部2の端に設けられた突起1aを、金属基板1の開口部すべてに設けるのではなく、突起を設けない開口部2b(端部1c)を混合して形成していることである。それ以外については、第1実施形態と同様である。
図8は、本発明の第3実施形態に係る金属基板を備えた回路基板を有する回路装置を示した断面図である。第1実施形態と異なる箇所は、金属基板1の上面側に突起1a(反対側はへたり1b)を有する開口部2と、金属基板1の下面側に突起1a(反対側はへたり1b)を有する開口部2aとを混合して形成していることである。尚、図中では、上面側と下面側に1箇所の突起を有する例を示しているが、実際には、搭載する回路素子20の位置に応じて効果的に放熱できるように、開口部2(上面側の突起1a)と開口部2a(下面側の突起1a)を配置している。それ以外については、第1実施形態と同様である。
1a 開口部の突起
1b 開口部の丸みを帯びた角部
2 開口部
3,5 絶縁層
3a,5a 開口部内の絶縁層
4,6 配線層(配線パターン層)
7 スルーホール
8 導体層
10 回路基板
20 LSIチップ
21 半田ボール
50 回路装置
Claims (3)
- 基板と、
前記基板に設けられた開口部と、
前記基板の一方の面に、第1の絶縁層を介して設けられた第1の配線層と、
前記基板の他方の面に、前記第1の絶縁層と同じ組成である第2の絶縁層を介して設けられた第2の配線層と、
前記開口部を介して前記基板を貫通し、前記第1の配線層と第2の配線層とを接続する導体層と、
を備え、
前記基板の前記一方の面側において、前記開口部の端に沿って突起を設け、
前記開口部の、前記突起とは反対側の開口端部に沿って丸みを帯びた角部を設け、
前記第1の絶縁層および前記第2の絶縁層は、それぞれ絶縁層の放熱性を向上させるための充填材を含有し、
前記開口部内における前記突起側の充填材の濃度が、前記開口部内における前記丸みを帯びた角部側の充填材の濃度よりも高いことを特徴とした回路基板。 - 請求項1に記載の回路基板と、
前記回路基板に搭載された回路素子と、を備え、
前記回路素子は、前記基板の前記一方の面側において前記第1の配線層に接続されていることを特徴とした回路装置。 - 前記回路素子は、前記突起を有する開口部に隣接して配置されていることを特徴とした請求項2に記載の回路装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005250369A JP4467489B2 (ja) | 2005-08-30 | 2005-08-30 | 回路基板およびそれを用いた回路装置 |
US11/511,496 US7420126B2 (en) | 2005-08-30 | 2006-08-29 | Circuit board and circuit apparatus using the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005250369A JP4467489B2 (ja) | 2005-08-30 | 2005-08-30 | 回路基板およびそれを用いた回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007067120A JP2007067120A (ja) | 2007-03-15 |
JP4467489B2 true JP4467489B2 (ja) | 2010-05-26 |
Family
ID=37802454
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005250369A Expired - Fee Related JP4467489B2 (ja) | 2005-08-30 | 2005-08-30 | 回路基板およびそれを用いた回路装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7420126B2 (ja) |
JP (1) | JP4467489B2 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8035992B2 (en) * | 2005-10-18 | 2011-10-11 | Nec Corporation | Vertical transitions, printed circuit boards therewith and semiconductor packages with the printed circuit boards and semiconductor chip |
US8440916B2 (en) | 2007-06-28 | 2013-05-14 | Intel Corporation | Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method |
US8877565B2 (en) * | 2007-06-28 | 2014-11-04 | Intel Corporation | Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method |
US20110108955A1 (en) * | 2008-07-16 | 2011-05-12 | Koninklijke Philips Electronics N.V. | Semiconductor device and manufacturing method |
KR101002680B1 (ko) * | 2008-10-21 | 2010-12-21 | 삼성전기주식회사 | 반도체 패키지 및 그 제조 방법 |
JP5138549B2 (ja) | 2008-10-31 | 2013-02-06 | 日東電工株式会社 | 回路付サスペンション基板 |
KR101006603B1 (ko) * | 2009-01-09 | 2011-01-07 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
KR101167427B1 (ko) * | 2010-09-29 | 2012-07-19 | 삼성전기주식회사 | 양극산화 방열기판 및 그 제조방법 |
KR101194456B1 (ko) * | 2010-11-05 | 2012-10-24 | 삼성전기주식회사 | 방열기판 및 그 제조방법 |
TWI505765B (zh) * | 2010-12-14 | 2015-10-21 | Unimicron Technology Corp | 線路板及其製造方法 |
KR101181105B1 (ko) | 2010-12-24 | 2012-09-07 | 엘지이노텍 주식회사 | 방열회로기판 및 그 제조 방법 |
US20120199386A1 (en) * | 2011-02-04 | 2012-08-09 | Ibiden Co., Ltd. | Multilayer printed wiring board |
US20120247818A1 (en) * | 2011-03-29 | 2012-10-04 | Ibiden Co., Ltd. | Printed wiring board |
US8772646B2 (en) * | 2011-03-29 | 2014-07-08 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing printed wiring board |
JP5754333B2 (ja) * | 2011-09-30 | 2015-07-29 | イビデン株式会社 | 多層プリント配線板及び多層プリント配線板の製造方法 |
KR101567929B1 (ko) | 2014-04-01 | 2015-11-20 | 주식회사 루멘스 | 발광 소자 패키지, 백라이트 유닛, 조명 장치 및 발광 소자 패키지의 제조 방법 |
US9706639B2 (en) * | 2015-06-18 | 2017-07-11 | Samsung Electro-Mechanics Co., Ltd. | Circuit board and method of manufacturing the same |
CN109661125B (zh) * | 2017-10-12 | 2021-11-16 | 宏启胜精密电子(秦皇岛)有限公司 | 电路板及其制作方法 |
US11160163B2 (en) * | 2017-11-17 | 2021-10-26 | Texas Instruments Incorporated | Electronic substrate having differential coaxial vias |
US11818833B2 (en) * | 2021-11-15 | 2023-11-14 | Unimicron Technology Corp. | Circuit board structure |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6143116A (en) * | 1996-09-26 | 2000-11-07 | Kyocera Corporation | Process for producing a multi-layer wiring board |
US6623844B2 (en) * | 2001-02-26 | 2003-09-23 | Kyocera Corporation | Multi-layer wiring board and method of producing the same |
JP2002335057A (ja) | 2001-05-08 | 2002-11-22 | Hitachi Metals Ltd | メタルコア素材およびそれを用いているメタルコア、該メタルコアを用いているメタルコア基板 |
JP4430976B2 (ja) * | 2004-05-10 | 2010-03-10 | 富士通株式会社 | 配線基板及びその製造方法 |
US7683266B2 (en) * | 2005-07-29 | 2010-03-23 | Sanyo Electric Co., Ltd. | Circuit board and circuit apparatus using the same |
-
2005
- 2005-08-30 JP JP2005250369A patent/JP4467489B2/ja not_active Expired - Fee Related
-
2006
- 2006-08-29 US US11/511,496 patent/US7420126B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20070044999A1 (en) | 2007-03-01 |
US7420126B2 (en) | 2008-09-02 |
JP2007067120A (ja) | 2007-03-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4467489B2 (ja) | 回路基板およびそれを用いた回路装置 | |
US8166643B2 (en) | Method of manufacturing the circuit apparatus, method of manufacturing the circuit board, and method of manufacturing the circuit device | |
US8378229B2 (en) | Circuit board and method for manufacturing semiconductor modules and circuit boards | |
JP4503039B2 (ja) | 回路装置 | |
JP5265183B2 (ja) | 半導体装置 | |
JP5106460B2 (ja) | 半導体装置及びその製造方法、並びに電子装置 | |
JP4900624B2 (ja) | 回路装置 | |
JP4730426B2 (ja) | 実装基板及び半導体モジュール | |
JP2003258189A (ja) | 半導体装置及びその製造方法 | |
TW200839998A (en) | Semiconductor chip embedding structure | |
JP2009194322A (ja) | 半導体装置の製造方法、半導体装置及び配線基板 | |
JP2007180105A (ja) | 回路基板、回路基板を用いた回路装置、及び回路基板の製造方法 | |
JP2006310783A (ja) | 回路装置 | |
US20080274588A1 (en) | Semiconductor device and method of fabricating the same, circuit board, and electronic instrument | |
JP2006270065A (ja) | 回路装置 | |
JP2007158279A (ja) | 半導体装置及びそれを用いた電子制御装置 | |
JP2007324330A (ja) | 回路基板 | |
JP4534927B2 (ja) | 半導体装置 | |
JP2005353944A (ja) | 素子搭載基板 | |
JP4467540B2 (ja) | 回路装置 | |
WO2022004178A1 (ja) | インターポーザ、回路装置、インターポーザの製造方法、および回路装置の製造方法 | |
JP4155985B2 (ja) | 回路基板およびそれを用いた回路装置 | |
JP2008034762A (ja) | 回路装置 | |
JP2008060548A (ja) | 素子搭載用基板、素子搭載用基板の製造方法、および半導体モジュール | |
JP2007180122A (ja) | 回路装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080829 |
|
A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20090930 |
|
A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20091026 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091110 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091225 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100126 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100223 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130305 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140305 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |