JP4443190B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4443190B2
JP4443190B2 JP2003371771A JP2003371771A JP4443190B2 JP 4443190 B2 JP4443190 B2 JP 4443190B2 JP 2003371771 A JP2003371771 A JP 2003371771A JP 2003371771 A JP2003371771 A JP 2003371771A JP 4443190 B2 JP4443190 B2 JP 4443190B2
Authority
JP
Japan
Prior art keywords
conductive
conductive path
semiconductor device
insulating resin
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003371771A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004048077A5 (hr
JP2004048077A (ja
Inventor
則明 坂本
義幸 小林
純次 阪本
茂明 真下
克実 大川
栄寿 前原
幸嗣 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2003371771A priority Critical patent/JP4443190B2/ja
Publication of JP2004048077A publication Critical patent/JP2004048077A/ja
Publication of JP2004048077A5 publication Critical patent/JP2004048077A5/ja
Application granted granted Critical
Publication of JP4443190B2 publication Critical patent/JP4443190B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Lead Frames For Integrated Circuits (AREA)
JP2003371771A 2003-10-31 2003-10-31 半導体装置の製造方法 Expired - Fee Related JP4443190B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003371771A JP4443190B2 (ja) 2003-10-31 2003-10-31 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003371771A JP4443190B2 (ja) 2003-10-31 2003-10-31 半導体装置の製造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2000088831A Division JP3510839B2 (ja) 2000-03-28 2000-03-28 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2004048077A JP2004048077A (ja) 2004-02-12
JP2004048077A5 JP2004048077A5 (hr) 2007-03-22
JP4443190B2 true JP4443190B2 (ja) 2010-03-31

Family

ID=31712928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003371771A Expired - Fee Related JP4443190B2 (ja) 2003-10-31 2003-10-31 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP4443190B2 (hr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100773482B1 (ko) 2006-10-09 2007-11-05 서동관 주입구가 구비된 포장백의 제조방법
KR100764684B1 (ko) 2006-11-01 2007-10-08 인티그런트 테크놀로지즈(주) 반도체 패키지 제조방법, 반도체 장치 및 그 제조방법

Also Published As

Publication number Publication date
JP2004048077A (ja) 2004-02-12

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