JP4443190B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4443190B2 JP4443190B2 JP2003371771A JP2003371771A JP4443190B2 JP 4443190 B2 JP4443190 B2 JP 4443190B2 JP 2003371771 A JP2003371771 A JP 2003371771A JP 2003371771 A JP2003371771 A JP 2003371771A JP 4443190 B2 JP4443190 B2 JP 4443190B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- conductive path
- semiconductor device
- insulating resin
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003371771A JP4443190B2 (ja) | 2003-10-31 | 2003-10-31 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003371771A JP4443190B2 (ja) | 2003-10-31 | 2003-10-31 | 半導体装置の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000088831A Division JP3510839B2 (ja) | 2000-03-28 | 2000-03-28 | 半導体装置およびその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2004048077A JP2004048077A (ja) | 2004-02-12 |
JP2004048077A5 JP2004048077A5 (hr) | 2007-03-22 |
JP4443190B2 true JP4443190B2 (ja) | 2010-03-31 |
Family
ID=31712928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003371771A Expired - Fee Related JP4443190B2 (ja) | 2003-10-31 | 2003-10-31 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4443190B2 (hr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100773482B1 (ko) | 2006-10-09 | 2007-11-05 | 서동관 | 주입구가 구비된 포장백의 제조방법 |
KR100764684B1 (ko) | 2006-11-01 | 2007-10-08 | 인티그런트 테크놀로지즈(주) | 반도체 패키지 제조방법, 반도체 장치 및 그 제조방법 |
-
2003
- 2003-10-31 JP JP2003371771A patent/JP4443190B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2004048077A (ja) | 2004-02-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100386520B1 (ko) | 회로 장치의 제조 방법 및 회로 장치 | |
KR100509136B1 (ko) | 회로 장치 및 그 제조 방법 | |
JP3639514B2 (ja) | 回路装置の製造方法 | |
JP3609684B2 (ja) | 半導体装置およびその製造方法 | |
JP3574026B2 (ja) | 回路装置およびその製造方法 | |
JP3561683B2 (ja) | 回路装置の製造方法 | |
JP2001217372A (ja) | 回路装置およびその製造方法 | |
JP3691335B2 (ja) | 回路装置の製造方法 | |
JP3634709B2 (ja) | 半導体モジュール | |
JP3574025B2 (ja) | 回路装置およびその製造方法 | |
JP3510839B2 (ja) | 半導体装置およびその製造方法 | |
JP3668090B2 (ja) | 実装基板およびそれを用いた回路モジュール | |
JP4443190B2 (ja) | 半導体装置の製造方法 | |
JP2001250884A (ja) | 回路装置の製造方法 | |
JP4036603B2 (ja) | 半導体装置およびその製造方法 | |
JP4698080B2 (ja) | 回路装置の製造方法 | |
JP2005175509A (ja) | 回路装置 | |
JP3691328B2 (ja) | 回路装置および回路モジュール | |
JP3639495B2 (ja) | 回路装置の製造方法 | |
JP3778783B2 (ja) | 回路装置およびその製造方法 | |
JP3869633B2 (ja) | 半導体装置の製造方法 | |
JP2001250883A (ja) | 回路装置の製造方法 | |
JP4748892B2 (ja) | 回路装置の製造方法 | |
JP2005150767A (ja) | 回路装置 | |
JP2001223318A (ja) | 回路装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070201 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070202 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070202 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090728 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090925 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20091215 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100112 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130122 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |