JP4430606B2 - 抵抗性メモリ素子 - Google Patents
抵抗性メモリ素子 Download PDFInfo
- Publication number
- JP4430606B2 JP4430606B2 JP2005319041A JP2005319041A JP4430606B2 JP 4430606 B2 JP4430606 B2 JP 4430606B2 JP 2005319041 A JP2005319041 A JP 2005319041A JP 2005319041 A JP2005319041 A JP 2005319041A JP 4430606 B2 JP4430606 B2 JP 4430606B2
- Authority
- JP
- Japan
- Prior art keywords
- resistive
- region
- probe
- layer
- ferroelectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000523 sample Substances 0.000 claims description 144
- 239000012535 impurity Substances 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- 230000010287 polarization Effects 0.000 claims description 20
- 229920000642 polymer Polymers 0.000 claims description 16
- 230000008878 coupling Effects 0.000 claims description 14
- 238000010168 coupling process Methods 0.000 claims description 14
- 238000005859 coupling reaction Methods 0.000 claims description 14
- 239000002245 particle Substances 0.000 claims description 4
- 239000004840 adhesive resin Substances 0.000 claims description 3
- 229920006223 adhesive resin Polymers 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 167
- 238000004519 manufacturing process Methods 0.000 description 20
- 238000000034 method Methods 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 12
- 230000005684 electric field Effects 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000005283 ground state Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000007523 nucleic acids Chemical group 0.000 description 1
- 102000039446 nucleic acids Human genes 0.000 description 1
- 108020004707 nucleic acids Proteins 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B9/00—Recording or reproducing using a method not covered by one of the main groups G11B3/00 - G11B7/00; Record carriers therefor
- G11B9/02—Recording or reproducing using a method not covered by one of the main groups G11B3/00 - G11B7/00; Record carriers therefor using ferroelectric record carriers; Record carriers therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Semiconductor Memories (AREA)
- Measuring Leads Or Probes (AREA)
Description
本発明の他の目的は、強誘電層をメモリ層として利用し、このようなメモリ層に抵抗性探針を対応させて、抵抗性探針を利用してメモリ層への記録および再生を具現する抵抗性メモリ素子を提供するところにある。
図2は、本発明の実施形態に係る抵抗性メモリ素子のセル構造を説明するための概略図である。図3は、本発明の実施形態に係る抵抗性メモリ素子のセルへのデータ記録を説明するための概略図である。図4は、本発明の実施形態に係る抵抗性メモリ素子のセルへのデータ再生を説明するための概略図である。
したがって、携帯電子製品の環境に適するように、高密度の記録および再生が可能であり、相対的に高い耐衝撃性および耐摩耗性を備える抵抗性メモリ素子およびその製造方法を提供することができる。
また、強誘電層をメモリ層として利用し、このようなメモリ層に抵抗性探針を対応させて、抵抗性探針を利用してメモリ層への記録および再生を具現する抵抗性メモリ素子を提供する。
20 探針部
30 メモリセル
100 底電極層
101 第1基板
200 強誘電層
300 第2基板
400 抵抗性探針
401 本体
404 抵抗領域
403,405 電極領域
407,409 端子
500 結合層
Claims (7)
- 第1基板および第2基板と、
前記第1基板上に形成された底電極層および強誘電層を備えるメモリ部と、
前記第2基板上に固定され、前記強誘電層と対向するようにチップ部分が設けられた、前記強誘電層へのデータの記録および再生のための抵抗性探針を備える探針部と、
前記抵抗性探針を前記強誘電層上につかんで固定させる結合層と、
を備え、
前記抵抗性探針は、
前記チップ部分に位置し、前記チップ部分に対応する前記強誘電層のドメインの残留分極の方向により抵抗が変化する抵抗領域と、
前記抵抗領域を挟んで互いに離れた傾斜面にそれぞれ位置して、前記データの再生時に、前記抵抗領域の抵抗値を検出するのに使用される第1電極領域および第2電極領域と、
を備え、
前記抵抗領域は前記抵抗性探針を前記強誘電層上につかんで固定させるために前記結合層中に配置され、
前記第1電極領域および前記第2電極領域は前記結合層中に配置されず、
前記結合層は、強誘電層を、電荷粒子および大気中の湿気から絶縁および保護するポリマーおよび接着レジンのうちの一つを有することを特徴とする抵抗性メモリ素子。 - 前記抵抗性探針は、第1不純物がドーピングされたシリコンを備える円錐形、四角錘形または多角錘形の本体を有し、
前記第1電極領域および前記第2電極領域は、前記本体の互いに離れた傾斜面に、前記第1不純物とは逆の導電型の第2不純物がドーピングされた領域を備えることを特徴とする請求項1に記載の抵抗性メモリ素子。 - 前記抵抗性探針の前記抵抗領域は、前記第1電極領域および前記第2電極領域に比べて低濃度で前記第2不純物がドーピングされた領域を備えることを特徴とする請求項1または請求項2に記載の抵抗性メモリ素子。
- 前記探針部は、前記抵抗性探針のアレイの後端側に、前記何れか一つの抵抗性探針を選択し、選択された前記抵抗性探針に電圧を印加するための端子として、前記抵抗性探針の前記第1電極領域および前記第2電極領域にそれぞれ連結される配線を更に備えることを特徴とする請求項1から請求項3のいずれか1項に記載の抵抗性メモリ素子。
- 前記探針部は、前記抵抗性探針のアレイの後端側に、前記抵抗性探針の前記第1電極領域および前記第2電極領域にそれぞれ連結されるビットラインと、
前記ビットラインへの電流印加を制御する選択トランジスタと、
を更に備えることを特徴とする請求項1から請求項4のいずれか1項に記載の抵抗性メモリ素子。 - 前記結合層は、ポリマー層を含んでなることを特徴とする請求項1から請求項5のいずれか1項に記載の抵抗性メモリ素子。
- 第1基板および第2基板と、
前記第1基板上に形成された底電極層および強誘電層を備えるメモリ部と、
前記第2基板上に固定され、前記強誘電層と対向するようにチップ部分が設けられた、前記強誘電層へのデータ記録および再生のための抵抗性探針と、を備え、
前記抵抗性探針は、第1不純物がドーピングされたシリコンを備える円錐形または多角錘形の本体を有し、
前記抵抗性探針のチップ部分に位置して、前記チップ部分に対応する前記強誘電層のドメインへの残留分極の方向により抵抗が変化する抵抗領域、および前記抵抗領域を挟んで互いに離れた前記本体の傾斜面にそれぞれ位置して、前記データの再生時に、前記抵抗領域の抵抗値を検出するのに使用される第1電極領域および第2電極領域を備え、
前記抵抗領域は、前記第1電極領域および第2電極領域に比べて、低濃度で前記第2不純物がドーピングされた領域を備え、
前記抵抗性探針のアレイの後端側に、前記何れか一つの抵抗性探針を選択し、選択された前記抵抗性探針に電流を提供するための端子として、前記抵抗性探針の前記第1電極領域および第2電極領域にそれぞれ連結されるビットライン、および前記ビットラインへの電流印加を制御する選択トランジスタを備える探針部と
前記抵抗性探針を前記強誘電層上につかんで固定させる結合層と、
を備え、
前記抵抗領域は前記抵抗性探針を前記強誘電層上につかんで固定させるために前記結合層中に配置され、
前記第1電極領域および前記第2電極領域は前記結合層中に配置されず、
前記結合層は、強誘電層を、電荷粒子および大気中の湿気から絶縁および保護するポリマーおよび接着レジンのうちの一つを有することを特徴とする抵抗性メモリ素子。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040088163A KR100612867B1 (ko) | 2004-11-02 | 2004-11-02 | 탐침 어레이를 가지는 저항성 메모리 소자 및 그 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006135326A JP2006135326A (ja) | 2006-05-25 |
JP4430606B2 true JP4430606B2 (ja) | 2010-03-10 |
Family
ID=35705214
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005319041A Expired - Fee Related JP4430606B2 (ja) | 2004-11-02 | 2005-11-02 | 抵抗性メモリ素子 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7687838B2 (ja) |
EP (1) | EP1653473B1 (ja) |
JP (1) | JP4430606B2 (ja) |
KR (1) | KR100612867B1 (ja) |
CN (1) | CN1770456A (ja) |
DE (1) | DE602005012472D1 (ja) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4356997B2 (ja) * | 2005-03-15 | 2009-11-04 | キヤノン株式会社 | 通信装置及びその通信方法 |
NO20052904L (no) | 2005-06-14 | 2006-12-15 | Thin Film Electronics Asa | Et ikke-flyktig elektrisk minnesystem |
JP4476919B2 (ja) | 2005-12-01 | 2010-06-09 | 株式会社東芝 | 不揮発性記憶装置 |
KR100909962B1 (ko) | 2006-05-10 | 2009-07-29 | 삼성전자주식회사 | 전계 정보 재생 헤드, 전계 정보 기록/재생헤드 및 그제조방법과 이를 채용한 정보저장장치 |
US20070121477A1 (en) * | 2006-06-15 | 2007-05-31 | Nanochip, Inc. | Cantilever with control of vertical and lateral position of contact probe tip |
US20080074792A1 (en) * | 2006-09-21 | 2008-03-27 | Nanochip, Inc. | Control scheme for a memory device |
US20080074984A1 (en) * | 2006-09-21 | 2008-03-27 | Nanochip, Inc. | Architecture for a Memory Device |
DE102007013063A1 (de) | 2007-03-19 | 2008-10-09 | Qimonda Ag | Vorrichtung und Verfahren zur elektrischen Kontakierung von Halbleiter-Bauelementen zu Testzwecken |
US20080232228A1 (en) * | 2007-03-20 | 2008-09-25 | Nanochip, Inc. | Systems and methods of writing and reading a ferro-electric media with a probe tip |
US20080316897A1 (en) * | 2007-06-19 | 2008-12-25 | Nanochip, Inc. | Methods of treating a surface of a ferroelectric media |
US20080318086A1 (en) * | 2007-06-19 | 2008-12-25 | Nanochip, Inc. | Surface-treated ferroelectric media for use in systems for storing information |
US7626846B2 (en) * | 2007-07-16 | 2009-12-01 | Nanochip, Inc. | Method and media for improving ferroelectric domain stability in an information storage device |
US20090201015A1 (en) * | 2008-02-12 | 2009-08-13 | Nanochip, Inc. | Method and device for detecting ferroelectric polarization |
US20090213492A1 (en) * | 2008-02-22 | 2009-08-27 | Nanochip, Inc. | Method of improving stability of domain polarization in ferroelectric thin films |
US20100002563A1 (en) * | 2008-07-01 | 2010-01-07 | Nanochip, Inc. | Media with tetragonally-strained recording layer having improved surface roughness |
US20100085863A1 (en) * | 2008-10-07 | 2010-04-08 | Nanochip, Inc. | Retuning of ferroelectric media built-in-bias |
US8035274B2 (en) * | 2009-05-14 | 2011-10-11 | The Neothermal Energy Company | Apparatus and method for ferroelectric conversion of heat to electrical energy |
CN102157688B (zh) * | 2011-03-23 | 2012-07-18 | 北京大学 | 一种阻变存储器及其制备方法 |
US9444040B2 (en) | 2013-03-13 | 2016-09-13 | Microchip Technology Incorporated | Sidewall type memory cell |
US9385313B2 (en) * | 2014-02-19 | 2016-07-05 | Microchip Technology Incorporated | Resistive memory cell having a reduced conductive path area |
US11043634B2 (en) | 2019-04-09 | 2021-06-22 | International Business Machines Corporation | Confining filament at pillar center for memory devices |
US11903218B2 (en) | 2020-06-26 | 2024-02-13 | Sandisk Technologies Llc | Bonded memory devices and methods of making the same |
KR20220088472A (ko) * | 2020-06-26 | 2022-06-27 | 샌디스크 테크놀로지스 엘엘씨 | 접합된 메모리 디바이스 및 그 제조 방법 |
US11538817B2 (en) * | 2020-06-26 | 2022-12-27 | Sandisk Technologies Llc | Bonded memory devices and methods of making the same |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5357481A (en) * | 1976-11-04 | 1978-05-24 | Canon Inc | Connecting process |
US5519234A (en) * | 1991-02-25 | 1996-05-21 | Symetrix Corporation | Ferroelectric dielectric memory cell can switch at least giga cycles and has low fatigue - has high dielectric constant and low leakage current |
US5146299A (en) * | 1990-03-02 | 1992-09-08 | Westinghouse Electric Corp. | Ferroelectric thin film material, method of deposition, and devices using same |
US5468684A (en) * | 1991-12-13 | 1995-11-21 | Symetrix Corporation | Integrated circuit with layered superlattice material and method of fabricating same |
US5719416A (en) * | 1991-12-13 | 1998-02-17 | Symetrix Corporation | Integrated circuit with layered superlattice material compound |
US6373743B1 (en) * | 1999-08-30 | 2002-04-16 | Symetrix Corporation | Ferroelectric memory and method of operating same |
JPH09503622A (ja) | 1993-09-30 | 1997-04-08 | コピン・コーポレーシヨン | 転写薄膜回路を使用した3次元プロセッサー |
JPH10105243A (ja) * | 1996-09-10 | 1998-04-24 | Hewlett Packard Co <Hp> | 位置決め機構、位置決め装置及び情報記録装置 |
US6025618A (en) * | 1996-11-12 | 2000-02-15 | Chen; Zhi Quan | Two-parts ferroelectric RAM |
KR100253352B1 (ko) | 1997-11-19 | 2000-04-15 | 김영환 | 적층가능한 반도체 칩 및 적층된 반도체 칩 모듈의 제조 방법 |
KR19990070783A (ko) * | 1998-02-24 | 1999-09-15 | 윤종용 | 강유전체를 이용한 고밀도 데이터 저장 장치 |
KR100277976B1 (ko) | 1998-07-02 | 2001-03-02 | 구자홍 | 강유전체 비휘발성 메모리의 정보 기록 및 재생방법 |
JP3332014B2 (ja) | 1999-07-01 | 2002-10-07 | セイコーエプソン株式会社 | 半導体記憶装置の製造方法 |
US6337805B1 (en) * | 1999-08-30 | 2002-01-08 | Micron Technology, Inc. | Discrete devices including EAPROM transistor and NVRAM memory cell with edge defined ferroelectric capacitance, methods for operating same, and apparatuses including same |
JP3939250B2 (ja) * | 2001-05-10 | 2007-07-04 | シメトリックス・コーポレーション | 強誘電性複合材料、その製造方法、およびそれを用いたメモリ |
JP3967237B2 (ja) | 2001-09-19 | 2007-08-29 | 株式会社東芝 | 磁気抵抗効果素子及びその製造方法、磁気再生素子並びに磁気メモリ |
KR100468850B1 (ko) | 2002-05-08 | 2005-01-29 | 삼성전자주식회사 | 저항성 팁을 구비하는 반도체 탐침 및 그 제조방법 및 이를 구비하는 정보 기록장치, 정보재생장치 및 정보측정장치 |
NO322192B1 (no) * | 2002-06-18 | 2006-08-28 | Thin Film Electronics Asa | Fremgangsmate til fremstilling av elektrodelag av ferroelektriske minneceller i en ferroelektrisk minneinnretning, samt ferroelektrisk minneinnretning |
JP3791614B2 (ja) * | 2002-10-24 | 2006-06-28 | セイコーエプソン株式会社 | 強誘電体膜、強誘電体メモリ装置、圧電素子、半導体素子、圧電アクチュエータ、液体噴射ヘッド及びプリンタ |
EP1439546A1 (en) * | 2003-01-16 | 2004-07-21 | Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. | A nanotube based cantilever arm, a method of operating and manufacturing a nanotube based cantilever arm, and a storage device and a photonic crystal based on an array of nanotube based cantilever arms |
JP2004319651A (ja) * | 2003-04-14 | 2004-11-11 | Seiko Epson Corp | メモリの素子及びその製造方法 |
US6841396B2 (en) * | 2003-05-19 | 2005-01-11 | Texas Instruments Incorporated | VIA0 etch process for FRAM integration |
US7291878B2 (en) * | 2003-06-03 | 2007-11-06 | Hitachi Global Storage Technologies Netherlands B.V. | Ultra low-cost solid-state memory |
US7391706B2 (en) * | 2003-10-31 | 2008-06-24 | Samsung Electronics Co., Ltd. | Data storage device including conductive probe and ferroelectric storage medium |
US20050145908A1 (en) * | 2003-12-30 | 2005-07-07 | Moise Theodore S.Iv | High polarization ferroelectric capacitors for integrated circuits |
US7173842B2 (en) * | 2004-03-31 | 2007-02-06 | Intel Corporation | Metal heater for in situ heating and crystallization of ferroelectric polymer memory film |
-
2004
- 2004-11-02 KR KR1020040088163A patent/KR100612867B1/ko not_active IP Right Cessation
-
2005
- 2005-08-16 EP EP05255059A patent/EP1653473B1/en not_active Expired - Fee Related
- 2005-08-16 DE DE602005012472T patent/DE602005012472D1/de active Active
- 2005-08-19 CN CNA2005100921197A patent/CN1770456A/zh active Pending
- 2005-10-03 US US11/240,570 patent/US7687838B2/en not_active Expired - Fee Related
- 2005-11-02 JP JP2005319041A patent/JP4430606B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20060091437A1 (en) | 2006-05-04 |
KR100612867B1 (ko) | 2006-08-14 |
KR20060039109A (ko) | 2006-05-08 |
EP1653473A2 (en) | 2006-05-03 |
JP2006135326A (ja) | 2006-05-25 |
CN1770456A (zh) | 2006-05-10 |
DE602005012472D1 (de) | 2009-03-12 |
EP1653473B1 (en) | 2009-01-21 |
US7687838B2 (en) | 2010-03-30 |
EP1653473A3 (en) | 2007-04-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4430606B2 (ja) | 抵抗性メモリ素子 | |
US8896070B2 (en) | Patterning embedded control lines for vertically stacked semiconductor elements | |
US5940705A (en) | Methods of forming floating-gate FFRAM devices | |
KR100707181B1 (ko) | 듀얼 스토리지 노드를 구비하는 반도체 메모리 장치와 그제조 및 동작 방법 | |
US8617952B2 (en) | Vertical transistor with hardening implatation | |
US20130302948A1 (en) | 3d array with vertical transistor | |
US6541792B1 (en) | Memory device having dual tunnel junction memory cells | |
JP4373647B2 (ja) | 強誘電体不揮発性記憶装置及びその駆動方法 | |
JP5566981B2 (ja) | 縦型トランジスタstramアレイ | |
WO2007102341A1 (ja) | 抵抗変化型素子、半導体装置、およびその製造方法 | |
US20020173111A1 (en) | Semiconductor memory device with memory cells having same characteristics and manufacturing method for the same | |
US7413913B2 (en) | Semiconductor device and method of manufacturing the same | |
US8537605B2 (en) | Nonvolatile semiconductor memory device having coplanar surfaces at resistance variable layer and wiring layer and manufacturing method thereof | |
US7629635B2 (en) | Semiconductor memory and driving method for the same | |
US7554151B2 (en) | Low voltage non-volatile memory cell with electrically transparent control gate | |
JP3226989B2 (ja) | 強誘電体メモリ | |
JP2937254B2 (ja) | 強誘電体メモリの修復方法 | |
RU2668716C2 (ru) | Сегнетоэлектрический элемент памяти и сумматор | |
EP0537791A1 (en) | Semiconductor memory | |
JPH1197559A (ja) | 強誘電体メモリセル、その駆動方法及びメモリ装置 | |
KR20090054685A (ko) | 비휘발성 메모리 장치 | |
KR19990015720A (ko) | 비파괴 읽기 박막 트랜지스터 강유전체 메모리 및그 구동방법 | |
JP2008198771A (ja) | 不揮発性半導体記憶装置及びその製造方法 | |
KR19990019531A (ko) | 비파괴 읽기 강유전체 메모리 단위셀 구조체 및 그 제조 방법과 구동 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20061102 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20061106 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080115 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090721 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091021 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20091124 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091217 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121225 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121225 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131225 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |