JP4422411B2 - ダイ支持を有するマイクロエレクトロニック・アセンブリを形成する方法 - Google Patents
ダイ支持を有するマイクロエレクトロニック・アセンブリを形成する方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 21
- 238000004377 microelectronic Methods 0.000 title claims description 19
- 239000000463 material Substances 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 44
- 229910000679 solder Inorganic materials 0.000 claims description 30
- 239000012704 polymeric precursor Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229920000642 polymer Polymers 0.000 claims description 6
- 239000002243 precursor Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 3
- 238000007789 sealing Methods 0.000 claims 1
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- 235000012431 wafers Nutrition 0.000 description 12
- 239000000945 filler Substances 0.000 description 9
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
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- WYTZZXDRDKSJID-UHFFFAOYSA-N (3-aminopropyl)triethoxysilane Chemical group CCO[Si](OCC)(OCC)CCCN WYTZZXDRDKSJID-UHFFFAOYSA-N 0.000 description 1
- ZCUJYXPAKHMBAZ-UHFFFAOYSA-N 2-phenyl-1h-imidazole Chemical group C1=CNC(C=2C=CC=CC=2)=N1 ZCUJYXPAKHMBAZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- FZHAPNGMFPVSLP-UHFFFAOYSA-N silanamine Chemical group [SiH3]N FZHAPNGMFPVSLP-UHFFFAOYSA-N 0.000 description 1
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- General Physics & Mathematics (AREA)
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- Wire Bonding (AREA)
Description
と接続部との破損の可能性を減少させる。しかしながら、これらの方法は追加の製造工程、材料、および装置を必要とする。ある場合には、ダイの封入自身がダイに応力を及ぼし、マーキング法に不利であり、ダイの熱放散能力を減ずることによって、ダイの有効動作寿命を短縮する。
ここで述べる好ましい実施例の説明は、開示された正確な形式に本発明の範囲を制限する意図はなく、説明を理解できるように本発明の理論を説明するためである。
ェニリミダゾールである。他の適切な触媒はアミン、酸、および無水物である。
接着促進剤はアミノシランである。基板との濡れを改善して封入剤の接着を促進する。好ましい接着促進剤はガンマ−アミノプロピルトリエトキシシランである。他の適切な接着促進剤はフルオロポリマとシリコーンである。
Claims (5)
- マイクロエレクトロニク・アセンブリを形成する方法であって、
複数のボンドパッドを有する基板を作製する工程と、
面上に複数のはんだバンプを有するダイ面を有する集積回路ダイ部品を作製する工程と、
該ダイの外縁周辺に、高分子前駆体材料を配置する工程と、
各はんだバンプが、複数のボンドパッドの対応するパッドと接触して、ダイ面と基板とがギャップによって離間されるべく、基板上にダイ面を重ね合わせる工程と、
該はんだバンプをリフローするのに十分な温度にダイと基板とを加熱して、対応する該ボンドパッドにはんだ接続を形成し、かつ、該高分子前駆体材料を基板上に流動させ硬化させる工程と、
からなる方法。 - マイクロエレクトロニク・アセンブリを形成する方法であって、
複数のボンドパッドを有する基板を作製する工程と、
面上に複数のはんだバンプを有するダイ面を有する集積回路ダイ部品を作製する工程と、
ダイの外縁周辺に、該はんだ材料の融点以下で流動するのに適合した高分子前駆体材料を配置する工程と、
各はんだバンプが、複数のボンドパッドの対応するパッドと接触して、ダイ面と基板とがギャップによって離間されるべく、基板上にダイ面を重ね合わせる工程と、
はんだバンプをリフローするのに十分な温度にダイと基板とを加熱して、対応するボンドパッドに接続し、同時に、該高分子前駆体材料をギャップ中に流動させ、硬化させて封止し、同封止がボンドパッドとはんだバンプとの間の接続を保護する工程と、
からなる方法。 - マイクロエレクトロニク・アセンブリを形成する方法であって、
ウエハ面を有する半導体ウエハを作製する工程であって、該ウエハ面はその上に少なくとも1つの集積回路ダイ部品を有し、該各ダイ部品はダイ面上に複数のはんだバンプを有することと、
該ウエハ面が接着支持材料から外側に向くように、該半導体ウエハを接着支持材料上に配置する工程と、
該各ダイ部品の周囲に道を形成する工程と、
高分子前駆体材料で道を充填する工程と、
高分子前駆体材料が各ダイ部品の外縁周辺に配置されるように、道を再切断して個々のダイに分離する工程と、
複数のボンドパッドを有する基板を作製する工程と、
基板上にダイ面を重ね合わせる工程であって、各はんだバンプが、複数のボンドパッドの対応するパッドと接触することと、
はんだバンプをリフローするのに十分な温度に、ダイ部品と基板を加熱して、対応するボンドパッドにはんだ接続をし、該高分子前駆体材料を基板上に流動させ硬化させる工程と、
からなる方法。 - ダイ部品が分離される前に、前記高分子前駆体材料が部分硬化される請求項3に記載のマイクロエレクトロニック・アセンブリを形成する方法。
- 前記高分子前駆体材料が、はんだリフロー温度で硬化されるべく適応された請求項3に記載のマイクロエレクトロニック・アセンブリを形成する方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/819,393 US6562663B2 (en) | 2001-03-28 | 2001-03-28 | Microelectronic assembly with die support and method |
PCT/US2002/005431 WO2002080229A2 (en) | 2001-03-28 | 2002-02-22 | Microelectronic assembly with die support and method |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2004524703A JP2004524703A (ja) | 2004-08-12 |
JP2004524703A5 JP2004524703A5 (ja) | 2005-12-22 |
JP4422411B2 true JP4422411B2 (ja) | 2010-02-24 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002578545A Expired - Fee Related JP4422411B2 (ja) | 2001-03-28 | 2002-02-22 | ダイ支持を有するマイクロエレクトロニック・アセンブリを形成する方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US6562663B2 (ja) |
EP (1) | EP1504468A4 (ja) |
JP (1) | JP4422411B2 (ja) |
WO (1) | WO2002080229A2 (ja) |
Families Citing this family (13)
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US6352881B1 (en) * | 1999-07-22 | 2002-03-05 | National Semiconductor Corporation | Method and apparatus for forming an underfill adhesive layer |
JP4403631B2 (ja) * | 2000-04-24 | 2010-01-27 | ソニー株式会社 | チップ状電子部品の製造方法、並びにその製造に用いる擬似ウエーハの製造方法 |
JP2001313350A (ja) * | 2000-04-28 | 2001-11-09 | Sony Corp | チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法 |
US7423337B1 (en) | 2002-08-19 | 2008-09-09 | National Semiconductor Corporation | Integrated circuit device package having a support coating for improved reliability during temperature cycling |
US7115998B2 (en) * | 2002-08-29 | 2006-10-03 | Micron Technology, Inc. | Multi-component integrated circuit contacts |
US7301222B1 (en) | 2003-02-12 | 2007-11-27 | National Semiconductor Corporation | Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages |
TW594955B (en) * | 2003-06-30 | 2004-06-21 | Advanced Semiconductor Eng | Flip chip package process |
US7282375B1 (en) | 2004-04-14 | 2007-10-16 | National Semiconductor Corporation | Wafer level package design that facilitates trimming and testing |
JP5197175B2 (ja) * | 2008-06-16 | 2013-05-15 | キヤノン株式会社 | インクジェット記録ヘッドおよびその製造方法 |
US20110108997A1 (en) * | 2009-04-24 | 2011-05-12 | Panasonic Corporation | Mounting method and mounting structure for semiconductor package component |
US9691734B1 (en) * | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
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- 2002-02-22 WO PCT/US2002/005431 patent/WO2002080229A2/en active Application Filing
- 2002-02-22 JP JP2002578545A patent/JP4422411B2/ja not_active Expired - Fee Related
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2003
- 2003-04-02 US US10/405,383 patent/US20040002181A1/en not_active Abandoned
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WO2002080229A2 (en) | 2002-10-10 |
JP2004524703A (ja) | 2004-08-12 |
US20020142514A1 (en) | 2002-10-03 |
EP1504468A4 (en) | 2005-05-25 |
WO2002080229A3 (en) | 2003-04-17 |
US6562663B2 (en) | 2003-05-13 |
EP1504468A2 (en) | 2005-02-09 |
US20040002181A1 (en) | 2004-01-01 |
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