JP4373291B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4373291B2
JP4373291B2 JP2004185884A JP2004185884A JP4373291B2 JP 4373291 B2 JP4373291 B2 JP 4373291B2 JP 2004185884 A JP2004185884 A JP 2004185884A JP 2004185884 A JP2004185884 A JP 2004185884A JP 4373291 B2 JP4373291 B2 JP 4373291B2
Authority
JP
Japan
Prior art keywords
mold
cleaning
sheet
resin
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004185884A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006007506A5 (https=
JP2006007506A (ja
Inventor
清 土田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2004185884A priority Critical patent/JP4373291B2/ja
Publication of JP2006007506A publication Critical patent/JP2006007506A/ja
Publication of JP2006007506A5 publication Critical patent/JP2006007506A5/ja
Application granted granted Critical
Publication of JP4373291B2 publication Critical patent/JP4373291B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Moulds For Moulding Plastics Or The Like (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2004185884A 2004-06-24 2004-06-24 半導体装置の製造方法 Expired - Fee Related JP4373291B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004185884A JP4373291B2 (ja) 2004-06-24 2004-06-24 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004185884A JP4373291B2 (ja) 2004-06-24 2004-06-24 半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009163477A Division JP2009283955A (ja) 2009-07-10 2009-07-10 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2006007506A JP2006007506A (ja) 2006-01-12
JP2006007506A5 JP2006007506A5 (https=) 2009-06-04
JP4373291B2 true JP4373291B2 (ja) 2009-11-25

Family

ID=35775284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004185884A Expired - Fee Related JP4373291B2 (ja) 2004-06-24 2004-06-24 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP4373291B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101450152B1 (ko) 2014-03-27 2014-10-13 임상수 전자제품의 국부적 방수 구조의 형성방법

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242924A (ja) * 2006-03-09 2007-09-20 Renesas Technology Corp 半導体装置の製造方法
KR100884733B1 (ko) * 2007-07-31 2009-02-19 이교안 칩 패키징 금형에 에폭시 릴리즈 왁스를 도포하기 위한 방법 및 이에 적합한 도포 시트
CN102292406B (zh) * 2009-02-13 2013-07-03 李教安 用于模具的蜡涂覆构件及使用该构件的蜡涂覆方法
JP5741398B2 (ja) * 2011-11-21 2015-07-01 日立化成株式会社 金型クリーニングシート
JP7318927B2 (ja) * 2019-11-15 2023-08-01 東北物流株式会社 クリーニング用シート、半導体装置の製造方法およびクリーニング用シートの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101450152B1 (ko) 2014-03-27 2014-10-13 임상수 전자제품의 국부적 방수 구조의 형성방법

Also Published As

Publication number Publication date
JP2006007506A (ja) 2006-01-12

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