JP4334589B2 - 半導体装置、およびその製造方法 - Google Patents
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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Description
(半導体装置の構成)
図1は、本発明の第1の実施の形態に係る半導体装置の有する所定の配線層の平面図である。また、図2は、図1の破線A−Aにおける半導体装置の断面図である。
図3A(a)〜(b)、図3B(c)〜(d)は、本発明の第1の実施の形態に係る半導体装置の製造方法を表す断面図である。
本発明の第1の実施の形態によれば、エアギャップ15をメタルリング13に囲まれた領域にのみ形成し、エアギャップ領域14と非エアギャップ領域16を作り分けることができる。これにより、エアギャップ15の必要ない領域(配線間容量の低減を強く求めない領域)の機械的強度を保ち、半導体装置10全体の機械的強度の低下を抑えることができる。
本発明の第2の実施の形態は、半導体装置10の製造方法において第1の実施の形態と異なる。半導体装置10の構成等、第1の実施の形態と同様の点については説明を省略する。
本発明の第2の実施の形態によれば、1つの配線層を形成する毎にエアギャップ15を形成するため、反応物排出孔23が上層の配線層により塞がれ、蓋材24を用いる必要がない。
本発明の第3の実施の形態は、配線12およびビア21からなる配線構造の構成において第1の実施の形態と異なる。他の部材の構成等、第1の実施の形態と同様の点については説明を省略する。
本発明の第3の実施の形態によれば、配線12およびビア21の側面に保護膜26が形成されるため、エアギャップ形成時やエアギャップ形成後における配線12およびビア21の酸化や、その他の化学変化に対する耐性が向上する。
本発明の第4の実施の形態は、メタルリング13の内側に別のメタルリング13aが形成される点において第1の実施の形態と異なる。他の部材の構成等、第1の実施の形態と同様の点については説明を省略する。
本発明の第4の実施の形態によれば、メタルリング13の内側の領域において配線間容量の低減の必要性の少ない領域が存在する等の場合、その領域にメタルリング13aを形成することにより、メタルリング13aをエアギャップ領域14の機械的強度を保持する柱として用いることができる。なお、機械的強度の保持にメタルリング13aを用いる場合、メタルダミーパターンを用いて機械的強度の保持を図る場合と比べて、メタル部分の面積が小さいため、特に上下の配線層の配線間における電気容量の増加を抑えることができる。
本発明の第5の実施の形態は、任意の配線層の任意の領域にエアギャップを形成する点において第1の実施の形態と異なる。他の部材の構成等、第1の実施の形態と同様の点については説明を省略する。
図7は、本発明の第5の実施の形態に係る半導体装置の有する所定の配線層の平面図である。また、図8は、図7の破線B−Bにおける半導体装置の断面図であり、図9は、図7の破線C−Cにおける半導体装置の断面図である。
図10A(a)〜(b)、図10B(c)〜(d)は、本発明の第5の実施の形態に係る半導体装置の製造方法を表す断面図である。図10A(a)〜(b)、図10B(c)〜(d)に示した断面は、図9に示した断面に対応する。
本発明の第5の実施の形態によれば、メタルリング13bの内側に反応物排出孔23を形成することにより、配線層11b、11cにおいてメタルリング13bに囲まれた領域にのみエアギャップ15を形成することができる。これにより、任意の配線層の任意の領域にのみエアギャップ15を形成することができる。
本発明の第6の実施の形態は、配線12ではなく、回路ブロック27a、27bをエアギャップ領域14に備える点において第5の実施の形態と異なる。他の部材の構成等、第5の実施の形態と同様の点については説明を省略する。
本発明の第6の実施の形態によれば、回路ブロック27a、27bの配線間容量の低減を重視する場合、これを実現することができる。
本発明の第7の実施の形態においては、上記各実施の形態における蓋材24の変形例について説明する。
本発明の第7の実施の形態によれば、蓋材28をSOD法、SOG法等の薬液が塗布時に高い粘性を有するような方法で形成することにより、反応物排出孔23の開口部近傍のみを埋めるような形状に形成することができる。これにより、エアギャップ15内に蓋材28が入り込むことを抑え、各層間絶縁膜、エアギャップ15等に含まれる水分をより効率的に外部に排出することができる。
なお、上記各実施例は一実施例に過ぎず、本発明はこれらに限定されずに、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。
Claims (4)
- 表面に半導体素子を有する半導体基板と、
前記半導体基板上に、ビアを含む第1の層間絶縁膜および前記ビアと接続した配線を含む第2の層間絶縁膜が積層して形成された層間絶縁膜と、
前記層間絶縁膜内に形成された、前記第2の層間絶縁膜内の閉ループ形状を有する配線を含む第1のメタルリングと、
前記層間絶縁膜内の前記第1のメタルリングの内側の領域に形成された第2のメタルリングと、
前記第2の層間絶縁膜内の前記第1のメタルリングの前記閉ループ形状を有する配線と前記第2のメタルリングの間の領域に形成されたエアギャップと、
を有することを特徴とする半導体装置。 - 前記層間絶縁膜内の前記第1のメタルリングと前記第2のメタルリングの間の領域に形成された配線は、前記層間絶縁膜の上層または下層の前記第1のメタルリングを含まない他の層間絶縁膜内に形成された配線を介して、前記第1のメタルリングの外側の領域に形成された回路に接続される、
ことを特徴とする請求項1に記載の半導体装置。 - 表面に半導体素子を有する半導体基板上に層間絶縁膜を形成する工程と、
前記層間絶縁膜内に第1のメタルリングおよび前記メタルリングの内側の領域に位置する第2のメタルリングを含む配線構造を形成する工程と、
前記第1のメタルリングと前記第2のメタルリングの間の前記層間絶縁膜の少なくとも一部を、前記層間絶縁膜の上層に形成された絶縁膜を通して露出させる反応物排出孔を形成する工程と、
前記第1のメタルリングと前記第2のメタルリングの間の前記層間絶縁膜をエッチングにより前記反応物排出孔を介して除去する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第1のメタルリングと前記第2のメタルリングの間の前記層間絶縁膜を除去する工程の後、前記反応物排出孔の少なくとも開口部近傍を埋めるように蓋材を形成する工程と、
を含むことを特徴とする請求項3に記載の半導体装置の製造方法。
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JP2007290071A JP4334589B2 (ja) | 2006-12-06 | 2007-11-07 | 半導体装置、およびその製造方法 |
US11/951,559 US7786589B2 (en) | 2006-12-06 | 2007-12-06 | Semiconductor device and method for manufacturing semiconductor device |
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DE4441898C1 (de) | 1994-11-24 | 1996-04-04 | Siemens Ag | Verfahren zur Herstellung eines Halbleiterbauelementes |
JPH08306775A (ja) | 1995-05-01 | 1996-11-22 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2962272B2 (ja) | 1997-04-18 | 1999-10-12 | 日本電気株式会社 | 半導体装置の製造方法 |
JP3501937B2 (ja) * | 1998-01-30 | 2004-03-02 | 富士通株式会社 | 半導体装置の製造方法 |
JP2001217312A (ja) | 2000-02-07 | 2001-08-10 | Sony Corp | 半導体装置およびその製造方法 |
US6645873B2 (en) | 2000-06-21 | 2003-11-11 | Asm Japan K.K. | Method for manufacturing a semiconductor device |
JP4436989B2 (ja) | 2001-05-23 | 2010-03-24 | パナソニック株式会社 | 半導体装置の製造方法 |
JP2003273210A (ja) | 2002-03-12 | 2003-09-26 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6747340B2 (en) * | 2002-03-15 | 2004-06-08 | Memx, Inc. | Multi-level shielded multi-conductor interconnect bus for MEMS |
US7042095B2 (en) * | 2002-03-29 | 2006-05-09 | Renesas Technology Corp. | Semiconductor device including an interconnect having copper as a main component |
JP4068868B2 (ja) | 2002-03-29 | 2008-03-26 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP4619705B2 (ja) | 2004-01-15 | 2011-01-26 | 株式会社東芝 | 半導体装置 |
JP2006019401A (ja) | 2004-06-30 | 2006-01-19 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US7977795B2 (en) | 2006-01-05 | 2011-07-12 | Kabushiki Kaisha Toshiba | Semiconductor device, method of fabricating the same, and pattern generating method |
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