JP4328616B2 - 半導体装置用のトレンチ構造 - Google Patents
半導体装置用のトレンチ構造 Download PDFInfo
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Description
本発明は、概して半導体装置に関する。具体的には、本発明は、半導体構造の性能を高めるのに用いることのできるトレンチ構造に関する。
本発明の様々な局面によると、一般に、分断(broken)トレンチ構造は、半導体装置の絶縁破壊特性を向上させる。たとえば、以下に詳しく説明するように、ショットキー障壁整流器が、本発明の分断トレンチ局面と一体化されると、先行技術の構造で実現可能なものと比べて、逆阻止能力が改善される。
まず図6Aを参照すると、本発明の一態様による、MOSトレンチ構造と一体化されたショットキー障壁整流器を含む半導体装置構造60が示されている。装置構造60は第1の金属層600を含んでおり、この上部に半導体層602が形成されている。半導体層602は、単一のシリコン層を含みうり、または、図6Aに示されているように、エピタキシャル層604(もしくは「ドリフト」層)およびより大量にドーピングされた基板606を含みうる。より大量にドーピングされた基板606と第1の金属層600は装置のオーム端子を構成している。装置構造60はまた、エピタキシャル層604に形成された複数の並列トレンチ612および周辺トレンチ614を含む、MOSトレンチ構造を含む。周辺トレンチ614は所定の寸法および並列トレンチ614からの所定の間隔を有しており、好ましい寸法および間隔は以下に示されている。周辺トレンチ614および並列トレンチ512は、誘電体616に裏打ちされている。誘電体に裏打ちされたこれらのトレンチには、たとえば、金属またはドーピングされたポリシリコンなどの導電材料(図6Aには示されていない)が満たされている。図6Aには示されていないが、装置構造の全面にわたって第2の金属層が形成されている。第2の金属層と、並列トレンチ612間に形成されたメサ618の上面との間の接合部に、金属/半導体障壁が形成されている。
Claims (12)
- 以下を含む、半導体装置と一体化されたMOSトレンチ構造:
半導体層;
各並列トレンチが端部、側壁、および底部によって規定され、隣接するそれぞれ2つの並列トレンチが、半導体装置を含むメサによって分離され、かつメサがメサ幅を有する、半導体層内に形成された非連続的な複数の並列トレンチ;
半導体層内に形成され、端部、側壁、および底部によって規定され、並列トレンチを少なくとも部分的に囲み、かつ、並列トレンチ-周辺トレンチ間隔の分、並列トレンチの端部から離して配置された部分を有する、周辺トレンチ;
並列トレンチおよび周辺トレンチを裏打ちする誘電材料;ならびに
誘電体に裏打ちされたトレンチを満たす導電材料。 - 並列トレンチ-周辺トレンチ間隔が、メサ幅の2分の1である、請求項1記載のMOSトレンチ構造。
- 半導体層が以下を含む、請求項1記載のMOSトレンチ構造:
基板;および
基板の第1の主面上に形成され、基板のドーピング濃度よりも低いドーピング濃度を有する、エピタキシャル成長した半導体層。 - 半導体層の反対側の第2の主面上に形成された第1の金属接触層をさらに含む、請求項3記載のMOSトレンチ構造。
- 半導体装置が、メサ上、ならびに、誘導体に裏打ちされ導電材料で満たされた並列トレンチおよび周辺トレンチ上に形成された第2の金属層をさらに含む、請求項4記載のMOSトレンチ構造。
- 半導体装置の絶縁破壊特性を向上させるために半導体装置と一体化されたMOSトレンチ構造であって、以下を含むMOSトレンチ構造:
基板;
基板の第1の主面上に形成された、エピタキシャル成長した半導体層;
各並列トレンチが端壁、側壁、および底部によって規定され、隣接するそれぞれ2つの並列トレンチが、メサ幅を有するメサによって分離され、半導体装置が、隣接するそれぞれ2つの並列トレンチの間にゲートを有し、かつゲートにバイアスがかかって半導体装置の電源がオンになった時に電流が半導体装置内を流れるようにゲートが構成されている、エピタキシャル成長した半導体層内に形成された非連続的な複数の並列トレンチ;
エピタキシャル成長した半導体層内に形成され、側壁および底部によって規定され、並列トレンチを少なくとも部分的に囲み、かつ、並列トレンチ-周辺トレンチ間隔の分、並列トレンチの端部から離して配置された部分を有する、周辺トレンチ;
並列トレンチおよび周辺トレンチを裏打ちする誘電材料;ならびに
誘電体に裏打ちされたトレンチを満たす導電材料。 - 半導体装置がショットキー障壁整流器であり、かつ第1および第2の金属接触層が、ショットキー障壁整流器用の陰極端子および陽極端子を含む、請求項5記載の構造。
- 並列トレンチ-周辺トレンチ間隔が、メサ幅の2分の1である、請求項6記載の構造。
- 無線周波数電界効果トランジスタ(RF FET)の絶縁破壊特性を向上させるためにRF FETと一体化されたMOSトレンチ構造であって、以下を含むMOSトレンチ構造:
第1の導電型を有するドレイン層;
ドレイン層の第1の主面上に形成され、かつ、ドーピング濃度は低いがドレイン層と同じ導電型を有する、エピタキシャル成長した半導体層;
ドレイン層の反対側の第2の主面上に形成された、第1の金属接触層;
各並列トレンチが端部、側壁、および底部によって規定され、互いに隣接する並列トレンチが、RF FETを含むメサによって分離され、RF FETが、ゲートにバイアスがかかってRF FETの電源がオンになった時に電流がソース領域とドレイン層の間を流れるように構成されたソース領域部分を覆うゲートを有する、エピタキシャル成長した半導体層内に形成された非連続的な複数の並列トレンチ;
エピタキシャル成長した半導体層内に形成され、側壁および底部によって規定され、並列トレンチを少なくとも部分的に囲み、かつ、並列トレンチ-周辺トレンチ間隔の分、並列トレンチの端部から離して配置された部分を有する、周辺トレンチ;
並列トレンチおよび周辺トレンチを裏打ちする誘電材料;ならびに
誘電体に裏打ちされたトレンチを満たす導電材料。 - RF FETが以下を含む、請求項9記載の構造:
メサ内のそれぞれ2つのウェル領域がギャップによって分離され、ソース領域が第1の導電型でありかつウェル領域内に形成され、ゲートが、各メサ内のギャップ部分上に形成された、メサの上部コーナーに形成された第2の導電型のウェル領域。 - 並列トレンチ-周辺トレンチ間隔が、メサ幅の2分の1である、請求項9記載の構造。
- 半導体装置が、隣接する並列トレンチ間のメサ内に形成された整流器であり、オン状態でバイアスがかかった時に電流がメサ内を流れるように整流器が構成されている、請求項1記載の構造。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/898,133 US6683363B2 (en) | 2001-07-03 | 2001-07-03 | Trench structure for semiconductor devices |
PCT/US2002/021185 WO2003005416A2 (en) | 2001-07-03 | 2002-07-03 | Trench structure for semiconductor devices |
Publications (3)
Publication Number | Publication Date |
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JP2004535064A JP2004535064A (ja) | 2004-11-18 |
JP2004535064A5 JP2004535064A5 (ja) | 2005-11-17 |
JP4328616B2 true JP4328616B2 (ja) | 2009-09-09 |
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Application Number | Title | Priority Date | Filing Date |
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JP2003511285A Expired - Fee Related JP4328616B2 (ja) | 2001-07-03 | 2002-07-03 | 半導体装置用のトレンチ構造 |
Country Status (6)
Country | Link |
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US (1) | US6683363B2 (ja) |
JP (1) | JP4328616B2 (ja) |
AU (1) | AU2002329197A1 (ja) |
DE (1) | DE10297021B4 (ja) |
TW (1) | TW550739B (ja) |
WO (1) | WO2003005416A2 (ja) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7786533B2 (en) * | 2001-09-07 | 2010-08-31 | Power Integrations, Inc. | High-voltage vertical transistor with edge termination structure |
JP3701227B2 (ja) * | 2001-10-30 | 2005-09-28 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US7638841B2 (en) | 2003-05-20 | 2009-12-29 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
JP4903055B2 (ja) * | 2003-12-30 | 2012-03-21 | フェアチャイルド・セミコンダクター・コーポレーション | パワー半導体デバイスおよびその製造方法 |
FR2879024A1 (fr) * | 2004-12-08 | 2006-06-09 | St Microelectronics Sa | Peripherie de composant unipolaire vertical |
US7535057B2 (en) * | 2005-05-24 | 2009-05-19 | Robert Kuo-Chang Yang | DMOS transistor with a poly-filled deep trench for improved performance |
US7595542B2 (en) | 2006-03-13 | 2009-09-29 | Fairchild Semiconductor Corporation | Periphery design for charge balance power devices |
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DE10297021B4 (de) | 2012-02-23 |
US6683363B2 (en) | 2004-01-27 |
DE10297021T5 (de) | 2004-08-05 |
WO2003005416A3 (en) | 2003-09-25 |
WO2003005416A2 (en) | 2003-01-16 |
US20030006452A1 (en) | 2003-01-09 |
JP2004535064A (ja) | 2004-11-18 |
AU2002329197A1 (en) | 2003-01-21 |
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